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8#include <linux/clk.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <sound/pcm.h>
15#include <sound/pcm_params.h>
16#include <linux/regmap.h>
17#include <sound/soc.h>
18#include <sound/soc-dai.h>
19#include "lpass-lpaif-reg.h"
20#include "lpass.h"
21
22#define LPASS_CPU_MAX_MI2S_LINES 4
23#define LPASS_CPU_I2S_SD0_MASK BIT(0)
24#define LPASS_CPU_I2S_SD1_MASK BIT(1)
25#define LPASS_CPU_I2S_SD2_MASK BIT(2)
26#define LPASS_CPU_I2S_SD3_MASK BIT(3)
27#define LPASS_CPU_I2S_SD0_1_MASK GENMASK(1, 0)
28#define LPASS_CPU_I2S_SD2_3_MASK GENMASK(3, 2)
29#define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0)
30#define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0)
31
32
33
34
35static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = {
36 { .channels = 4,
37 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL,
38 SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } },
39 { }
40};
41static int lpass_cpu_init_i2sctl_bitfields(struct device *dev,
42 struct lpaif_i2sctl *i2sctl, struct regmap *map)
43{
44 struct lpass_data *drvdata = dev_get_drvdata(dev);
45 struct lpass_variant *v = drvdata->variant;
46
47 i2sctl->loopback = devm_regmap_field_alloc(dev, map, v->loopback);
48 i2sctl->spken = devm_regmap_field_alloc(dev, map, v->spken);
49 i2sctl->spkmode = devm_regmap_field_alloc(dev, map, v->spkmode);
50 i2sctl->spkmono = devm_regmap_field_alloc(dev, map, v->spkmono);
51 i2sctl->micen = devm_regmap_field_alloc(dev, map, v->micen);
52 i2sctl->micmode = devm_regmap_field_alloc(dev, map, v->micmode);
53 i2sctl->micmono = devm_regmap_field_alloc(dev, map, v->micmono);
54 i2sctl->wssrc = devm_regmap_field_alloc(dev, map, v->wssrc);
55 i2sctl->bitwidth = devm_regmap_field_alloc(dev, map, v->bitwidth);
56
57 if (IS_ERR(i2sctl->loopback) || IS_ERR(i2sctl->spken) ||
58 IS_ERR(i2sctl->spkmode) || IS_ERR(i2sctl->spkmono) ||
59 IS_ERR(i2sctl->micen) || IS_ERR(i2sctl->micmode) ||
60 IS_ERR(i2sctl->micmono) || IS_ERR(i2sctl->wssrc) ||
61 IS_ERR(i2sctl->bitwidth))
62 return -EINVAL;
63
64 return 0;
65}
66
67static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
68 unsigned int freq, int dir)
69{
70 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
71 int ret;
72
73 ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
74 if (ret)
75 dev_err(dai->dev, "error setting mi2s osrclk to %u: %d\n",
76 freq, ret);
77
78 return ret;
79}
80
81static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
82 struct snd_soc_dai *dai)
83{
84 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
85 int ret;
86
87 ret = clk_prepare_enable(drvdata->mi2s_osr_clk[dai->driver->id]);
88 if (ret) {
89 dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
90 return ret;
91 }
92 ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
93 if (ret) {
94 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
95 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
96 return ret;
97 }
98 return 0;
99}
100
101static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
102 struct snd_soc_dai *dai)
103{
104 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
105 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
106 unsigned int id = dai->driver->id;
107
108 clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
109
110
111
112
113
114 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
115 regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_DISABLE);
116 else
117 regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_DISABLE);
118
119
120
121
122
123
124 if (drvdata->mi2s_was_prepared[dai->driver->id]) {
125 drvdata->mi2s_was_prepared[dai->driver->id] = false;
126 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
127 }
128
129 clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
130}
131
132static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
133 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
134{
135 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
136 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
137 unsigned int id = dai->driver->id;
138 snd_pcm_format_t format = params_format(params);
139 unsigned int channels = params_channels(params);
140 unsigned int rate = params_rate(params);
141 unsigned int mode;
142 unsigned int regval;
143 int bitwidth, ret;
144
145 bitwidth = snd_pcm_format_width(format);
146 if (bitwidth < 0) {
147 dev_err(dai->dev, "invalid bit width given: %d\n", bitwidth);
148 return bitwidth;
149 }
150
151 ret = regmap_fields_write(i2sctl->loopback, id,
152 LPAIF_I2SCTL_LOOPBACK_DISABLE);
153 if (ret) {
154 dev_err(dai->dev, "error updating loopback field: %d\n", ret);
155 return ret;
156 }
157
158 ret = regmap_fields_write(i2sctl->wssrc, id,
159 LPAIF_I2SCTL_WSSRC_INTERNAL);
160 if (ret) {
161 dev_err(dai->dev, "error updating wssrc field: %d\n", ret);
162 return ret;
163 }
164
165 switch (bitwidth) {
166 case 16:
167 regval = LPAIF_I2SCTL_BITWIDTH_16;
168 break;
169 case 24:
170 regval = LPAIF_I2SCTL_BITWIDTH_24;
171 break;
172 case 32:
173 regval = LPAIF_I2SCTL_BITWIDTH_32;
174 break;
175 default:
176 dev_err(dai->dev, "invalid bitwidth given: %d\n", bitwidth);
177 return -EINVAL;
178 }
179
180 ret = regmap_fields_write(i2sctl->bitwidth, id, regval);
181 if (ret) {
182 dev_err(dai->dev, "error updating bitwidth field: %d\n", ret);
183 return ret;
184 }
185
186 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
187 mode = drvdata->mi2s_playback_sd_mode[id];
188 else
189 mode = drvdata->mi2s_capture_sd_mode[id];
190
191 if (!mode) {
192 dev_err(dai->dev, "no line is assigned\n");
193 return -EINVAL;
194 }
195
196 switch (channels) {
197 case 1:
198 case 2:
199 switch (mode) {
200 case LPAIF_I2SCTL_MODE_QUAD01:
201 case LPAIF_I2SCTL_MODE_6CH:
202 case LPAIF_I2SCTL_MODE_8CH:
203 mode = LPAIF_I2SCTL_MODE_SD0;
204 break;
205 case LPAIF_I2SCTL_MODE_QUAD23:
206 mode = LPAIF_I2SCTL_MODE_SD2;
207 break;
208 }
209
210 break;
211 case 4:
212 if (mode < LPAIF_I2SCTL_MODE_QUAD01) {
213 dev_err(dai->dev, "cannot configure 4 channels with mode %d\n",
214 mode);
215 return -EINVAL;
216 }
217
218 switch (mode) {
219 case LPAIF_I2SCTL_MODE_6CH:
220 case LPAIF_I2SCTL_MODE_8CH:
221 mode = LPAIF_I2SCTL_MODE_QUAD01;
222 break;
223 }
224 break;
225 case 6:
226 if (mode < LPAIF_I2SCTL_MODE_6CH) {
227 dev_err(dai->dev, "cannot configure 6 channels with mode %d\n",
228 mode);
229 return -EINVAL;
230 }
231
232 switch (mode) {
233 case LPAIF_I2SCTL_MODE_8CH:
234 mode = LPAIF_I2SCTL_MODE_6CH;
235 break;
236 }
237 break;
238 case 8:
239 if (mode < LPAIF_I2SCTL_MODE_8CH) {
240 dev_err(dai->dev, "cannot configure 8 channels with mode %d\n",
241 mode);
242 return -EINVAL;
243 }
244 break;
245 default:
246 dev_err(dai->dev, "invalid channels given: %u\n", channels);
247 return -EINVAL;
248 }
249
250 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
251 ret = regmap_fields_write(i2sctl->spkmode, id,
252 LPAIF_I2SCTL_SPKMODE(mode));
253 if (ret) {
254 dev_err(dai->dev, "error writing to i2sctl spkr mode: %d\n",
255 ret);
256 return ret;
257 }
258 if (channels >= 2)
259 ret = regmap_fields_write(i2sctl->spkmono, id,
260 LPAIF_I2SCTL_SPKMONO_STEREO);
261 else
262 ret = regmap_fields_write(i2sctl->spkmono, id,
263 LPAIF_I2SCTL_SPKMONO_MONO);
264 } else {
265 ret = regmap_fields_write(i2sctl->micmode, id,
266 LPAIF_I2SCTL_MICMODE(mode));
267 if (ret) {
268 dev_err(dai->dev, "error writing to i2sctl mic mode: %d\n",
269 ret);
270 return ret;
271 }
272 if (channels >= 2)
273 ret = regmap_fields_write(i2sctl->micmono, id,
274 LPAIF_I2SCTL_MICMONO_STEREO);
275 else
276 ret = regmap_fields_write(i2sctl->micmono, id,
277 LPAIF_I2SCTL_MICMONO_MONO);
278 }
279
280 if (ret) {
281 dev_err(dai->dev, "error writing to i2sctl channels mode: %d\n",
282 ret);
283 return ret;
284 }
285
286 ret = clk_set_rate(drvdata->mi2s_bit_clk[id],
287 rate * bitwidth * 2);
288 if (ret) {
289 dev_err(dai->dev, "error setting mi2s bitclk to %u: %d\n",
290 rate * bitwidth * 2, ret);
291 return ret;
292 }
293
294 return 0;
295}
296
297static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
298 int cmd, struct snd_soc_dai *dai)
299{
300 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
301 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
302 unsigned int id = dai->driver->id;
303 int ret = -EINVAL;
304
305 switch (cmd) {
306 case SNDRV_PCM_TRIGGER_START:
307 case SNDRV_PCM_TRIGGER_RESUME:
308 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
309
310
311
312
313
314
315
316
317
318
319
320
321 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
322 ret = regmap_fields_write(i2sctl->spken, id,
323 LPAIF_I2SCTL_SPKEN_ENABLE);
324 } else {
325 ret = regmap_fields_write(i2sctl->micen, id,
326 LPAIF_I2SCTL_MICEN_ENABLE);
327 }
328 if (ret)
329 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
330 ret);
331
332 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
333 if (ret) {
334 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
335 clk_disable(drvdata->mi2s_osr_clk[id]);
336 return ret;
337 }
338 break;
339 case SNDRV_PCM_TRIGGER_STOP:
340 case SNDRV_PCM_TRIGGER_SUSPEND:
341 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
342
343
344
345
346 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
347 ret = regmap_fields_write(i2sctl->spken, id,
348 LPAIF_I2SCTL_SPKEN_DISABLE);
349 } else {
350 ret = regmap_fields_write(i2sctl->micen, id,
351 LPAIF_I2SCTL_MICEN_DISABLE);
352 }
353 if (ret)
354 dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
355 ret);
356
357 clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
358
359 break;
360 }
361
362 return ret;
363}
364
365static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
366 struct snd_soc_dai *dai)
367{
368 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
369 struct lpaif_i2sctl *i2sctl = drvdata->i2sctl;
370 unsigned int id = dai->driver->id;
371 int ret;
372
373
374
375
376
377
378
379 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
380 ret = regmap_fields_write(i2sctl->spken, id, LPAIF_I2SCTL_SPKEN_ENABLE);
381 else
382 ret = regmap_fields_write(i2sctl->micen, id, LPAIF_I2SCTL_MICEN_ENABLE);
383
384 if (ret) {
385 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
386 return ret;
387 }
388
389
390
391
392
393
394 if (!drvdata->mi2s_was_prepared[dai->driver->id]) {
395 ret = clk_enable(drvdata->mi2s_bit_clk[id]);
396 if (ret) {
397 dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
398 return ret;
399 }
400 drvdata->mi2s_was_prepared[dai->driver->id] = true;
401 }
402 return 0;
403}
404
405const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
406 .set_sysclk = lpass_cpu_daiops_set_sysclk,
407 .startup = lpass_cpu_daiops_startup,
408 .shutdown = lpass_cpu_daiops_shutdown,
409 .hw_params = lpass_cpu_daiops_hw_params,
410 .trigger = lpass_cpu_daiops_trigger,
411 .prepare = lpass_cpu_daiops_prepare,
412};
413EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
414
415int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd,
416 struct snd_soc_dai *dai)
417{
418 int ret;
419 struct snd_soc_dai_driver *drv = dai->driver;
420 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
421
422 if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) {
423 ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,
424 lpass_quad_chmaps, drv->playback.channels_max, 0,
425 NULL);
426 if (ret < 0)
427 return ret;
428 }
429
430 return 0;
431}
432EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new);
433
434int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
435{
436 struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
437 int ret;
438
439
440 ret = regmap_write(drvdata->lpaif_map,
441 LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
442 if (ret)
443 dev_err(dai->dev, "error writing to i2sctl reg: %d\n", ret);
444
445 return ret;
446}
447EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
448
449static int asoc_qcom_of_xlate_dai_name(struct snd_soc_component *component,
450 const struct of_phandle_args *args,
451 const char **dai_name)
452{
453 struct lpass_data *drvdata = snd_soc_component_get_drvdata(component);
454 struct lpass_variant *variant = drvdata->variant;
455 int id = args->args[0];
456 int ret = -EINVAL;
457 int i;
458
459 for (i = 0; i < variant->num_dai; i++) {
460 if (variant->dai_driver[i].id == id) {
461 *dai_name = variant->dai_driver[i].name;
462 ret = 0;
463 break;
464 }
465 }
466
467 return ret;
468}
469
470static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
471 .name = "lpass-cpu",
472 .of_xlate_dai_name = asoc_qcom_of_xlate_dai_name,
473};
474
475static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
476{
477 struct lpass_data *drvdata = dev_get_drvdata(dev);
478 struct lpass_variant *v = drvdata->variant;
479 int i;
480
481 for (i = 0; i < v->i2s_ports; ++i)
482 if (reg == LPAIF_I2SCTL_REG(v, i))
483 return true;
484
485 for (i = 0; i < v->irq_ports; ++i) {
486 if (reg == LPAIF_IRQEN_REG(v, i))
487 return true;
488 if (reg == LPAIF_IRQCLEAR_REG(v, i))
489 return true;
490 }
491
492 for (i = 0; i < v->rdma_channels; ++i) {
493 if (reg == LPAIF_RDMACTL_REG(v, i))
494 return true;
495 if (reg == LPAIF_RDMABASE_REG(v, i))
496 return true;
497 if (reg == LPAIF_RDMABUFF_REG(v, i))
498 return true;
499 if (reg == LPAIF_RDMAPER_REG(v, i))
500 return true;
501 }
502
503 for (i = 0; i < v->wrdma_channels; ++i) {
504 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
505 return true;
506 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
507 return true;
508 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
509 return true;
510 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
511 return true;
512 }
513
514 return false;
515}
516
517static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
518{
519 struct lpass_data *drvdata = dev_get_drvdata(dev);
520 struct lpass_variant *v = drvdata->variant;
521 int i;
522
523 for (i = 0; i < v->i2s_ports; ++i)
524 if (reg == LPAIF_I2SCTL_REG(v, i))
525 return true;
526
527 for (i = 0; i < v->irq_ports; ++i) {
528 if (reg == LPAIF_IRQCLEAR_REG(v, i))
529 return true;
530 if (reg == LPAIF_IRQEN_REG(v, i))
531 return true;
532 if (reg == LPAIF_IRQSTAT_REG(v, i))
533 return true;
534 }
535
536 for (i = 0; i < v->rdma_channels; ++i) {
537 if (reg == LPAIF_RDMACTL_REG(v, i))
538 return true;
539 if (reg == LPAIF_RDMABASE_REG(v, i))
540 return true;
541 if (reg == LPAIF_RDMABUFF_REG(v, i))
542 return true;
543 if (reg == LPAIF_RDMACURR_REG(v, i))
544 return true;
545 if (reg == LPAIF_RDMAPER_REG(v, i))
546 return true;
547 }
548
549 for (i = 0; i < v->wrdma_channels; ++i) {
550 if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
551 return true;
552 if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
553 return true;
554 if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
555 return true;
556 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
557 return true;
558 if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
559 return true;
560 }
561
562 return false;
563}
564
565static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
566{
567 struct lpass_data *drvdata = dev_get_drvdata(dev);
568 struct lpass_variant *v = drvdata->variant;
569 int i;
570
571 for (i = 0; i < v->irq_ports; ++i) {
572 if (reg == LPAIF_IRQCLEAR_REG(v, i))
573 return true;
574 if (reg == LPAIF_IRQSTAT_REG(v, i))
575 return true;
576 }
577
578 for (i = 0; i < v->rdma_channels; ++i)
579 if (reg == LPAIF_RDMACURR_REG(v, i))
580 return true;
581
582 for (i = 0; i < v->wrdma_channels; ++i)
583 if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
584 return true;
585
586 return false;
587}
588
589static struct regmap_config lpass_cpu_regmap_config = {
590 .name = "lpass_cpu",
591 .reg_bits = 32,
592 .reg_stride = 4,
593 .val_bits = 32,
594 .writeable_reg = lpass_cpu_regmap_writeable,
595 .readable_reg = lpass_cpu_regmap_readable,
596 .volatile_reg = lpass_cpu_regmap_volatile,
597 .cache_type = REGCACHE_FLAT,
598};
599
600static int lpass_hdmi_init_bitfields(struct device *dev, struct regmap *map)
601{
602 struct lpass_data *drvdata = dev_get_drvdata(dev);
603 struct lpass_variant *v = drvdata->variant;
604 unsigned int i;
605 struct lpass_hdmi_tx_ctl *tx_ctl;
606 struct regmap_field *legacy_en;
607 struct lpass_vbit_ctrl *vbit_ctl;
608 struct regmap_field *tx_parity;
609 struct lpass_dp_metadata_ctl *meta_ctl;
610 struct lpass_sstream_ctl *sstream_ctl;
611 struct regmap_field *ch_msb;
612 struct regmap_field *ch_lsb;
613 struct lpass_hdmitx_dmactl *tx_dmactl;
614 int rval;
615
616 tx_ctl = devm_kzalloc(dev, sizeof(*tx_ctl), GFP_KERNEL);
617 if (!tx_ctl)
618 return -ENOMEM;
619
620 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->soft_reset, tx_ctl->soft_reset);
621 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->force_reset, tx_ctl->force_reset);
622 drvdata->tx_ctl = tx_ctl;
623
624 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->legacy_en, legacy_en);
625 drvdata->hdmitx_legacy_en = legacy_en;
626
627 vbit_ctl = devm_kzalloc(dev, sizeof(*vbit_ctl), GFP_KERNEL);
628 if (!vbit_ctl)
629 return -ENOMEM;
630
631 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->replace_vbit, vbit_ctl->replace_vbit);
632 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->vbit_stream, vbit_ctl->vbit_stream);
633 drvdata->vbit_ctl = vbit_ctl;
634
635
636 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->calc_en, tx_parity);
637 drvdata->hdmitx_parity_calc_en = tx_parity;
638
639 meta_ctl = devm_kzalloc(dev, sizeof(*meta_ctl), GFP_KERNEL);
640 if (!meta_ctl)
641 return -ENOMEM;
642
643 rval = devm_regmap_field_bulk_alloc(dev, map, &meta_ctl->mute, &v->mute, 7);
644 if (rval)
645 return rval;
646 drvdata->meta_ctl = meta_ctl;
647
648 sstream_ctl = devm_kzalloc(dev, sizeof(*sstream_ctl), GFP_KERNEL);
649 if (!sstream_ctl)
650 return -ENOMEM;
651
652 rval = devm_regmap_field_bulk_alloc(dev, map, &sstream_ctl->sstream_en, &v->sstream_en, 9);
653 if (rval)
654 return rval;
655
656 drvdata->sstream_ctl = sstream_ctl;
657
658 for (i = 0; i < LPASS_MAX_HDMI_DMA_CHANNELS; i++) {
659 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->msb_bits, ch_msb);
660 drvdata->hdmitx_ch_msb[i] = ch_msb;
661
662 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->lsb_bits, ch_lsb);
663 drvdata->hdmitx_ch_lsb[i] = ch_lsb;
664
665 tx_dmactl = devm_kzalloc(dev, sizeof(*tx_dmactl), GFP_KERNEL);
666 if (!tx_dmactl)
667 return -ENOMEM;
668
669 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_chs, tx_dmactl->use_hw_chs);
670 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->use_hw_usr, tx_dmactl->use_hw_usr);
671 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_chs_sel, tx_dmactl->hw_chs_sel);
672 QCOM_REGMAP_FIELD_ALLOC(dev, map, v->hw_usr_sel, tx_dmactl->hw_usr_sel);
673 drvdata->hdmi_tx_dmactl[i] = tx_dmactl;
674 }
675 return 0;
676}
677
678static bool lpass_hdmi_regmap_writeable(struct device *dev, unsigned int reg)
679{
680 struct lpass_data *drvdata = dev_get_drvdata(dev);
681 struct lpass_variant *v = drvdata->variant;
682 int i;
683
684 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
685 return true;
686 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
687 return true;
688 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
689 return true;
690 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
691 return true;
692 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
693 return true;
694 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
695 return true;
696 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
697 return true;
698 if (reg == LPASS_HDMITX_APP_IRQCLEAR_REG(v))
699 return true;
700
701 for (i = 0; i < v->hdmi_rdma_channels; i++) {
702 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
703 return true;
704 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
705 return true;
706 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
707 return true;
708 }
709
710 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
711 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
712 return true;
713 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
714 return true;
715 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
716 return true;
717 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
718 return true;
719 }
720 return false;
721}
722
723static bool lpass_hdmi_regmap_readable(struct device *dev, unsigned int reg)
724{
725 struct lpass_data *drvdata = dev_get_drvdata(dev);
726 struct lpass_variant *v = drvdata->variant;
727 int i;
728
729 if (reg == LPASS_HDMI_TX_CTL_ADDR(v))
730 return true;
731 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
732 return true;
733 if (reg == LPASS_HDMI_TX_VBIT_CTL_ADDR(v))
734 return true;
735
736 for (i = 0; i < v->hdmi_rdma_channels; i++) {
737 if (reg == LPASS_HDMI_TX_CH_LSB_ADDR(v, i))
738 return true;
739 if (reg == LPASS_HDMI_TX_CH_MSB_ADDR(v, i))
740 return true;
741 if (reg == LPASS_HDMI_TX_DMA_ADDR(v, i))
742 return true;
743 }
744
745 if (reg == LPASS_HDMI_TX_PARITY_ADDR(v))
746 return true;
747 if (reg == LPASS_HDMI_TX_DP_ADDR(v))
748 return true;
749 if (reg == LPASS_HDMI_TX_SSTREAM_ADDR(v))
750 return true;
751 if (reg == LPASS_HDMITX_APP_IRQEN_REG(v))
752 return true;
753 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
754 return true;
755
756 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
757 if (reg == LPAIF_HDMI_RDMACTL_REG(v, i))
758 return true;
759 if (reg == LPAIF_HDMI_RDMABASE_REG(v, i))
760 return true;
761 if (reg == LPAIF_HDMI_RDMABUFF_REG(v, i))
762 return true;
763 if (reg == LPAIF_HDMI_RDMAPER_REG(v, i))
764 return true;
765 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
766 return true;
767 }
768
769 return false;
770}
771
772static bool lpass_hdmi_regmap_volatile(struct device *dev, unsigned int reg)
773{
774 struct lpass_data *drvdata = dev_get_drvdata(dev);
775 struct lpass_variant *v = drvdata->variant;
776 int i;
777
778 if (reg == LPASS_HDMITX_APP_IRQSTAT_REG(v))
779 return true;
780 if (reg == LPASS_HDMI_TX_LEGACY_ADDR(v))
781 return true;
782
783 for (i = 0; i < v->hdmi_rdma_channels; ++i) {
784 if (reg == LPAIF_HDMI_RDMACURR_REG(v, i))
785 return true;
786 }
787 return false;
788}
789
790static struct regmap_config lpass_hdmi_regmap_config = {
791 .name = "lpass_hdmi",
792 .reg_bits = 32,
793 .reg_stride = 4,
794 .val_bits = 32,
795 .writeable_reg = lpass_hdmi_regmap_writeable,
796 .readable_reg = lpass_hdmi_regmap_readable,
797 .volatile_reg = lpass_hdmi_regmap_volatile,
798 .cache_type = REGCACHE_FLAT,
799};
800
801static unsigned int of_lpass_cpu_parse_sd_lines(struct device *dev,
802 struct device_node *node,
803 const char *name)
804{
805 unsigned int lines[LPASS_CPU_MAX_MI2S_LINES];
806 unsigned int sd_line_mask = 0;
807 int num_lines, i;
808
809 num_lines = of_property_read_variable_u32_array(node, name, lines, 0,
810 LPASS_CPU_MAX_MI2S_LINES);
811 if (num_lines < 0)
812 return LPAIF_I2SCTL_MODE_NONE;
813
814 for (i = 0; i < num_lines; i++)
815 sd_line_mask |= BIT(lines[i]);
816
817 switch (sd_line_mask) {
818 case LPASS_CPU_I2S_SD0_MASK:
819 return LPAIF_I2SCTL_MODE_SD0;
820 case LPASS_CPU_I2S_SD1_MASK:
821 return LPAIF_I2SCTL_MODE_SD1;
822 case LPASS_CPU_I2S_SD2_MASK:
823 return LPAIF_I2SCTL_MODE_SD2;
824 case LPASS_CPU_I2S_SD3_MASK:
825 return LPAIF_I2SCTL_MODE_SD3;
826 case LPASS_CPU_I2S_SD0_1_MASK:
827 return LPAIF_I2SCTL_MODE_QUAD01;
828 case LPASS_CPU_I2S_SD2_3_MASK:
829 return LPAIF_I2SCTL_MODE_QUAD23;
830 case LPASS_CPU_I2S_SD0_1_2_MASK:
831 return LPAIF_I2SCTL_MODE_6CH;
832 case LPASS_CPU_I2S_SD0_1_2_3_MASK:
833 return LPAIF_I2SCTL_MODE_8CH;
834 default:
835 dev_err(dev, "Unsupported SD line mask: %#x\n", sd_line_mask);
836 return LPAIF_I2SCTL_MODE_NONE;
837 }
838}
839
840static void of_lpass_cpu_parse_dai_data(struct device *dev,
841 struct lpass_data *data)
842{
843 struct device_node *node;
844 int ret, id;
845
846
847 for (id = 0; id < data->variant->num_dai; id++) {
848 data->mi2s_playback_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
849 data->mi2s_capture_sd_mode[id] = LPAIF_I2SCTL_MODE_8CH;
850 }
851
852 for_each_child_of_node(dev->of_node, node) {
853 ret = of_property_read_u32(node, "reg", &id);
854 if (ret || id < 0) {
855 dev_err(dev, "valid dai id not found: %d\n", ret);
856 continue;
857 }
858 if (id == LPASS_DP_RX) {
859 data->hdmi_port_enable = 1;
860 } else {
861 data->mi2s_playback_sd_mode[id] =
862 of_lpass_cpu_parse_sd_lines(dev, node,
863 "qcom,playback-sd-lines");
864 data->mi2s_capture_sd_mode[id] =
865 of_lpass_cpu_parse_sd_lines(dev, node,
866 "qcom,capture-sd-lines");
867 }
868 }
869}
870
871int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
872{
873 struct lpass_data *drvdata;
874 struct device_node *dsp_of_node;
875 struct lpass_variant *variant;
876 struct device *dev = &pdev->dev;
877 const struct of_device_id *match;
878 int ret, i, dai_id;
879
880 dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
881 if (dsp_of_node) {
882 dev_err(dev, "DSP exists and holds audio resources\n");
883 return -EBUSY;
884 }
885
886 drvdata = devm_kzalloc(dev, sizeof(struct lpass_data), GFP_KERNEL);
887 if (!drvdata)
888 return -ENOMEM;
889 platform_set_drvdata(pdev, drvdata);
890
891 match = of_match_device(dev->driver->of_match_table, dev);
892 if (!match || !match->data)
893 return -EINVAL;
894
895 drvdata->variant = (struct lpass_variant *)match->data;
896 variant = drvdata->variant;
897
898 of_lpass_cpu_parse_dai_data(dev, drvdata);
899
900 drvdata->lpaif = devm_platform_ioremap_resource_byname(pdev, "lpass-lpaif");
901 if (IS_ERR(drvdata->lpaif))
902 return PTR_ERR(drvdata->lpaif);
903
904 lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
905 variant->wrdma_channels +
906 variant->wrdma_channel_start);
907
908 drvdata->lpaif_map = devm_regmap_init_mmio(dev, drvdata->lpaif,
909 &lpass_cpu_regmap_config);
910 if (IS_ERR(drvdata->lpaif_map)) {
911 dev_err(dev, "error initializing regmap: %ld\n",
912 PTR_ERR(drvdata->lpaif_map));
913 return PTR_ERR(drvdata->lpaif_map);
914 }
915
916 if (drvdata->hdmi_port_enable) {
917 drvdata->hdmiif = devm_platform_ioremap_resource_byname(pdev, "lpass-hdmiif");
918 if (IS_ERR(drvdata->hdmiif))
919 return PTR_ERR(drvdata->hdmiif);
920
921 lpass_hdmi_regmap_config.max_register = LPAIF_HDMI_RDMAPER_REG(variant,
922 variant->hdmi_rdma_channels - 1);
923 drvdata->hdmiif_map = devm_regmap_init_mmio(dev, drvdata->hdmiif,
924 &lpass_hdmi_regmap_config);
925 if (IS_ERR(drvdata->hdmiif_map)) {
926 dev_err(dev, "error initializing regmap: %ld\n",
927 PTR_ERR(drvdata->hdmiif_map));
928 return PTR_ERR(drvdata->hdmiif_map);
929 }
930 }
931
932 if (variant->init) {
933 ret = variant->init(pdev);
934 if (ret) {
935 dev_err(dev, "error initializing variant: %d\n", ret);
936 return ret;
937 }
938 }
939
940 for (i = 0; i < variant->num_dai; i++) {
941 dai_id = variant->dai_driver[i].id;
942 if (dai_id == LPASS_DP_RX)
943 continue;
944
945 drvdata->mi2s_osr_clk[dai_id] = devm_clk_get_optional(dev,
946 variant->dai_osr_clk_names[i]);
947 drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(dev,
948 variant->dai_bit_clk_names[i]);
949 if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
950 dev_err(dev,
951 "error getting %s: %ld\n",
952 variant->dai_bit_clk_names[i],
953 PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
954 return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
955 }
956 if (drvdata->mi2s_playback_sd_mode[dai_id] ==
957 LPAIF_I2SCTL_MODE_QUAD01) {
958 variant->dai_driver[dai_id].playback.channels_min = 4;
959 variant->dai_driver[dai_id].playback.channels_max = 4;
960 }
961 }
962
963
964 drvdata->i2sctl = devm_kzalloc(&pdev->dev, sizeof(struct lpaif_i2sctl),
965 GFP_KERNEL);
966
967
968 ret = lpass_cpu_init_i2sctl_bitfields(dev, drvdata->i2sctl,
969 drvdata->lpaif_map);
970 if (ret) {
971 dev_err(dev, "error init i2sctl field: %d\n", ret);
972 return ret;
973 }
974
975 if (drvdata->hdmi_port_enable) {
976 ret = lpass_hdmi_init_bitfields(dev, drvdata->hdmiif_map);
977 if (ret) {
978 dev_err(dev, "%s error hdmi init failed\n", __func__);
979 return ret;
980 }
981 }
982 ret = devm_snd_soc_register_component(dev,
983 &lpass_cpu_comp_driver,
984 variant->dai_driver,
985 variant->num_dai);
986 if (ret) {
987 dev_err(dev, "error registering cpu driver: %d\n", ret);
988 goto err;
989 }
990
991 ret = asoc_qcom_lpass_platform_register(pdev);
992 if (ret) {
993 dev_err(dev, "error registering platform driver: %d\n", ret);
994 goto err;
995 }
996
997err:
998 return ret;
999}
1000EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
1001
1002int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
1003{
1004 struct lpass_data *drvdata = platform_get_drvdata(pdev);
1005
1006 if (drvdata->variant->exit)
1007 drvdata->variant->exit(pdev);
1008
1009
1010 return 0;
1011}
1012EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
1013
1014void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev)
1015{
1016 struct lpass_data *drvdata = platform_get_drvdata(pdev);
1017
1018 if (drvdata->variant->exit)
1019 drvdata->variant->exit(pdev);
1020
1021}
1022EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_shutdown);
1023
1024MODULE_DESCRIPTION("QTi LPASS CPU Driver");
1025MODULE_LICENSE("GPL v2");
1026
