LXR linux/sound/soc/qcom/lpass.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
   4 *
   5 * lpass.h - Definitions for the QTi LPASS
   6 */
   7
   8#ifndef __LPASS_H__
   9#define __LPASS_H__
  10
  11#include <linux/clk.h>
  12#include <linux/compiler.h>
  13#include <linux/platform_device.h>
  14#include <linux/regmap.h>
  15#include <dt-bindings/sound/qcom,lpass.h>
  16#include <dt-bindings/sound/qcom,q6afe.h>
  17#include "lpass-hdmi.h"
  18
  19#define LPASS_AHBIX_CLOCK_FREQUENCY             131072000
  20#define LPASS_MAX_PORTS                 (DISPLAY_PORT_RX_7 + 1)
  21#define LPASS_MAX_MI2S_PORTS                    (8)
  22#define LPASS_MAX_DMA_CHANNELS                  (8)
  23#define LPASS_MAX_HDMI_DMA_CHANNELS             (4)
  24#define LPASS_MAX_CDC_DMA_CHANNELS              (8)
  25#define LPASS_MAX_VA_CDC_DMA_CHANNELS           (8)
  26#define LPASS_CDC_DMA_INTF_ONE_CHANNEL          (0x01)
  27#define LPASS_CDC_DMA_INTF_TWO_CHANNEL          (0x03)
  28#define LPASS_CDC_DMA_INTF_FOUR_CHANNEL         (0x0F)
  29#define LPASS_CDC_DMA_INTF_SIX_CHANNEL          (0x3F)
  30#define LPASS_CDC_DMA_INTF_EIGHT_CHANNEL        (0xFF)
  31
  32#define LPASS_ACTIVE_PDS                        (4)
  33#define LPASS_PROXY_PDS                 (8)
  34
  35#define QCOM_REGMAP_FIELD_ALLOC(d, m, f, mf)    \
  36        do { \
  37                mf = devm_regmap_field_alloc(d, m, f);     \
  38                if (IS_ERR(mf))                \
  39                        return -EINVAL;         \
  40        } while (0)
  41
  42static inline bool is_cdc_dma_port(int dai_id)
  43{
  44        switch (dai_id) {
  45        case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
  46        case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
  47        case LPASS_CDC_DMA_VA_TX0 ... LPASS_CDC_DMA_VA_TX8:
  48                return true;
  49        }
  50        return false;
  51}
  52
  53static inline bool is_rxtx_cdc_dma_port(int dai_id)
  54{
  55        switch (dai_id) {
  56        case LPASS_CDC_DMA_RX0 ... LPASS_CDC_DMA_RX9:
  57        case LPASS_CDC_DMA_TX0 ... LPASS_CDC_DMA_TX8:
  58                return true;
  59        }
  60        return false;
  61}
  62
  63struct lpaif_i2sctl {
  64        struct regmap_field *loopback;
  65        struct regmap_field *spken;
  66        struct regmap_field *spkmode;
  67        struct regmap_field *spkmono;
  68        struct regmap_field *micen;
  69        struct regmap_field *micmode;
  70        struct regmap_field *micmono;
  71        struct regmap_field *wssrc;
  72        struct regmap_field *bitwidth;
  73};
  74
  75
  76struct lpaif_dmactl {
  77        struct regmap_field *intf;
  78        struct regmap_field *bursten;
  79        struct regmap_field *wpscnt;
  80        struct regmap_field *fifowm;
  81        struct regmap_field *enable;
  82        struct regmap_field *dyncclk;
  83        struct regmap_field *burst8;
  84        struct regmap_field *burst16;
  85        struct regmap_field *dynburst;
  86        struct regmap_field *codec_enable;
  87        struct regmap_field *codec_pack;
  88        struct regmap_field *codec_intf;
  89        struct regmap_field *codec_fs_sel;
  90        struct regmap_field *codec_channel;
  91        struct regmap_field *codec_fs_delay;
  92};
  93
  94/* Both the CPU DAI and platform drivers will access this data */
  95struct lpass_data {
  96
  97        /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
  98        struct clk *ahbix_clk;
  99
 100        /* MI2S system clock */
 101        struct clk *mi2s_osr_clk[LPASS_MAX_MI2S_PORTS];
 102
 103        /* MI2S bit clock (derived from system clock by a divider */
 104        struct clk *mi2s_bit_clk[LPASS_MAX_MI2S_PORTS];
 105
 106        struct clk *codec_mem0;
 107        struct clk *codec_mem1;
 108        struct clk *codec_mem2;
 109        struct clk *va_mem0;
 110
 111        /* MI2S SD lines to use for playback/capture */
 112        unsigned int mi2s_playback_sd_mode[LPASS_MAX_MI2S_PORTS];
 113        unsigned int mi2s_capture_sd_mode[LPASS_MAX_MI2S_PORTS];
 114
 115        /* The state of MI2S prepare dai_ops was called */
 116        bool mi2s_was_prepared[LPASS_MAX_MI2S_PORTS];
 117
 118        int hdmi_port_enable;
 119        int codec_dma_enable;
 120
 121        /* low-power audio interface (LPAIF) registers */
 122        void __iomem *lpaif;
 123        void __iomem *hdmiif;
 124        void __iomem *rxtx_lpaif;
 125        void __iomem *va_lpaif;
 126
 127        u32 rxtx_cdc_dma_lpm_buf;
 128        u32 va_cdc_dma_lpm_buf;
 129
 130        /* regmap backed by the low-power audio interface (LPAIF) registers */
 131        struct regmap *lpaif_map;
 132        struct regmap *hdmiif_map;
 133        struct regmap *rxtx_lpaif_map;
 134        struct regmap *va_lpaif_map;
 135
 136        /* interrupts from the low-power audio interface (LPAIF) */
 137        int lpaif_irq;
 138        int hdmiif_irq;
 139        int rxtxif_irq;
 140        int vaif_irq;
 141
 142        /* SOC specific variations in the LPASS IP integration */
 143        const struct lpass_variant *variant;
 144
 145        /* bit map to keep track of static channel allocations */
 146        unsigned long dma_ch_bit_map;
 147        unsigned long hdmi_dma_ch_bit_map;
 148        unsigned long rxtx_dma_ch_bit_map;
 149        unsigned long va_dma_ch_bit_map;
 150
 151        /* used it for handling interrupt per dma channel */
 152        struct snd_pcm_substream *substream[LPASS_MAX_DMA_CHANNELS];
 153        struct snd_pcm_substream *hdmi_substream[LPASS_MAX_HDMI_DMA_CHANNELS];
 154        struct snd_pcm_substream *rxtx_substream[LPASS_MAX_CDC_DMA_CHANNELS];
 155        struct snd_pcm_substream *va_substream[LPASS_MAX_CDC_DMA_CHANNELS];
 156
 157        /* SOC specific clock list */
 158        struct clk_bulk_data *clks;
 159        int num_clks;
 160
 161        /* Regmap fields of I2SCTL & DMACTL registers bitfields */
 162        struct lpaif_i2sctl *i2sctl;
 163        struct lpaif_dmactl *rd_dmactl;
 164        struct lpaif_dmactl *wr_dmactl;
 165        struct lpaif_dmactl *hdmi_rd_dmactl;
 166
 167        /* Regmap fields of CODEC DMA CTRL registers */
 168        struct lpaif_dmactl *rxtx_rd_dmactl;
 169        struct lpaif_dmactl *rxtx_wr_dmactl;
 170        struct lpaif_dmactl *va_wr_dmactl;
 171
 172        /* Regmap fields of HDMI_CTRL registers*/
 173        struct regmap_field *hdmitx_legacy_en;
 174        struct regmap_field *hdmitx_parity_calc_en;
 175        struct regmap_field *hdmitx_ch_msb[LPASS_MAX_HDMI_DMA_CHANNELS];
 176        struct regmap_field *hdmitx_ch_lsb[LPASS_MAX_HDMI_DMA_CHANNELS];
 177        struct lpass_hdmi_tx_ctl *tx_ctl;
 178        struct lpass_vbit_ctrl *vbit_ctl;
 179        struct lpass_hdmitx_dmactl *hdmi_tx_dmactl[LPASS_MAX_HDMI_DMA_CHANNELS];
 180        struct lpass_dp_metadata_ctl *meta_ctl;
 181        struct lpass_sstream_ctl *sstream_ctl;
 182};
 183
 184/* Vairant data per each SOC */
 185struct lpass_variant {
 186        u32     irq_reg_base;
 187        u32     irq_reg_stride;
 188        u32     irq_ports;
 189        u32     rdma_reg_base;
 190        u32     rdma_reg_stride;
 191        u32     rdma_channels;
 192        u32     hdmi_rdma_reg_base;
 193        u32     hdmi_rdma_reg_stride;
 194        u32     hdmi_rdma_channels;
 195        u32     wrdma_reg_base;
 196        u32     wrdma_reg_stride;
 197        u32     wrdma_channels;
 198        u32     rxtx_irq_reg_base;
 199        u32     rxtx_irq_reg_stride;
 200        u32     rxtx_irq_ports;
 201        u32     rxtx_rdma_reg_base;
 202        u32     rxtx_rdma_reg_stride;
 203        u32     rxtx_rdma_channels;
 204        u32     rxtx_wrdma_reg_base;
 205        u32     rxtx_wrdma_reg_stride;
 206        u32     rxtx_wrdma_channels;
 207        u32     va_irq_reg_base;
 208        u32     va_irq_reg_stride;
 209        u32     va_irq_ports;
 210        u32     va_rdma_reg_base;
 211        u32     va_rdma_reg_stride;
 212        u32     va_rdma_channels;
 213        u32     va_wrdma_reg_base;
 214        u32     va_wrdma_reg_stride;
 215        u32     va_wrdma_channels;
 216        u32     i2sctrl_reg_base;
 217        u32     i2sctrl_reg_stride;
 218        u32     i2s_ports;
 219
 220        /* I2SCTL Register fields */
 221        struct reg_field loopback;
 222        struct reg_field spken;
 223        struct reg_field spkmode;
 224        struct reg_field spkmono;
 225        struct reg_field micen;
 226        struct reg_field micmode;
 227        struct reg_field micmono;
 228        struct reg_field wssrc;
 229        struct reg_field bitwidth;
 230
 231        u32     hdmi_irq_reg_base;
 232        u32     hdmi_irq_reg_stride;
 233        u32     hdmi_irq_ports;
 234
 235        /* HDMI specific controls */
 236        u32     hdmi_tx_ctl_addr;
 237        u32     hdmi_legacy_addr;
 238        u32     hdmi_vbit_addr;
 239        u32     hdmi_ch_lsb_addr;
 240        u32     hdmi_ch_msb_addr;
 241        u32     ch_stride;
 242        u32     hdmi_parity_addr;
 243        u32     hdmi_dmactl_addr;
 244        u32     hdmi_dma_stride;
 245        u32     hdmi_DP_addr;
 246        u32     hdmi_sstream_addr;
 247
 248        /* HDMI SSTREAM CTRL fields  */
 249        struct reg_field sstream_en;
 250        struct reg_field dma_sel;
 251        struct reg_field auto_bbit_en;
 252        struct reg_field layout;
 253        struct reg_field layout_sp;
 254        struct reg_field set_sp_on_en;
 255        struct reg_field dp_audio;
 256        struct reg_field dp_staffing_en;
 257        struct reg_field dp_sp_b_hw_en;
 258
 259        /* HDMI DP METADATA CTL fields */
 260        struct reg_field mute;
 261        struct reg_field as_sdp_cc;
 262        struct reg_field as_sdp_ct;
 263        struct reg_field aif_db4;
 264        struct reg_field frequency;
 265        struct reg_field mst_index;
 266        struct reg_field dptx_index;
 267
 268        /* HDMI TX CTRL fields */
 269        struct reg_field soft_reset;
 270        struct reg_field force_reset;
 271
 272        /* HDMI TX DMA CTRL */
 273        struct reg_field use_hw_chs;
 274        struct reg_field use_hw_usr;
 275        struct reg_field hw_chs_sel;
 276        struct reg_field hw_usr_sel;
 277
 278        /* HDMI VBIT CTRL */
 279        struct reg_field replace_vbit;
 280        struct reg_field vbit_stream;
 281
 282        /* HDMI TX LEGACY */
 283        struct reg_field legacy_en;
 284
 285        /* HDMI TX PARITY */
 286        struct reg_field calc_en;
 287
 288        /* HDMI CH LSB */
 289        struct reg_field lsb_bits;
 290
 291        /* HDMI CH MSB */
 292        struct reg_field msb_bits;
 293
 294        struct reg_field hdmi_rdma_bursten;
 295        struct reg_field hdmi_rdma_wpscnt;
 296        struct reg_field hdmi_rdma_fifowm;
 297        struct reg_field hdmi_rdma_enable;
 298        struct reg_field hdmi_rdma_dyncclk;
 299        struct reg_field hdmi_rdma_burst8;
 300        struct reg_field hdmi_rdma_burst16;
 301        struct reg_field hdmi_rdma_dynburst;
 302
 303        /* RD_DMA Register fields */
 304        struct reg_field rdma_intf;
 305        struct reg_field rdma_bursten;
 306        struct reg_field rdma_wpscnt;
 307        struct reg_field rdma_fifowm;
 308        struct reg_field rdma_enable;
 309        struct reg_field rdma_dyncclk;
 310
 311        /* WR_DMA Register fields */
 312        struct reg_field wrdma_intf;
 313        struct reg_field wrdma_bursten;
 314        struct reg_field wrdma_wpscnt;
 315        struct reg_field wrdma_fifowm;
 316        struct reg_field wrdma_enable;
 317        struct reg_field wrdma_dyncclk;
 318
 319        /* CDC RXTX RD_DMA */
 320        struct reg_field rxtx_rdma_intf;
 321        struct reg_field rxtx_rdma_bursten;
 322        struct reg_field rxtx_rdma_wpscnt;
 323        struct reg_field rxtx_rdma_fifowm;
 324        struct reg_field rxtx_rdma_enable;
 325        struct reg_field rxtx_rdma_dyncclk;
 326        struct reg_field rxtx_rdma_burst8;
 327        struct reg_field rxtx_rdma_burst16;
 328        struct reg_field rxtx_rdma_dynburst;
 329        struct reg_field rxtx_rdma_codec_enable;
 330        struct reg_field rxtx_rdma_codec_pack;
 331        struct reg_field rxtx_rdma_codec_intf;
 332        struct reg_field rxtx_rdma_codec_fs_sel;
 333        struct reg_field rxtx_rdma_codec_ch;
 334        struct reg_field rxtx_rdma_codec_fs_delay;
 335
 336        /* CDC RXTX WR_DMA */
 337        struct reg_field rxtx_wrdma_intf;
 338        struct reg_field rxtx_wrdma_bursten;
 339        struct reg_field rxtx_wrdma_wpscnt;
 340        struct reg_field rxtx_wrdma_fifowm;
 341        struct reg_field rxtx_wrdma_enable;
 342        struct reg_field rxtx_wrdma_dyncclk;
 343        struct reg_field rxtx_wrdma_burst8;
 344        struct reg_field rxtx_wrdma_burst16;
 345        struct reg_field rxtx_wrdma_dynburst;
 346        struct reg_field rxtx_wrdma_codec_enable;
 347        struct reg_field rxtx_wrdma_codec_pack;
 348        struct reg_field rxtx_wrdma_codec_intf;
 349        struct reg_field rxtx_wrdma_codec_fs_sel;
 350        struct reg_field rxtx_wrdma_codec_ch;
 351        struct reg_field rxtx_wrdma_codec_fs_delay;
 352
 353        /* CDC VA WR_DMA */
 354        struct reg_field va_wrdma_intf;
 355        struct reg_field va_wrdma_bursten;
 356        struct reg_field va_wrdma_wpscnt;
 357        struct reg_field va_wrdma_fifowm;
 358        struct reg_field va_wrdma_enable;
 359        struct reg_field va_wrdma_dyncclk;
 360        struct reg_field va_wrdma_burst8;
 361        struct reg_field va_wrdma_burst16;
 362        struct reg_field va_wrdma_dynburst;
 363        struct reg_field va_wrdma_codec_enable;
 364        struct reg_field va_wrdma_codec_pack;
 365        struct reg_field va_wrdma_codec_intf;
 366        struct reg_field va_wrdma_codec_fs_sel;
 367        struct reg_field va_wrdma_codec_ch;
 368        struct reg_field va_wrdma_codec_fs_delay;
 369
 370        /**
 371         * on SOCs like APQ8016 the channel control bits start
 372         * at different offset to ipq806x
 373         **/
 374        u32     dmactl_audif_start;
 375        u32     wrdma_channel_start;
 376        u32     rxtx_wrdma_channel_start;
 377        u32     va_wrdma_channel_start;
 378
 379        /* SOC specific initialization like clocks */
 380        int (*init)(struct platform_device *pdev);
 381        int (*exit)(struct platform_device *pdev);
 382        int (*alloc_dma_channel)(struct lpass_data *data, int direction, unsigned int dai_id);
 383        int (*free_dma_channel)(struct lpass_data *data, int ch, unsigned int dai_id);
 384
 385        /* SOC specific dais */
 386        struct snd_soc_dai_driver *dai_driver;
 387        int num_dai;
 388        const char * const *dai_osr_clk_names;
 389        const char * const *dai_bit_clk_names;
 390
 391        /* SOC specific clocks configuration */
 392        const char **clk_name;
 393        int num_clks;
 394};
 395
 396struct lpass_pcm_data {
 397        int dma_ch;
 398        int i2s_port;
 399};
 400
 401/* register the platform driver from the CPU DAI driver */
 402int asoc_qcom_lpass_platform_register(struct platform_device *pdev);
 403void asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev);
 404void asoc_qcom_lpass_cpu_platform_shutdown(struct platform_device *pdev);
 405int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev);
 406extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops;
 407extern const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops2;
 408extern const struct snd_soc_dai_ops asoc_qcom_lpass_cdc_dma_dai_ops;
 409
 410#endif /* __LPASS_H__ */
 411