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10#include <linux/module.h>
11#include <linux/mfd/syscon.h>
12#include <linux/delay.h>
13#include <linux/of_gpio.h>
14#include <linux/of_device.h>
15#include <linux/clk.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/spinlock.h>
19#include <sound/pcm_params.h>
20#include <sound/dmaengine_pcm.h>
21
22#include "rockchip_i2s.h"
23#include "rockchip_pcm.h"
24
25#define DRV_NAME "rockchip-i2s"
26
27struct rk_i2s_pins {
28 u32 reg_offset;
29 u32 shift;
30};
31
32struct rk_i2s_dev {
33 struct device *dev;
34
35 struct clk *hclk;
36 struct clk *mclk;
37
38 struct snd_dmaengine_dai_dma_data capture_dma_data;
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
40
41 struct regmap *regmap;
42 struct regmap *grf;
43
44 bool has_capture;
45 bool has_playback;
46
47
48
49
50
51
52 bool tx_start;
53 bool rx_start;
54 bool is_master_mode;
55 const struct rk_i2s_pins *pins;
56 unsigned int bclk_ratio;
57 spinlock_t lock;
58};
59
60static int i2s_runtime_suspend(struct device *dev)
61{
62 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
63
64 regcache_cache_only(i2s->regmap, true);
65 clk_disable_unprepare(i2s->mclk);
66
67 return 0;
68}
69
70static int i2s_runtime_resume(struct device *dev)
71{
72 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
73 int ret;
74
75 ret = clk_prepare_enable(i2s->mclk);
76 if (ret) {
77 dev_err(i2s->dev, "clock enable failed %d\n", ret);
78 return ret;
79 }
80
81 regcache_cache_only(i2s->regmap, false);
82 regcache_mark_dirty(i2s->regmap);
83
84 ret = regcache_sync(i2s->regmap);
85 if (ret)
86 clk_disable_unprepare(i2s->mclk);
87
88 return ret;
89}
90
91static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
92{
93 return snd_soc_dai_get_drvdata(dai);
94}
95
96static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
97{
98 unsigned int val = 0;
99 int retry = 10;
100
101 spin_lock(&i2s->lock);
102 if (on) {
103 regmap_update_bits(i2s->regmap, I2S_DMACR,
104 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
105
106 regmap_update_bits(i2s->regmap, I2S_XFER,
107 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
108 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
109
110 i2s->tx_start = true;
111 } else {
112 i2s->tx_start = false;
113
114 regmap_update_bits(i2s->regmap, I2S_DMACR,
115 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
116
117 if (!i2s->rx_start) {
118 regmap_update_bits(i2s->regmap, I2S_XFER,
119 I2S_XFER_TXS_START |
120 I2S_XFER_RXS_START,
121 I2S_XFER_TXS_STOP |
122 I2S_XFER_RXS_STOP);
123
124 udelay(150);
125 regmap_update_bits(i2s->regmap, I2S_CLR,
126 I2S_CLR_TXC | I2S_CLR_RXC,
127 I2S_CLR_TXC | I2S_CLR_RXC);
128
129 regmap_read(i2s->regmap, I2S_CLR, &val);
130
131
132 while (val) {
133 regmap_read(i2s->regmap, I2S_CLR, &val);
134 retry--;
135 if (!retry) {
136 dev_warn(i2s->dev, "fail to clear\n");
137 break;
138 }
139 }
140 }
141 }
142 spin_unlock(&i2s->lock);
143}
144
145static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
146{
147 unsigned int val = 0;
148 int retry = 10;
149
150 spin_lock(&i2s->lock);
151 if (on) {
152 regmap_update_bits(i2s->regmap, I2S_DMACR,
153 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
154
155 regmap_update_bits(i2s->regmap, I2S_XFER,
156 I2S_XFER_TXS_START | I2S_XFER_RXS_START,
157 I2S_XFER_TXS_START | I2S_XFER_RXS_START);
158
159 i2s->rx_start = true;
160 } else {
161 i2s->rx_start = false;
162
163 regmap_update_bits(i2s->regmap, I2S_DMACR,
164 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
165
166 if (!i2s->tx_start) {
167 regmap_update_bits(i2s->regmap, I2S_XFER,
168 I2S_XFER_TXS_START |
169 I2S_XFER_RXS_START,
170 I2S_XFER_TXS_STOP |
171 I2S_XFER_RXS_STOP);
172
173 udelay(150);
174 regmap_update_bits(i2s->regmap, I2S_CLR,
175 I2S_CLR_TXC | I2S_CLR_RXC,
176 I2S_CLR_TXC | I2S_CLR_RXC);
177
178 regmap_read(i2s->regmap, I2S_CLR, &val);
179
180
181 while (val) {
182 regmap_read(i2s->regmap, I2S_CLR, &val);
183 retry--;
184 if (!retry) {
185 dev_warn(i2s->dev, "fail to clear\n");
186 break;
187 }
188 }
189 }
190 }
191 spin_unlock(&i2s->lock);
192}
193
194static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
195 unsigned int fmt)
196{
197 struct rk_i2s_dev *i2s = to_info(cpu_dai);
198 unsigned int mask = 0, val = 0;
199 int ret = 0;
200
201 pm_runtime_get_sync(cpu_dai->dev);
202 mask = I2S_CKR_MSS_MASK;
203 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
204 case SND_SOC_DAIFMT_CBS_CFS:
205
206 val = I2S_CKR_MSS_MASTER;
207 i2s->is_master_mode = true;
208 break;
209 case SND_SOC_DAIFMT_CBM_CFM:
210 val = I2S_CKR_MSS_SLAVE;
211 i2s->is_master_mode = false;
212 break;
213 default:
214 ret = -EINVAL;
215 goto err_pm_put;
216 }
217
218 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
219
220 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
221 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
222 case SND_SOC_DAIFMT_NB_NF:
223 val = I2S_CKR_CKP_NORMAL |
224 I2S_CKR_TLP_NORMAL |
225 I2S_CKR_RLP_NORMAL;
226 break;
227 case SND_SOC_DAIFMT_NB_IF:
228 val = I2S_CKR_CKP_NORMAL |
229 I2S_CKR_TLP_INVERTED |
230 I2S_CKR_RLP_INVERTED;
231 break;
232 case SND_SOC_DAIFMT_IB_NF:
233 val = I2S_CKR_CKP_INVERTED |
234 I2S_CKR_TLP_NORMAL |
235 I2S_CKR_RLP_NORMAL;
236 break;
237 case SND_SOC_DAIFMT_IB_IF:
238 val = I2S_CKR_CKP_INVERTED |
239 I2S_CKR_TLP_INVERTED |
240 I2S_CKR_RLP_INVERTED;
241 break;
242 default:
243 ret = -EINVAL;
244 goto err_pm_put;
245 }
246
247 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
248
249 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
250 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
251 case SND_SOC_DAIFMT_RIGHT_J:
252 val = I2S_TXCR_IBM_RSJM;
253 break;
254 case SND_SOC_DAIFMT_LEFT_J:
255 val = I2S_TXCR_IBM_LSJM;
256 break;
257 case SND_SOC_DAIFMT_I2S:
258 val = I2S_TXCR_IBM_NORMAL;
259 break;
260 case SND_SOC_DAIFMT_DSP_A:
261 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
262 break;
263 case SND_SOC_DAIFMT_DSP_B:
264 val = I2S_TXCR_TFS_PCM;
265 break;
266 default:
267 ret = -EINVAL;
268 goto err_pm_put;
269 }
270
271 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
272
273 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
274 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
275 case SND_SOC_DAIFMT_RIGHT_J:
276 val = I2S_RXCR_IBM_RSJM;
277 break;
278 case SND_SOC_DAIFMT_LEFT_J:
279 val = I2S_RXCR_IBM_LSJM;
280 break;
281 case SND_SOC_DAIFMT_I2S:
282 val = I2S_RXCR_IBM_NORMAL;
283 break;
284 case SND_SOC_DAIFMT_DSP_A:
285 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
286 break;
287 case SND_SOC_DAIFMT_DSP_B:
288 val = I2S_RXCR_TFS_PCM;
289 break;
290 default:
291 ret = -EINVAL;
292 goto err_pm_put;
293 }
294
295 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
296
297err_pm_put:
298 pm_runtime_put(cpu_dai->dev);
299
300 return ret;
301}
302
303static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
304 struct snd_pcm_hw_params *params,
305 struct snd_soc_dai *dai)
306{
307 struct rk_i2s_dev *i2s = to_info(dai);
308 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
309 unsigned int val = 0;
310 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
311
312 if (i2s->is_master_mode) {
313 mclk_rate = clk_get_rate(i2s->mclk);
314 bclk_rate = i2s->bclk_ratio * params_rate(params);
315 if (!bclk_rate)
316 return -EINVAL;
317
318 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
319 div_lrck = bclk_rate / params_rate(params);
320 regmap_update_bits(i2s->regmap, I2S_CKR,
321 I2S_CKR_MDIV_MASK,
322 I2S_CKR_MDIV(div_bclk));
323
324 regmap_update_bits(i2s->regmap, I2S_CKR,
325 I2S_CKR_TSD_MASK |
326 I2S_CKR_RSD_MASK,
327 I2S_CKR_TSD(div_lrck) |
328 I2S_CKR_RSD(div_lrck));
329 }
330
331 switch (params_format(params)) {
332 case SNDRV_PCM_FORMAT_S8:
333 val |= I2S_TXCR_VDW(8);
334 break;
335 case SNDRV_PCM_FORMAT_S16_LE:
336 val |= I2S_TXCR_VDW(16);
337 break;
338 case SNDRV_PCM_FORMAT_S20_3LE:
339 val |= I2S_TXCR_VDW(20);
340 break;
341 case SNDRV_PCM_FORMAT_S24_LE:
342 val |= I2S_TXCR_VDW(24);
343 break;
344 case SNDRV_PCM_FORMAT_S32_LE:
345 val |= I2S_TXCR_VDW(32);
346 break;
347 default:
348 return -EINVAL;
349 }
350
351 switch (params_channels(params)) {
352 case 8:
353 val |= I2S_CHN_8;
354 break;
355 case 6:
356 val |= I2S_CHN_6;
357 break;
358 case 4:
359 val |= I2S_CHN_4;
360 break;
361 case 2:
362 val |= I2S_CHN_2;
363 break;
364 default:
365 dev_err(i2s->dev, "invalid channel: %d\n",
366 params_channels(params));
367 return -EINVAL;
368 }
369
370 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
371 regmap_update_bits(i2s->regmap, I2S_RXCR,
372 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
373 val);
374 else
375 regmap_update_bits(i2s->regmap, I2S_TXCR,
376 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
377 val);
378
379 if (!IS_ERR(i2s->grf) && i2s->pins) {
380 regmap_read(i2s->regmap, I2S_TXCR, &val);
381 val &= I2S_TXCR_CSR_MASK;
382
383 switch (val) {
384 case I2S_CHN_4:
385 val = I2S_IO_4CH_OUT_6CH_IN;
386 break;
387 case I2S_CHN_6:
388 val = I2S_IO_6CH_OUT_4CH_IN;
389 break;
390 case I2S_CHN_8:
391 val = I2S_IO_8CH_OUT_2CH_IN;
392 break;
393 default:
394 val = I2S_IO_2CH_OUT_8CH_IN;
395 break;
396 }
397
398 val <<= i2s->pins->shift;
399 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
400 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
401 }
402
403 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
404 I2S_DMACR_TDL(16));
405 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
406 I2S_DMACR_RDL(16));
407
408 val = I2S_CKR_TRCM_TXRX;
409 if (dai->driver->symmetric_rate && rtd->dai_link->symmetric_rate)
410 val = I2S_CKR_TRCM_TXONLY;
411
412 regmap_update_bits(i2s->regmap, I2S_CKR,
413 I2S_CKR_TRCM_MASK,
414 val);
415 return 0;
416}
417
418static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
419 int cmd, struct snd_soc_dai *dai)
420{
421 struct rk_i2s_dev *i2s = to_info(dai);
422 int ret = 0;
423
424 switch (cmd) {
425 case SNDRV_PCM_TRIGGER_START:
426 case SNDRV_PCM_TRIGGER_RESUME:
427 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
428 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
429 rockchip_snd_rxctrl(i2s, 1);
430 else
431 rockchip_snd_txctrl(i2s, 1);
432 break;
433 case SNDRV_PCM_TRIGGER_SUSPEND:
434 case SNDRV_PCM_TRIGGER_STOP:
435 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
436 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
437 rockchip_snd_rxctrl(i2s, 0);
438 else
439 rockchip_snd_txctrl(i2s, 0);
440 break;
441 default:
442 ret = -EINVAL;
443 break;
444 }
445
446 return ret;
447}
448
449static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
450 unsigned int ratio)
451{
452 struct rk_i2s_dev *i2s = to_info(dai);
453
454 i2s->bclk_ratio = ratio;
455
456 return 0;
457}
458
459static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
460 unsigned int freq, int dir)
461{
462 struct rk_i2s_dev *i2s = to_info(cpu_dai);
463 int ret;
464
465 if (freq == 0)
466 return 0;
467
468 ret = clk_set_rate(i2s->mclk, freq);
469 if (ret)
470 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
471
472 return ret;
473}
474
475static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
476{
477 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
478
479 snd_soc_dai_init_dma_data(dai,
480 i2s->has_playback ? &i2s->playback_dma_data : NULL,
481 i2s->has_capture ? &i2s->capture_dma_data : NULL);
482
483 return 0;
484}
485
486static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
487 .hw_params = rockchip_i2s_hw_params,
488 .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
489 .set_sysclk = rockchip_i2s_set_sysclk,
490 .set_fmt = rockchip_i2s_set_fmt,
491 .trigger = rockchip_i2s_trigger,
492};
493
494static struct snd_soc_dai_driver rockchip_i2s_dai = {
495 .probe = rockchip_i2s_dai_probe,
496 .ops = &rockchip_i2s_dai_ops,
497 .symmetric_rate = 1,
498};
499
500static const struct snd_soc_component_driver rockchip_i2s_component = {
501 .name = DRV_NAME,
502};
503
504static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
505{
506 switch (reg) {
507 case I2S_TXCR:
508 case I2S_RXCR:
509 case I2S_CKR:
510 case I2S_DMACR:
511 case I2S_INTCR:
512 case I2S_XFER:
513 case I2S_CLR:
514 case I2S_TXDR:
515 return true;
516 default:
517 return false;
518 }
519}
520
521static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
522{
523 switch (reg) {
524 case I2S_TXCR:
525 case I2S_RXCR:
526 case I2S_CKR:
527 case I2S_DMACR:
528 case I2S_INTCR:
529 case I2S_XFER:
530 case I2S_CLR:
531 case I2S_TXDR:
532 case I2S_RXDR:
533 case I2S_FIFOLR:
534 case I2S_INTSR:
535 return true;
536 default:
537 return false;
538 }
539}
540
541static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
542{
543 switch (reg) {
544 case I2S_INTSR:
545 case I2S_CLR:
546 case I2S_FIFOLR:
547 case I2S_TXDR:
548 case I2S_RXDR:
549 return true;
550 default:
551 return false;
552 }
553}
554
555static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
556{
557 switch (reg) {
558 case I2S_RXDR:
559 return true;
560 default:
561 return false;
562 }
563}
564
565static const struct reg_default rockchip_i2s_reg_defaults[] = {
566 {0x00, 0x0000000f},
567 {0x04, 0x0000000f},
568 {0x08, 0x00071f1f},
569 {0x10, 0x001f0000},
570 {0x14, 0x01f00000},
571};
572
573static const struct regmap_config rockchip_i2s_regmap_config = {
574 .reg_bits = 32,
575 .reg_stride = 4,
576 .val_bits = 32,
577 .max_register = I2S_RXDR,
578 .reg_defaults = rockchip_i2s_reg_defaults,
579 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
580 .writeable_reg = rockchip_i2s_wr_reg,
581 .readable_reg = rockchip_i2s_rd_reg,
582 .volatile_reg = rockchip_i2s_volatile_reg,
583 .precious_reg = rockchip_i2s_precious_reg,
584 .cache_type = REGCACHE_FLAT,
585};
586
587static const struct rk_i2s_pins rk3399_i2s_pins = {
588 .reg_offset = 0xe220,
589 .shift = 11,
590};
591
592static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
593 { .compatible = "rockchip,px30-i2s", },
594 { .compatible = "rockchip,rk1808-i2s", },
595 { .compatible = "rockchip,rk3036-i2s", },
596 { .compatible = "rockchip,rk3066-i2s", },
597 { .compatible = "rockchip,rk3128-i2s", },
598 { .compatible = "rockchip,rk3188-i2s", },
599 { .compatible = "rockchip,rk3228-i2s", },
600 { .compatible = "rockchip,rk3288-i2s", },
601 { .compatible = "rockchip,rk3308-i2s", },
602 { .compatible = "rockchip,rk3328-i2s", },
603 { .compatible = "rockchip,rk3366-i2s", },
604 { .compatible = "rockchip,rk3368-i2s", },
605 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
606 { .compatible = "rockchip,rv1126-i2s", },
607 {},
608};
609
610static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
611 struct snd_soc_dai_driver **dp)
612{
613 struct device_node *node = i2s->dev->of_node;
614 struct snd_soc_dai_driver *dai;
615 struct property *dma_names;
616 const char *dma_name;
617 unsigned int val;
618
619 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
620 if (!strcmp(dma_name, "tx"))
621 i2s->has_playback = true;
622 if (!strcmp(dma_name, "rx"))
623 i2s->has_capture = true;
624 }
625
626 dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
627 sizeof(*dai), GFP_KERNEL);
628 if (!dai)
629 return -ENOMEM;
630
631 if (i2s->has_playback) {
632 dai->playback.stream_name = "Playback";
633 dai->playback.channels_min = 2;
634 dai->playback.channels_max = 8;
635 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
636 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
637 SNDRV_PCM_FMTBIT_S16_LE |
638 SNDRV_PCM_FMTBIT_S20_3LE |
639 SNDRV_PCM_FMTBIT_S24_LE |
640 SNDRV_PCM_FMTBIT_S32_LE;
641
642 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
643 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
644 i2s->playback_dma_data.maxburst = 8;
645
646 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
647 if (val >= 2 && val <= 8)
648 dai->playback.channels_max = val;
649 }
650 }
651
652 if (i2s->has_capture) {
653 dai->capture.stream_name = "Capture";
654 dai->capture.channels_min = 2;
655 dai->capture.channels_max = 8;
656 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
657 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
658 SNDRV_PCM_FMTBIT_S16_LE |
659 SNDRV_PCM_FMTBIT_S20_3LE |
660 SNDRV_PCM_FMTBIT_S24_LE |
661 SNDRV_PCM_FMTBIT_S32_LE;
662
663 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
664 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
665 i2s->capture_dma_data.maxburst = 8;
666
667 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
668 if (val >= 2 && val <= 8)
669 dai->capture.channels_max = val;
670 }
671 }
672
673 if (dp)
674 *dp = dai;
675
676 return 0;
677}
678
679static int rockchip_i2s_probe(struct platform_device *pdev)
680{
681 struct device_node *node = pdev->dev.of_node;
682 const struct of_device_id *of_id;
683 struct rk_i2s_dev *i2s;
684 struct snd_soc_dai_driver *dai;
685 struct resource *res;
686 void __iomem *regs;
687 int ret;
688
689 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
690 if (!i2s)
691 return -ENOMEM;
692
693 spin_lock_init(&i2s->lock);
694 i2s->dev = &pdev->dev;
695
696 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
697 if (!IS_ERR(i2s->grf)) {
698 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
699 if (!of_id || !of_id->data)
700 return -EINVAL;
701
702 i2s->pins = of_id->data;
703 }
704
705
706 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
707 if (IS_ERR(i2s->hclk)) {
708 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
709 return PTR_ERR(i2s->hclk);
710 }
711 ret = clk_prepare_enable(i2s->hclk);
712 if (ret) {
713 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
714 return ret;
715 }
716
717 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
718 if (IS_ERR(i2s->mclk)) {
719 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
720 return PTR_ERR(i2s->mclk);
721 }
722
723 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
724 if (IS_ERR(regs))
725 return PTR_ERR(regs);
726
727 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
728 &rockchip_i2s_regmap_config);
729 if (IS_ERR(i2s->regmap)) {
730 dev_err(&pdev->dev,
731 "Failed to initialise managed register map\n");
732 return PTR_ERR(i2s->regmap);
733 }
734
735 i2s->bclk_ratio = 64;
736
737 dev_set_drvdata(&pdev->dev, i2s);
738
739 pm_runtime_enable(&pdev->dev);
740 if (!pm_runtime_enabled(&pdev->dev)) {
741 ret = i2s_runtime_resume(&pdev->dev);
742 if (ret)
743 goto err_pm_disable;
744 }
745
746 ret = rockchip_i2s_init_dai(i2s, res, &dai);
747 if (ret)
748 goto err_pm_disable;
749
750 ret = devm_snd_soc_register_component(&pdev->dev,
751 &rockchip_i2s_component,
752 dai, 1);
753
754 if (ret) {
755 dev_err(&pdev->dev, "Could not register DAI\n");
756 goto err_suspend;
757 }
758
759 ret = rockchip_pcm_platform_register(&pdev->dev);
760 if (ret) {
761 dev_err(&pdev->dev, "Could not register PCM\n");
762 goto err_suspend;
763 }
764
765 return 0;
766
767err_suspend:
768 if (!pm_runtime_status_suspended(&pdev->dev))
769 i2s_runtime_suspend(&pdev->dev);
770err_pm_disable:
771 pm_runtime_disable(&pdev->dev);
772
773 return ret;
774}
775
776static int rockchip_i2s_remove(struct platform_device *pdev)
777{
778 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
779
780 pm_runtime_disable(&pdev->dev);
781 if (!pm_runtime_status_suspended(&pdev->dev))
782 i2s_runtime_suspend(&pdev->dev);
783
784 clk_disable_unprepare(i2s->hclk);
785
786 return 0;
787}
788
789static const struct dev_pm_ops rockchip_i2s_pm_ops = {
790 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
791 NULL)
792};
793
794static struct platform_driver rockchip_i2s_driver = {
795 .probe = rockchip_i2s_probe,
796 .remove = rockchip_i2s_remove,
797 .driver = {
798 .name = DRV_NAME,
799 .of_match_table = of_match_ptr(rockchip_i2s_match),
800 .pm = &rockchip_i2s_pm_ops,
801 },
802};
803module_platform_driver(rockchip_i2s_driver);
804
805MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
806MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
807MODULE_LICENSE("GPL v2");
808MODULE_ALIAS("platform:" DRV_NAME);
809MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
810
