1
2
3
4
5
6
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/mfd/syscon.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <linux/reset.h>
17#include <linux/spinlock.h>
18#include <sound/dmaengine_pcm.h>
19#include <sound/pcm_params.h>
20
21#include "rockchip_i2s_tdm.h"
22
23#define DRV_NAME "rockchip-i2s-tdm"
24
25#define CH_GRP_MAX 4
26#define MULTIPLEX_CH_MAX 10
27
28#define TRCM_TXRX 0
29#define TRCM_TX 1
30#define TRCM_RX 2
31
32struct txrx_config {
33 u32 addr;
34 u32 reg;
35 u32 txonly;
36 u32 rxonly;
37};
38
39struct rk_i2s_soc_data {
40 u32 softrst_offset;
41 u32 grf_reg_offset;
42 u32 grf_shift;
43 int config_count;
44 const struct txrx_config *configs;
45 int (*init)(struct device *dev, u32 addr);
46};
47
48struct rk_i2s_tdm_dev {
49 struct device *dev;
50 struct clk *hclk;
51 struct clk *mclk_tx;
52 struct clk *mclk_rx;
53 struct regmap *regmap;
54 struct regmap *grf;
55 struct snd_dmaengine_dai_dma_data capture_dma_data;
56 struct snd_dmaengine_dai_dma_data playback_dma_data;
57 struct reset_control *tx_reset;
58 struct reset_control *rx_reset;
59 const struct rk_i2s_soc_data *soc_data;
60 bool is_master_mode;
61 bool io_multiplex;
62 bool tdm_mode;
63 unsigned int frame_width;
64 unsigned int clk_trcm;
65 unsigned int i2s_sdis[CH_GRP_MAX];
66 unsigned int i2s_sdos[CH_GRP_MAX];
67 int refcount;
68 spinlock_t lock;
69 bool has_playback;
70 bool has_capture;
71 struct snd_soc_dai_driver *dai;
72 unsigned int mclk_rx_freq;
73 unsigned int mclk_tx_freq;
74};
75
76static int to_ch_num(unsigned int val)
77{
78 switch (val) {
79 case I2S_CHN_4:
80 return 4;
81 case I2S_CHN_6:
82 return 6;
83 case I2S_CHN_8:
84 return 8;
85 default:
86 return 2;
87 }
88}
89
90static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
91{
92 clk_disable_unprepare(i2s_tdm->mclk_tx);
93 clk_disable_unprepare(i2s_tdm->mclk_rx);
94}
95
96
97
98
99
100
101
102
103
104
105
106static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm)
107{
108 int ret = 0;
109
110 ret = clk_prepare_enable(i2s_tdm->mclk_tx);
111 if (ret)
112 goto err_mclk_tx;
113 ret = clk_prepare_enable(i2s_tdm->mclk_rx);
114 if (ret)
115 goto err_mclk_rx;
116
117 return 0;
118
119err_mclk_rx:
120 clk_disable_unprepare(i2s_tdm->mclk_tx);
121err_mclk_tx:
122 return ret;
123}
124
125static int i2s_tdm_runtime_suspend(struct device *dev)
126{
127 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
128
129 regcache_cache_only(i2s_tdm->regmap, true);
130 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
131
132 clk_disable_unprepare(i2s_tdm->hclk);
133
134 return 0;
135}
136
137static int i2s_tdm_runtime_resume(struct device *dev)
138{
139 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
140 int ret;
141
142 ret = clk_prepare_enable(i2s_tdm->hclk);
143 if (ret)
144 goto err_hclk;
145
146 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
147 if (ret)
148 goto err_mclk;
149
150 regcache_cache_only(i2s_tdm->regmap, false);
151 regcache_mark_dirty(i2s_tdm->regmap);
152
153 ret = regcache_sync(i2s_tdm->regmap);
154 if (ret)
155 goto err_regcache;
156
157 return 0;
158
159err_regcache:
160 i2s_tdm_disable_unprepare_mclk(i2s_tdm);
161err_mclk:
162 clk_disable_unprepare(i2s_tdm->hclk);
163err_hclk:
164 return ret;
165}
166
167static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
168{
169 return snd_soc_dai_get_drvdata(dai);
170}
171
172
173
174
175
176static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
177{
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196 reset_control_assert(i2s_tdm->tx_reset);
197 reset_control_assert(i2s_tdm->rx_reset);
198 udelay(10);
199 reset_control_deassert(i2s_tdm->tx_reset);
200 reset_control_deassert(i2s_tdm->rx_reset);
201 udelay(10);
202}
203
204static void rockchip_snd_reset(struct reset_control *rc)
205{
206 reset_control_assert(rc);
207 udelay(10);
208 reset_control_deassert(rc);
209 udelay(10);
210}
211
212static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm,
213 unsigned int clr)
214{
215 unsigned int xfer_mask = 0;
216 unsigned int xfer_val = 0;
217 unsigned int val;
218 int retry = 10;
219 bool tx = clr & I2S_CLR_TXC;
220 bool rx = clr & I2S_CLR_RXC;
221
222 if (!(rx || tx))
223 return;
224
225 if (tx) {
226 xfer_mask = I2S_XFER_TXS_START;
227 xfer_val = I2S_XFER_TXS_STOP;
228 }
229 if (rx) {
230 xfer_mask |= I2S_XFER_RXS_START;
231 xfer_val |= I2S_XFER_RXS_STOP;
232 }
233
234 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val);
235 udelay(150);
236 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
237
238 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
239
240 while (val) {
241 udelay(15);
242 regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
243 retry--;
244 if (!retry) {
245 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n",
246 tx ? "tx" : "", rx ? "rx" : "");
247 if (rx && tx)
248 rockchip_snd_xfer_sync_reset(i2s_tdm);
249 else if (tx)
250 rockchip_snd_reset(i2s_tdm->tx_reset);
251 else if (rx)
252 rockchip_snd_reset(i2s_tdm->rx_reset);
253 break;
254 }
255 }
256}
257
258static inline void rockchip_enable_tde(struct regmap *regmap)
259{
260 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
261 I2S_DMACR_TDE_ENABLE);
262}
263
264static inline void rockchip_disable_tde(struct regmap *regmap)
265{
266 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE,
267 I2S_DMACR_TDE_DISABLE);
268}
269
270static inline void rockchip_enable_rde(struct regmap *regmap)
271{
272 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
273 I2S_DMACR_RDE_ENABLE);
274}
275
276static inline void rockchip_disable_rde(struct regmap *regmap)
277{
278 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE,
279 I2S_DMACR_RDE_DISABLE);
280}
281
282
283static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
284 struct snd_soc_dai *dai, int on)
285{
286 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
287 unsigned long flags;
288
289 spin_lock_irqsave(&i2s_tdm->lock, flags);
290 if (on) {
291 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
292 rockchip_enable_tde(i2s_tdm->regmap);
293 else
294 rockchip_enable_rde(i2s_tdm->regmap);
295
296 if (++i2s_tdm->refcount == 1) {
297 rockchip_snd_xfer_sync_reset(i2s_tdm);
298 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
299 I2S_XFER_TXS_START |
300 I2S_XFER_RXS_START,
301 I2S_XFER_TXS_START |
302 I2S_XFER_RXS_START);
303 }
304 } else {
305 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
306 rockchip_disable_tde(i2s_tdm->regmap);
307 else
308 rockchip_disable_rde(i2s_tdm->regmap);
309
310 if (--i2s_tdm->refcount == 0) {
311 rockchip_snd_xfer_clear(i2s_tdm,
312 I2S_CLR_TXC | I2S_CLR_RXC);
313 }
314 }
315 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
316}
317
318static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
319{
320 if (on) {
321 rockchip_enable_tde(i2s_tdm->regmap);
322
323 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
324 I2S_XFER_TXS_START,
325 I2S_XFER_TXS_START);
326 } else {
327 rockchip_disable_tde(i2s_tdm->regmap);
328
329 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC);
330 }
331}
332
333static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
334{
335 if (on) {
336 rockchip_enable_rde(i2s_tdm->regmap);
337
338 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
339 I2S_XFER_RXS_START,
340 I2S_XFER_RXS_START);
341 } else {
342 rockchip_disable_rde(i2s_tdm->regmap);
343
344 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC);
345 }
346}
347
348static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
349 unsigned int fmt)
350{
351 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
352 unsigned int mask, val, tdm_val, txcr_val, rxcr_val;
353 int ret;
354 bool is_tdm = i2s_tdm->tdm_mode;
355
356 ret = pm_runtime_resume_and_get(cpu_dai->dev);
357 if (ret < 0 && ret != -EACCES)
358 return ret;
359
360 mask = I2S_CKR_MSS_MASK;
361 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
362 case SND_SOC_DAIFMT_BP_FP:
363 val = I2S_CKR_MSS_MASTER;
364 i2s_tdm->is_master_mode = true;
365 break;
366 case SND_SOC_DAIFMT_BC_FC:
367 val = I2S_CKR_MSS_SLAVE;
368 i2s_tdm->is_master_mode = false;
369 break;
370 default:
371 ret = -EINVAL;
372 goto err_pm_put;
373 }
374
375 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
376
377 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK;
378 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
379 case SND_SOC_DAIFMT_NB_NF:
380 val = I2S_CKR_CKP_NORMAL |
381 I2S_CKR_TLP_NORMAL |
382 I2S_CKR_RLP_NORMAL;
383 break;
384 case SND_SOC_DAIFMT_NB_IF:
385 val = I2S_CKR_CKP_NORMAL |
386 I2S_CKR_TLP_INVERTED |
387 I2S_CKR_RLP_INVERTED;
388 break;
389 case SND_SOC_DAIFMT_IB_NF:
390 val = I2S_CKR_CKP_INVERTED |
391 I2S_CKR_TLP_NORMAL |
392 I2S_CKR_RLP_NORMAL;
393 break;
394 case SND_SOC_DAIFMT_IB_IF:
395 val = I2S_CKR_CKP_INVERTED |
396 I2S_CKR_TLP_INVERTED |
397 I2S_CKR_RLP_INVERTED;
398 break;
399 default:
400 ret = -EINVAL;
401 goto err_pm_put;
402 }
403
404 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val);
405
406 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
407 case SND_SOC_DAIFMT_RIGHT_J:
408 txcr_val = I2S_TXCR_IBM_RSJM;
409 rxcr_val = I2S_RXCR_IBM_RSJM;
410 break;
411 case SND_SOC_DAIFMT_LEFT_J:
412 txcr_val = I2S_TXCR_IBM_LSJM;
413 rxcr_val = I2S_RXCR_IBM_LSJM;
414 break;
415 case SND_SOC_DAIFMT_I2S:
416 txcr_val = I2S_TXCR_IBM_NORMAL;
417 rxcr_val = I2S_RXCR_IBM_NORMAL;
418 break;
419 case SND_SOC_DAIFMT_DSP_A:
420 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
421 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
422 break;
423 case SND_SOC_DAIFMT_DSP_B:
424 txcr_val = I2S_TXCR_TFS_PCM;
425 rxcr_val = I2S_RXCR_TFS_PCM;
426 break;
427 default:
428 ret = -EINVAL;
429 goto err_pm_put;
430 }
431
432 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
433 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val);
434
435 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
436 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val);
437
438 if (is_tdm) {
439 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
440 case SND_SOC_DAIFMT_RIGHT_J:
441 val = I2S_TXCR_TFS_TDM_I2S;
442 tdm_val = TDM_SHIFT_CTRL(2);
443 break;
444 case SND_SOC_DAIFMT_LEFT_J:
445 val = I2S_TXCR_TFS_TDM_I2S;
446 tdm_val = TDM_SHIFT_CTRL(1);
447 break;
448 case SND_SOC_DAIFMT_I2S:
449 val = I2S_TXCR_TFS_TDM_I2S;
450 tdm_val = TDM_SHIFT_CTRL(0);
451 break;
452 case SND_SOC_DAIFMT_DSP_A:
453 val = I2S_TXCR_TFS_TDM_PCM;
454 tdm_val = TDM_SHIFT_CTRL(2);
455 break;
456 case SND_SOC_DAIFMT_DSP_B:
457 val = I2S_TXCR_TFS_TDM_PCM;
458 tdm_val = TDM_SHIFT_CTRL(4);
459 break;
460 default:
461 ret = -EINVAL;
462 goto err_pm_put;
463 }
464
465 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1);
466 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME;
467
468 mask = I2S_TXCR_TFS_MASK;
469 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val);
470 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val);
471
472 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK |
473 TDM_SHIFT_CTRL_MSK;
474 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
475 mask, tdm_val);
476 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
477 mask, tdm_val);
478 }
479
480err_pm_put:
481 pm_runtime_put(cpu_dai->dev);
482
483 return ret;
484}
485
486static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
487 struct rk_i2s_tdm_dev *i2s_tdm)
488{
489 int stream;
490
491 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
492 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
493 rockchip_disable_tde(i2s_tdm->regmap);
494 else
495 rockchip_disable_rde(i2s_tdm->regmap);
496
497 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC);
498}
499
500static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
501 struct rk_i2s_tdm_dev *i2s_tdm)
502{
503 int stream;
504
505 stream = SNDRV_PCM_STREAM_LAST - substream->stream;
506 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
507 rockchip_enable_tde(i2s_tdm->regmap);
508 else
509 rockchip_enable_rde(i2s_tdm->regmap);
510
511 regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
512 I2S_XFER_TXS_START |
513 I2S_XFER_RXS_START,
514 I2S_XFER_TXS_START |
515 I2S_XFER_RXS_START);
516}
517
518static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream,
519 struct snd_soc_dai *dai)
520{
521 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
522 int usable_chs = MULTIPLEX_CH_MAX;
523 unsigned int val = 0;
524
525 if (!i2s_tdm->io_multiplex)
526 return 0;
527
528 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
529 dev_err(i2s_tdm->dev,
530 "io multiplex not supported for this device\n");
531 return -EINVAL;
532 }
533
534 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
535 struct snd_pcm_str *playback_str =
536 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
537
538 if (playback_str->substream_opened) {
539 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
540 val &= I2S_TXCR_CSR_MASK;
541 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
542 }
543
544 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
545 val &= I2S_RXCR_CSR_MASK;
546
547 if (to_ch_num(val) > usable_chs) {
548 dev_err(i2s_tdm->dev,
549 "Capture channels (%d) > usable channels (%d)\n",
550 to_ch_num(val), usable_chs);
551 return -EINVAL;
552 }
553
554 } else {
555 struct snd_pcm_str *capture_str =
556 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
557
558 if (capture_str->substream_opened) {
559 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val);
560 val &= I2S_RXCR_CSR_MASK;
561 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val);
562 }
563
564 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
565 val &= I2S_TXCR_CSR_MASK;
566
567 if (to_ch_num(val) > usable_chs) {
568 dev_err(i2s_tdm->dev,
569 "Playback channels (%d) > usable channels (%d)\n",
570 to_ch_num(val), usable_chs);
571 return -EINVAL;
572 }
573 }
574
575 val <<= i2s_tdm->soc_data->grf_shift;
576 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16;
577 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val);
578
579 return 0;
580}
581
582static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
583 struct snd_soc_dai *dai,
584 unsigned int div_bclk,
585 unsigned int div_lrck,
586 unsigned int fmt)
587{
588 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
589 unsigned long flags;
590
591 if (!i2s_tdm->clk_trcm)
592 return 0;
593
594 spin_lock_irqsave(&i2s_tdm->lock, flags);
595 if (i2s_tdm->refcount)
596 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
597
598 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
599 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
600 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk));
601 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
602 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
603 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck));
604
605 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
606 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
607 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
608 fmt);
609 else
610 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
611 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
612 fmt);
613
614 if (i2s_tdm->refcount)
615 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
616 spin_unlock_irqrestore(&i2s_tdm->lock, flags);
617
618 return 0;
619}
620
621static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream,
622 unsigned int freq, int dir)
623{
624 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai);
625
626 if (i2s_tdm->clk_trcm) {
627 i2s_tdm->mclk_tx_freq = freq;
628 i2s_tdm->mclk_rx_freq = freq;
629 } else {
630 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
631 i2s_tdm->mclk_tx_freq = freq;
632 else
633 i2s_tdm->mclk_rx_freq = freq;
634 }
635
636 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n",
637 stream ? "rx" : "tx", freq);
638
639 return 0;
640}
641
642static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream,
643 struct snd_pcm_hw_params *params,
644 struct snd_soc_dai *dai)
645{
646 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
647 unsigned int val = 0;
648 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
649 int err;
650
651 if (i2s_tdm->is_master_mode) {
652 struct clk *mclk;
653
654 if (i2s_tdm->clk_trcm == TRCM_TX) {
655 mclk = i2s_tdm->mclk_tx;
656 mclk_rate = i2s_tdm->mclk_tx_freq;
657 } else if (i2s_tdm->clk_trcm == TRCM_RX) {
658 mclk = i2s_tdm->mclk_rx;
659 mclk_rate = i2s_tdm->mclk_rx_freq;
660 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
661 mclk = i2s_tdm->mclk_tx;
662 mclk_rate = i2s_tdm->mclk_tx_freq;
663 } else {
664 mclk = i2s_tdm->mclk_rx;
665 mclk_rate = i2s_tdm->mclk_rx_freq;
666 }
667
668 err = clk_set_rate(mclk, mclk_rate);
669 if (err)
670 return err;
671
672 mclk_rate = clk_get_rate(mclk);
673 bclk_rate = i2s_tdm->frame_width * params_rate(params);
674 if (!bclk_rate)
675 return -EINVAL;
676
677 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
678 div_lrck = bclk_rate / params_rate(params);
679 }
680
681 switch (params_format(params)) {
682 case SNDRV_PCM_FORMAT_S8:
683 val |= I2S_TXCR_VDW(8);
684 break;
685 case SNDRV_PCM_FORMAT_S16_LE:
686 val |= I2S_TXCR_VDW(16);
687 break;
688 case SNDRV_PCM_FORMAT_S20_3LE:
689 val |= I2S_TXCR_VDW(20);
690 break;
691 case SNDRV_PCM_FORMAT_S24_LE:
692 val |= I2S_TXCR_VDW(24);
693 break;
694 case SNDRV_PCM_FORMAT_S32_LE:
695 val |= I2S_TXCR_VDW(32);
696 break;
697 default:
698 return -EINVAL;
699 }
700
701 switch (params_channels(params)) {
702 case 8:
703 val |= I2S_CHN_8;
704 break;
705 case 6:
706 val |= I2S_CHN_6;
707 break;
708 case 4:
709 val |= I2S_CHN_4;
710 break;
711 case 2:
712 val |= I2S_CHN_2;
713 break;
714 default:
715 return -EINVAL;
716 }
717
718 if (i2s_tdm->clk_trcm) {
719 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
720 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
721 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
722 I2S_CLKDIV_TXM_MASK,
723 I2S_CLKDIV_TXM(div_bclk));
724 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
725 I2S_CKR_TSD_MASK,
726 I2S_CKR_TSD(div_lrck));
727 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
728 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
729 val);
730 } else {
731 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
732 I2S_CLKDIV_RXM_MASK,
733 I2S_CLKDIV_RXM(div_bclk));
734 regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
735 I2S_CKR_RSD_MASK,
736 I2S_CKR_RSD(div_lrck));
737 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
738 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
739 val);
740 }
741
742 return rockchip_i2s_io_multiplex(substream, dai);
743}
744
745static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream,
746 int cmd, struct snd_soc_dai *dai)
747{
748 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
749
750 switch (cmd) {
751 case SNDRV_PCM_TRIGGER_START:
752 case SNDRV_PCM_TRIGGER_RESUME:
753 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
754 if (i2s_tdm->clk_trcm)
755 rockchip_snd_txrxctrl(substream, dai, 1);
756 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
757 rockchip_snd_rxctrl(i2s_tdm, 1);
758 else
759 rockchip_snd_txctrl(i2s_tdm, 1);
760 break;
761 case SNDRV_PCM_TRIGGER_SUSPEND:
762 case SNDRV_PCM_TRIGGER_STOP:
763 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
764 if (i2s_tdm->clk_trcm)
765 rockchip_snd_txrxctrl(substream, dai, 0);
766 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
767 rockchip_snd_rxctrl(i2s_tdm, 0);
768 else
769 rockchip_snd_txctrl(i2s_tdm, 0);
770 break;
771 default:
772 return -EINVAL;
773 }
774
775 return 0;
776}
777
778static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
779{
780 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
781
782 if (i2s_tdm->has_capture)
783 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data);
784 if (i2s_tdm->has_playback)
785 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data);
786
787 return 0;
788}
789
790static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai,
791 unsigned int tx_mask, unsigned int rx_mask,
792 int slots, int slot_width)
793{
794 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
795 unsigned int mask, val;
796
797 i2s_tdm->tdm_mode = true;
798 i2s_tdm->frame_width = slots * slot_width;
799 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK;
800 val = TDM_SLOT_BIT_WIDTH(slot_width) |
801 TDM_FRAME_WIDTH(slots * slot_width);
802 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR,
803 mask, val);
804 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR,
805 mask, val);
806
807 return 0;
808}
809
810static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai,
811 unsigned int ratio)
812{
813 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
814
815 if (ratio < 32 || ratio > 512 || ratio % 2 == 1)
816 return -EINVAL;
817
818 i2s_tdm->frame_width = ratio;
819
820 return 0;
821}
822
823static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
824 .probe = rockchip_i2s_tdm_dai_probe,
825 .hw_params = rockchip_i2s_tdm_hw_params,
826 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio,
827 .set_fmt = rockchip_i2s_tdm_set_fmt,
828 .set_sysclk = rockchip_i2s_tdm_set_sysclk,
829 .set_tdm_slot = rockchip_dai_tdm_slot,
830 .trigger = rockchip_i2s_tdm_trigger,
831};
832
833static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
834 .name = DRV_NAME,
835 .legacy_dai_naming = 1,
836};
837
838static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
839{
840 switch (reg) {
841 case I2S_TXCR:
842 case I2S_RXCR:
843 case I2S_CKR:
844 case I2S_DMACR:
845 case I2S_INTCR:
846 case I2S_XFER:
847 case I2S_CLR:
848 case I2S_TXDR:
849 case I2S_TDM_TXCR:
850 case I2S_TDM_RXCR:
851 case I2S_CLKDIV:
852 return true;
853 default:
854 return false;
855 }
856}
857
858static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg)
859{
860 switch (reg) {
861 case I2S_TXCR:
862 case I2S_RXCR:
863 case I2S_CKR:
864 case I2S_DMACR:
865 case I2S_INTCR:
866 case I2S_XFER:
867 case I2S_CLR:
868 case I2S_TXDR:
869 case I2S_RXDR:
870 case I2S_TXFIFOLR:
871 case I2S_INTSR:
872 case I2S_RXFIFOLR:
873 case I2S_TDM_TXCR:
874 case I2S_TDM_RXCR:
875 case I2S_CLKDIV:
876 return true;
877 default:
878 return false;
879 }
880}
881
882static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg)
883{
884 switch (reg) {
885 case I2S_TXFIFOLR:
886 case I2S_INTSR:
887 case I2S_CLR:
888 case I2S_TXDR:
889 case I2S_RXDR:
890 case I2S_RXFIFOLR:
891 return true;
892 default:
893 return false;
894 }
895}
896
897static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg)
898{
899 if (reg == I2S_RXDR)
900 return true;
901 return false;
902}
903
904static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = {
905 {0x00, 0x7200000f},
906 {0x04, 0x01c8000f},
907 {0x08, 0x00001f1f},
908 {0x10, 0x001f0000},
909 {0x14, 0x01f00000},
910 {0x30, 0x00003eff},
911 {0x34, 0x00003eff},
912 {0x38, 0x00000707},
913};
914
915static const struct regmap_config rockchip_i2s_tdm_regmap_config = {
916 .reg_bits = 32,
917 .reg_stride = 4,
918 .val_bits = 32,
919 .max_register = I2S_CLKDIV,
920 .reg_defaults = rockchip_i2s_tdm_reg_defaults,
921 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults),
922 .writeable_reg = rockchip_i2s_tdm_wr_reg,
923 .readable_reg = rockchip_i2s_tdm_rd_reg,
924 .volatile_reg = rockchip_i2s_tdm_volatile_reg,
925 .precious_reg = rockchip_i2s_tdm_precious_reg,
926 .cache_type = REGCACHE_FLAT,
927};
928
929static int common_soc_init(struct device *dev, u32 addr)
930{
931 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
932 const struct txrx_config *configs = i2s_tdm->soc_data->configs;
933 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
934 int i;
935
936 if (trcm == TRCM_TXRX)
937 return 0;
938
939 if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
940 dev_err(i2s_tdm->dev,
941 "no grf present but non-txrx TRCM specified\n");
942 return -EINVAL;
943 }
944
945 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
946 if (addr != configs[i].addr)
947 continue;
948 reg = configs[i].reg;
949 if (trcm == TRCM_TX)
950 val = configs[i].txonly;
951 else
952 val = configs[i].rxonly;
953
954 if (reg)
955 regmap_write(i2s_tdm->grf, reg, val);
956 }
957
958 return 0;
959}
960
961static const struct txrx_config px30_txrx_config[] = {
962 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY },
963};
964
965static const struct txrx_config rk1808_txrx_config[] = {
966 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY },
967};
968
969static const struct txrx_config rk3308_txrx_config[] = {
970 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY },
971 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY },
972};
973
974static const struct txrx_config rk3568_txrx_config[] = {
975 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY },
976 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE },
977 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE },
978 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY },
979 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY },
980 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE },
981};
982
983static const struct txrx_config rv1126_txrx_config[] = {
984 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY },
985};
986
987static const struct rk_i2s_soc_data px30_i2s_soc_data = {
988 .softrst_offset = 0x0300,
989 .configs = px30_txrx_config,
990 .config_count = ARRAY_SIZE(px30_txrx_config),
991 .init = common_soc_init,
992};
993
994static const struct rk_i2s_soc_data rk1808_i2s_soc_data = {
995 .softrst_offset = 0x0300,
996 .configs = rk1808_txrx_config,
997 .config_count = ARRAY_SIZE(rk1808_txrx_config),
998 .init = common_soc_init,
999};
1000
1001static const struct rk_i2s_soc_data rk3308_i2s_soc_data = {
1002 .softrst_offset = 0x0400,
1003 .grf_reg_offset = 0x0308,
1004 .grf_shift = 5,
1005 .configs = rk3308_txrx_config,
1006 .config_count = ARRAY_SIZE(rk3308_txrx_config),
1007 .init = common_soc_init,
1008};
1009
1010static const struct rk_i2s_soc_data rk3568_i2s_soc_data = {
1011 .softrst_offset = 0x0400,
1012 .configs = rk3568_txrx_config,
1013 .config_count = ARRAY_SIZE(rk3568_txrx_config),
1014 .init = common_soc_init,
1015};
1016
1017static const struct rk_i2s_soc_data rv1126_i2s_soc_data = {
1018 .softrst_offset = 0x0300,
1019 .configs = rv1126_txrx_config,
1020 .config_count = ARRAY_SIZE(rv1126_txrx_config),
1021 .init = common_soc_init,
1022};
1023
1024static const struct of_device_id rockchip_i2s_tdm_match[] = {
1025 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data },
1026 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
1027 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
1028 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
1029 { .compatible = "rockchip,rk3588-i2s-tdm" },
1030 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
1031 {},
1032};
1033
1034static const struct snd_soc_dai_driver i2s_tdm_dai = {
1035 .ops = &rockchip_i2s_tdm_dai_ops,
1036};
1037
1038static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm)
1039{
1040 struct snd_soc_dai_driver *dai;
1041 struct property *dma_names;
1042 const char *dma_name;
1043 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |
1044 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |
1045 SNDRV_PCM_FMTBIT_S32_LE);
1046 struct device_node *node = i2s_tdm->dev->of_node;
1047
1048 of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
1049 if (!strcmp(dma_name, "tx"))
1050 i2s_tdm->has_playback = true;
1051 if (!strcmp(dma_name, "rx"))
1052 i2s_tdm->has_capture = true;
1053 }
1054
1055 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai,
1056 sizeof(*dai), GFP_KERNEL);
1057 if (!dai)
1058 return -ENOMEM;
1059
1060 if (i2s_tdm->has_playback) {
1061 dai->playback.stream_name = "Playback";
1062 dai->playback.channels_min = 2;
1063 dai->playback.channels_max = 8;
1064 dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
1065 dai->playback.formats = formats;
1066 }
1067
1068 if (i2s_tdm->has_capture) {
1069 dai->capture.stream_name = "Capture";
1070 dai->capture.channels_min = 2;
1071 dai->capture.channels_max = 8;
1072 dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
1073 dai->capture.formats = formats;
1074 }
1075
1076 if (i2s_tdm->clk_trcm != TRCM_TXRX)
1077 dai->symmetric_rate = 1;
1078
1079 i2s_tdm->dai = dai;
1080
1081 return 0;
1082}
1083
1084static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm,
1085 int num,
1086 bool is_rx_path)
1087{
1088 unsigned int *i2s_data;
1089 int i, j;
1090
1091 if (is_rx_path)
1092 i2s_data = i2s_tdm->i2s_sdis;
1093 else
1094 i2s_data = i2s_tdm->i2s_sdos;
1095
1096 for (i = 0; i < num; i++) {
1097 if (i2s_data[i] > CH_GRP_MAX - 1) {
1098 dev_err(i2s_tdm->dev,
1099 "%s path i2s_data[%d]: %d is too high, max is: %d\n",
1100 is_rx_path ? "RX" : "TX",
1101 i, i2s_data[i], CH_GRP_MAX);
1102 return -EINVAL;
1103 }
1104
1105 for (j = 0; j < num; j++) {
1106 if (i == j)
1107 continue;
1108
1109 if (i2s_data[i] == i2s_data[j]) {
1110 dev_err(i2s_tdm->dev,
1111 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n",
1112 is_rx_path ? "RX" : "TX",
1113 i, i2s_data[i],
1114 j, i2s_data[j]);
1115 return -EINVAL;
1116 }
1117 }
1118 }
1119
1120 return 0;
1121}
1122
1123static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1124 int num)
1125{
1126 int idx;
1127
1128 for (idx = 0; idx < num; idx++) {
1129 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1130 I2S_TXCR_PATH_MASK(idx),
1131 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx]));
1132 }
1133}
1134
1135static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1136 int num)
1137{
1138 int idx;
1139
1140 for (idx = 0; idx < num; idx++) {
1141 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1142 I2S_RXCR_PATH_MASK(idx),
1143 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx]));
1144 }
1145}
1146
1147static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm,
1148 int num, bool is_rx_path)
1149{
1150 if (is_rx_path)
1151 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num);
1152 else
1153 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num);
1154}
1155
1156static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1157 struct device_node *np,
1158 bool is_rx_path)
1159{
1160 char *i2s_tx_path_prop = "rockchip,i2s-tx-route";
1161 char *i2s_rx_path_prop = "rockchip,i2s-rx-route";
1162 char *i2s_path_prop;
1163 unsigned int *i2s_data;
1164 int num, ret = 0;
1165
1166 if (is_rx_path) {
1167 i2s_path_prop = i2s_rx_path_prop;
1168 i2s_data = i2s_tdm->i2s_sdis;
1169 } else {
1170 i2s_path_prop = i2s_tx_path_prop;
1171 i2s_data = i2s_tdm->i2s_sdos;
1172 }
1173
1174 num = of_count_phandle_with_args(np, i2s_path_prop, NULL);
1175 if (num < 0) {
1176 if (num != -ENOENT) {
1177 dev_err(i2s_tdm->dev,
1178 "Failed to read '%s' num: %d\n",
1179 i2s_path_prop, num);
1180 ret = num;
1181 }
1182 return ret;
1183 } else if (num != CH_GRP_MAX) {
1184 dev_err(i2s_tdm->dev,
1185 "The num: %d should be: %d\n", num, CH_GRP_MAX);
1186 return -EINVAL;
1187 }
1188
1189 ret = of_property_read_u32_array(np, i2s_path_prop,
1190 i2s_data, num);
1191 if (ret < 0) {
1192 dev_err(i2s_tdm->dev,
1193 "Failed to read '%s': %d\n",
1194 i2s_path_prop, ret);
1195 return ret;
1196 }
1197
1198 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path);
1199 if (ret < 0) {
1200 dev_err(i2s_tdm->dev,
1201 "Failed to check i2s data bus: %d\n", ret);
1202 return ret;
1203 }
1204
1205 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path);
1206
1207 return 0;
1208}
1209
1210static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1211 struct device_node *np)
1212{
1213 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0);
1214}
1215
1216static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm,
1217 struct device_node *np)
1218{
1219 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1220}
1221
1222static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1223{
1224 struct device_node *node = pdev->dev.of_node;
1225 struct rk_i2s_tdm_dev *i2s_tdm;
1226 struct resource *res;
1227 void __iomem *regs;
1228 int ret;
1229
1230 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL);
1231 if (!i2s_tdm)
1232 return -ENOMEM;
1233
1234 i2s_tdm->dev = &pdev->dev;
1235
1236 spin_lock_init(&i2s_tdm->lock);
1237 i2s_tdm->soc_data = device_get_match_data(&pdev->dev);
1238 i2s_tdm->frame_width = 64;
1239
1240 i2s_tdm->clk_trcm = TRCM_TXRX;
1241 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only"))
1242 i2s_tdm->clk_trcm = TRCM_TX;
1243 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) {
1244 if (i2s_tdm->clk_trcm) {
1245 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n");
1246 return -EINVAL;
1247 }
1248 i2s_tdm->clk_trcm = TRCM_RX;
1249 }
1250
1251 ret = rockchip_i2s_tdm_init_dai(i2s_tdm);
1252 if (ret)
1253 return ret;
1254
1255 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1256 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1257 "tx-m");
1258 if (IS_ERR(i2s_tdm->tx_reset)) {
1259 ret = PTR_ERR(i2s_tdm->tx_reset);
1260 return dev_err_probe(i2s_tdm->dev, ret,
1261 "Error in tx-m reset control\n");
1262 }
1263
1264 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
1265 "rx-m");
1266 if (IS_ERR(i2s_tdm->rx_reset)) {
1267 ret = PTR_ERR(i2s_tdm->rx_reset);
1268 return dev_err_probe(i2s_tdm->dev, ret,
1269 "Error in rx-m reset control\n");
1270 }
1271
1272 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk");
1273 if (IS_ERR(i2s_tdm->hclk)) {
1274 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk),
1275 "Failed to get clock hclk\n");
1276 }
1277
1278 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx");
1279 if (IS_ERR(i2s_tdm->mclk_tx)) {
1280 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx),
1281 "Failed to get clock mclk_tx\n");
1282 }
1283
1284 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx");
1285 if (IS_ERR(i2s_tdm->mclk_rx)) {
1286 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx),
1287 "Failed to get clock mclk_rx\n");
1288 }
1289
1290 i2s_tdm->io_multiplex =
1291 of_property_read_bool(node, "rockchip,io-multiplex");
1292
1293 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1294 if (IS_ERR(regs)) {
1295 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs),
1296 "Failed to get resource IORESOURCE_MEM\n");
1297 }
1298
1299 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1300 &rockchip_i2s_tdm_regmap_config);
1301 if (IS_ERR(i2s_tdm->regmap)) {
1302 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap),
1303 "Failed to initialise regmap\n");
1304 }
1305
1306 if (i2s_tdm->has_playback) {
1307 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1308 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1309 i2s_tdm->playback_dma_data.maxburst = 8;
1310 }
1311
1312 if (i2s_tdm->has_capture) {
1313 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1314 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1315 i2s_tdm->capture_dma_data.maxburst = 8;
1316 }
1317
1318 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret);
1321 return ret;
1322 }
1323
1324 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node);
1325 if (ret < 0) {
1326 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret);
1327 return ret;
1328 }
1329
1330 dev_set_drvdata(&pdev->dev, i2s_tdm);
1331
1332 ret = clk_prepare_enable(i2s_tdm->hclk);
1333 if (ret) {
1334 return dev_err_probe(i2s_tdm->dev, ret,
1335 "Failed to enable clock hclk\n");
1336 }
1337
1338 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm);
1339 if (ret) {
1340 ret = dev_err_probe(i2s_tdm->dev, ret,
1341 "Failed to enable one or more mclks\n");
1342 goto err_disable_hclk;
1343 }
1344
1345 pm_runtime_enable(&pdev->dev);
1346
1347 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1348 I2S_DMACR_TDL(16));
1349 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
1350 I2S_DMACR_RDL(16));
1351 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK,
1352 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT);
1353
1354 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init)
1355 i2s_tdm->soc_data->init(&pdev->dev, res->start);
1356
1357 ret = devm_snd_soc_register_component(&pdev->dev,
1358 &rockchip_i2s_tdm_component,
1359 i2s_tdm->dai, 1);
1360
1361 if (ret) {
1362 dev_err(&pdev->dev, "Could not register DAI\n");
1363 goto err_suspend;
1364 }
1365
1366 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1367 if (ret) {
1368 dev_err(&pdev->dev, "Could not register PCM\n");
1369 goto err_suspend;
1370 }
1371
1372 return 0;
1373
1374err_suspend:
1375 if (!pm_runtime_status_suspended(&pdev->dev))
1376 i2s_tdm_runtime_suspend(&pdev->dev);
1377 pm_runtime_disable(&pdev->dev);
1378
1379err_disable_hclk:
1380 clk_disable_unprepare(i2s_tdm->hclk);
1381
1382 return ret;
1383}
1384
1385static void rockchip_i2s_tdm_remove(struct platform_device *pdev)
1386{
1387 if (!pm_runtime_status_suspended(&pdev->dev))
1388 i2s_tdm_runtime_suspend(&pdev->dev);
1389
1390 pm_runtime_disable(&pdev->dev);
1391}
1392
1393static int rockchip_i2s_tdm_suspend(struct device *dev)
1394{
1395 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1396
1397 regcache_mark_dirty(i2s_tdm->regmap);
1398
1399 return 0;
1400}
1401
1402static int rockchip_i2s_tdm_resume(struct device *dev)
1403{
1404 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
1405 int ret;
1406
1407 ret = pm_runtime_resume_and_get(dev);
1408 if (ret < 0)
1409 return ret;
1410 ret = regcache_sync(i2s_tdm->regmap);
1411 pm_runtime_put(dev);
1412
1413 return ret;
1414}
1415
1416static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = {
1417 RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume, NULL)
1418 SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend, rockchip_i2s_tdm_resume)
1419};
1420
1421static struct platform_driver rockchip_i2s_tdm_driver = {
1422 .probe = rockchip_i2s_tdm_probe,
1423 .remove = rockchip_i2s_tdm_remove,
1424 .driver = {
1425 .name = DRV_NAME,
1426 .of_match_table = rockchip_i2s_tdm_match,
1427 .pm = pm_ptr(&rockchip_i2s_tdm_pm_ops),
1428 },
1429};
1430module_platform_driver(rockchip_i2s_tdm_driver);
1431
1432MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface");
1433MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
1434MODULE_LICENSE("GPL v2");
1435MODULE_ALIAS("platform:" DRV_NAME);
1436MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match);
1437
