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12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/of_gpio.h>
15#include <linux/clk.h>
16#include <linux/pm_runtime.h>
17#include <linux/mfd/syscon.h>
18#include <linux/regmap.h>
19#include <sound/pcm_params.h>
20#include <sound/dmaengine_pcm.h>
21
22#include "rockchip_spdif.h"
23
24enum rk_spdif_type {
25 RK_SPDIF_RK3066,
26 RK_SPDIF_RK3188,
27 RK_SPDIF_RK3288,
28 RK_SPDIF_RK3366,
29};
30
31#define RK3288_GRF_SOC_CON2 0x24c
32
33struct rk_spdif_dev {
34 struct device *dev;
35
36 struct clk *mclk;
37 struct clk *hclk;
38
39 struct snd_dmaengine_dai_dma_data playback_dma_data;
40
41 struct regmap *regmap;
42};
43
44static const struct of_device_id rk_spdif_match[] __maybe_unused = {
45 { .compatible = "rockchip,rk3066-spdif",
46 .data = (void *)RK_SPDIF_RK3066 },
47 { .compatible = "rockchip,rk3188-spdif",
48 .data = (void *)RK_SPDIF_RK3188 },
49 { .compatible = "rockchip,rk3228-spdif",
50 .data = (void *)RK_SPDIF_RK3366 },
51 { .compatible = "rockchip,rk3288-spdif",
52 .data = (void *)RK_SPDIF_RK3288 },
53 { .compatible = "rockchip,rk3328-spdif",
54 .data = (void *)RK_SPDIF_RK3366 },
55 { .compatible = "rockchip,rk3366-spdif",
56 .data = (void *)RK_SPDIF_RK3366 },
57 { .compatible = "rockchip,rk3368-spdif",
58 .data = (void *)RK_SPDIF_RK3366 },
59 { .compatible = "rockchip,rk3399-spdif",
60 .data = (void *)RK_SPDIF_RK3366 },
61 { .compatible = "rockchip,rk3568-spdif",
62 .data = (void *)RK_SPDIF_RK3366 },
63 {},
64};
65MODULE_DEVICE_TABLE(of, rk_spdif_match);
66
67static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
68{
69 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
70
71 regcache_cache_only(spdif->regmap, true);
72 clk_disable_unprepare(spdif->mclk);
73 clk_disable_unprepare(spdif->hclk);
74
75 return 0;
76}
77
78static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
79{
80 struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
81 int ret;
82
83 ret = clk_prepare_enable(spdif->mclk);
84 if (ret) {
85 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
86 return ret;
87 }
88
89 ret = clk_prepare_enable(spdif->hclk);
90 if (ret) {
91 dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
92 return ret;
93 }
94
95 regcache_cache_only(spdif->regmap, false);
96 regcache_mark_dirty(spdif->regmap);
97
98 ret = regcache_sync(spdif->regmap);
99 if (ret) {
100 clk_disable_unprepare(spdif->mclk);
101 clk_disable_unprepare(spdif->hclk);
102 }
103
104 return ret;
105}
106
107static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
108 struct snd_pcm_hw_params *params,
109 struct snd_soc_dai *dai)
110{
111 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
112 unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
113 int srate, mclk;
114 int ret;
115
116 srate = params_rate(params);
117 mclk = srate * 128;
118
119 switch (params_format(params)) {
120 case SNDRV_PCM_FORMAT_S16_LE:
121 val |= SPDIF_CFGR_VDW_16;
122 break;
123 case SNDRV_PCM_FORMAT_S20_3LE:
124 val |= SPDIF_CFGR_VDW_20;
125 break;
126 case SNDRV_PCM_FORMAT_S24_LE:
127 val |= SPDIF_CFGR_VDW_24;
128 break;
129 default:
130 return -EINVAL;
131 }
132
133
134 ret = clk_set_rate(spdif->mclk, mclk);
135 if (ret != 0) {
136 dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
137 ret);
138 return ret;
139 }
140
141 ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
142 SPDIF_CFGR_CLK_DIV_MASK |
143 SPDIF_CFGR_HALFWORD_ENABLE |
144 SDPIF_CFGR_VDW_MASK, val);
145
146 return ret;
147}
148
149static int rk_spdif_trigger(struct snd_pcm_substream *substream,
150 int cmd, struct snd_soc_dai *dai)
151{
152 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
153 int ret;
154
155 switch (cmd) {
156 case SNDRV_PCM_TRIGGER_START:
157 case SNDRV_PCM_TRIGGER_RESUME:
158 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
159 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
160 SPDIF_DMACR_TDE_ENABLE |
161 SPDIF_DMACR_TDL_MASK,
162 SPDIF_DMACR_TDE_ENABLE |
163 SPDIF_DMACR_TDL(16));
164
165 if (ret != 0)
166 return ret;
167
168 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
169 SPDIF_XFER_TXS_START,
170 SPDIF_XFER_TXS_START);
171 break;
172 case SNDRV_PCM_TRIGGER_SUSPEND:
173 case SNDRV_PCM_TRIGGER_STOP:
174 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
175 ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
176 SPDIF_DMACR_TDE_ENABLE,
177 SPDIF_DMACR_TDE_DISABLE);
178
179 if (ret != 0)
180 return ret;
181
182 ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
183 SPDIF_XFER_TXS_START,
184 SPDIF_XFER_TXS_STOP);
185 break;
186 default:
187 ret = -EINVAL;
188 break;
189 }
190
191 return ret;
192}
193
194static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
195{
196 struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
197
198 dai->playback_dma_data = &spdif->playback_dma_data;
199
200 return 0;
201}
202
203static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
204 .hw_params = rk_spdif_hw_params,
205 .trigger = rk_spdif_trigger,
206};
207
208static struct snd_soc_dai_driver rk_spdif_dai = {
209 .probe = rk_spdif_dai_probe,
210 .playback = {
211 .stream_name = "Playback",
212 .channels_min = 2,
213 .channels_max = 2,
214 .rates = (SNDRV_PCM_RATE_32000 |
215 SNDRV_PCM_RATE_44100 |
216 SNDRV_PCM_RATE_48000 |
217 SNDRV_PCM_RATE_96000 |
218 SNDRV_PCM_RATE_192000),
219 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
220 SNDRV_PCM_FMTBIT_S20_3LE |
221 SNDRV_PCM_FMTBIT_S24_LE),
222 },
223 .ops = &rk_spdif_dai_ops,
224};
225
226static const struct snd_soc_component_driver rk_spdif_component = {
227 .name = "rockchip-spdif",
228};
229
230static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
231{
232 switch (reg) {
233 case SPDIF_CFGR:
234 case SPDIF_DMACR:
235 case SPDIF_INTCR:
236 case SPDIF_XFER:
237 case SPDIF_SMPDR:
238 return true;
239 default:
240 return false;
241 }
242}
243
244static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
245{
246 switch (reg) {
247 case SPDIF_CFGR:
248 case SPDIF_SDBLR:
249 case SPDIF_INTCR:
250 case SPDIF_INTSR:
251 case SPDIF_XFER:
252 case SPDIF_SMPDR:
253 return true;
254 default:
255 return false;
256 }
257}
258
259static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
260{
261 switch (reg) {
262 case SPDIF_INTSR:
263 case SPDIF_SDBLR:
264 case SPDIF_SMPDR:
265 return true;
266 default:
267 return false;
268 }
269}
270
271static const struct regmap_config rk_spdif_regmap_config = {
272 .reg_bits = 32,
273 .reg_stride = 4,
274 .val_bits = 32,
275 .max_register = SPDIF_SMPDR,
276 .writeable_reg = rk_spdif_wr_reg,
277 .readable_reg = rk_spdif_rd_reg,
278 .volatile_reg = rk_spdif_volatile_reg,
279 .cache_type = REGCACHE_FLAT,
280};
281
282static int rk_spdif_probe(struct platform_device *pdev)
283{
284 struct device_node *np = pdev->dev.of_node;
285 struct rk_spdif_dev *spdif;
286 const struct of_device_id *match;
287 struct resource *res;
288 void __iomem *regs;
289 int ret;
290
291 match = of_match_node(rk_spdif_match, np);
292 if (match->data == (void *)RK_SPDIF_RK3288) {
293 struct regmap *grf;
294
295 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
296 if (IS_ERR(grf)) {
297 dev_err(&pdev->dev,
298 "rockchip_spdif missing 'rockchip,grf'\n");
299 return PTR_ERR(grf);
300 }
301
302
303
304
305 regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
306 }
307
308 spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
309 if (!spdif)
310 return -ENOMEM;
311
312 spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
313 if (IS_ERR(spdif->hclk))
314 return PTR_ERR(spdif->hclk);
315
316 spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
317 if (IS_ERR(spdif->mclk))
318 return PTR_ERR(spdif->mclk);
319
320 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
321 if (IS_ERR(regs))
322 return PTR_ERR(regs);
323
324 spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
325 &rk_spdif_regmap_config);
326 if (IS_ERR(spdif->regmap))
327 return PTR_ERR(spdif->regmap);
328
329 spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
330 spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
331 spdif->playback_dma_data.maxburst = 4;
332
333 spdif->dev = &pdev->dev;
334 dev_set_drvdata(&pdev->dev, spdif);
335
336 pm_runtime_enable(&pdev->dev);
337 if (!pm_runtime_enabled(&pdev->dev)) {
338 ret = rk_spdif_runtime_resume(&pdev->dev);
339 if (ret)
340 goto err_pm_runtime;
341 }
342
343 ret = devm_snd_soc_register_component(&pdev->dev,
344 &rk_spdif_component,
345 &rk_spdif_dai, 1);
346 if (ret) {
347 dev_err(&pdev->dev, "Could not register DAI\n");
348 goto err_pm_suspend;
349 }
350
351 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
352 if (ret) {
353 dev_err(&pdev->dev, "Could not register PCM\n");
354 goto err_pm_suspend;
355 }
356
357 return 0;
358
359err_pm_suspend:
360 if (!pm_runtime_status_suspended(&pdev->dev))
361 rk_spdif_runtime_suspend(&pdev->dev);
362err_pm_runtime:
363 pm_runtime_disable(&pdev->dev);
364
365 return ret;
366}
367
368static int rk_spdif_remove(struct platform_device *pdev)
369{
370 pm_runtime_disable(&pdev->dev);
371 if (!pm_runtime_status_suspended(&pdev->dev))
372 rk_spdif_runtime_suspend(&pdev->dev);
373
374 return 0;
375}
376
377static const struct dev_pm_ops rk_spdif_pm_ops = {
378 SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
379 NULL)
380};
381
382static struct platform_driver rk_spdif_driver = {
383 .probe = rk_spdif_probe,
384 .remove = rk_spdif_remove,
385 .driver = {
386 .name = "rockchip-spdif",
387 .of_match_table = of_match_ptr(rk_spdif_match),
388 .pm = &rk_spdif_pm_ops,
389 },
390};
391module_platform_driver(rk_spdif_driver);
392
393MODULE_ALIAS("platform:rockchip-spdif");
394MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
395MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
396MODULE_LICENSE("GPL v2");
397
