LXR linux/sound/soc/sof/intel/apl.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2//
   3// This file is provided under a dual BSD/GPLv2 license.  When using or
   4// redistributing this file, you may do so under either license.
   5//
   6// Copyright(c) 2018 Intel Corporation. All rights reserved.
   7//
   8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9//          Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
  10//          Rander Wang <rander.wang@intel.com>
  11//          Keyon Jie <yang.jie@linux.intel.com>
  12//
  13
  14/*
  15 * Hardware interface for audio DSP on Apollolake and GeminiLake
  16 */
  17
  18#include "../sof-priv.h"
  19#include "hda.h"
  20#include "../sof-audio.h"
  21
  22static const struct snd_sof_debugfs_map apl_dsp_debugfs[] = {
  23        {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  24        {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  25        {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  26};
  27
  28/* apollolake ops */
  29const struct snd_sof_dsp_ops sof_apl_ops = {
  30        /* probe/remove/shutdown */
  31        .probe          = hda_dsp_probe,
  32        .remove         = hda_dsp_remove,
  33        .shutdown       = hda_dsp_shutdown,
  34
  35        /* Register IO */
  36        .write          = sof_io_write,
  37        .read           = sof_io_read,
  38        .write64        = sof_io_write64,
  39        .read64         = sof_io_read64,
  40
  41        /* Block IO */
  42        .block_read     = sof_block_read,
  43        .block_write    = sof_block_write,
  44
  45        /* doorbell */
  46        .irq_thread     = hda_dsp_ipc_irq_thread,
  47
  48        /* ipc */
  49        .send_msg       = hda_dsp_ipc_send_msg,
  50        .fw_ready       = sof_fw_ready,
  51        .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
  52        .get_window_offset = hda_dsp_ipc_get_window_offset,
  53
  54        .ipc_msg_data   = hda_ipc_msg_data,
  55        .ipc_pcm_params = hda_ipc_pcm_params,
  56
  57        /* machine driver */
  58        .machine_select = hda_machine_select,
  59        .machine_register = sof_machine_register,
  60        .machine_unregister = sof_machine_unregister,
  61        .set_mach_params = hda_set_mach_params,
  62
  63        /* debug */
  64        .debug_map      = apl_dsp_debugfs,
  65        .debug_map_count        = ARRAY_SIZE(apl_dsp_debugfs),
  66        .dbg_dump       = hda_dsp_dump,
  67        .ipc_dump       = hda_ipc_dump,
  68
  69        /* stream callbacks */
  70        .pcm_open       = hda_dsp_pcm_open,
  71        .pcm_close      = hda_dsp_pcm_close,
  72        .pcm_hw_params  = hda_dsp_pcm_hw_params,
  73        .pcm_hw_free    = hda_dsp_stream_hw_free,
  74        .pcm_trigger    = hda_dsp_pcm_trigger,
  75        .pcm_pointer    = hda_dsp_pcm_pointer,
  76
  77#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
  78        /* probe callbacks */
  79        .probe_assign   = hda_probe_compr_assign,
  80        .probe_free     = hda_probe_compr_free,
  81        .probe_set_params       = hda_probe_compr_set_params,
  82        .probe_trigger  = hda_probe_compr_trigger,
  83        .probe_pointer  = hda_probe_compr_pointer,
  84#endif
  85
  86        /* firmware loading */
  87        .load_firmware = snd_sof_load_firmware_raw,
  88
  89        /* firmware run */
  90        .run = hda_dsp_cl_boot_firmware,
  91
  92        /* pre/post fw run */
  93        .pre_fw_run = hda_dsp_pre_fw_run,
  94        .post_fw_run = hda_dsp_post_fw_run,
  95
  96        /* parse platform specific extended manifest */
  97        .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
  98
  99        /* dsp core power up/down */
 100        .core_power_up = hda_dsp_enable_core,
 101        .core_power_down = hda_dsp_core_reset_power_down,
 102
 103        /* trace callback */
 104        .trace_init = hda_dsp_trace_init,
 105        .trace_release = hda_dsp_trace_release,
 106        .trace_trigger = hda_dsp_trace_trigger,
 107
 108        /* DAI drivers */
 109        .drv            = skl_dai,
 110        .num_drv        = SOF_SKL_NUM_DAIS,
 111
 112        /* PM */
 113        .suspend                = hda_dsp_suspend,
 114        .resume                 = hda_dsp_resume,
 115        .runtime_suspend        = hda_dsp_runtime_suspend,
 116        .runtime_resume         = hda_dsp_runtime_resume,
 117        .runtime_idle           = hda_dsp_runtime_idle,
 118        .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
 119        .set_power_state        = hda_dsp_set_power_state,
 120
 121        /* ALSA HW info flags */
 122        .hw_info =      SNDRV_PCM_INFO_MMAP |
 123                        SNDRV_PCM_INFO_MMAP_VALID |
 124                        SNDRV_PCM_INFO_INTERLEAVED |
 125                        SNDRV_PCM_INFO_PAUSE |
 126                        SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
 127
 128        .arch_ops = &sof_xtensa_arch_ops,
 129};
 130EXPORT_SYMBOL_NS(sof_apl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
 131
 132const struct sof_intel_dsp_desc apl_chip_info = {
 133        /* Apollolake */
 134        .cores_num = 2,
 135        .init_core_mask = 1,
 136        .host_managed_cores_mask = GENMASK(1, 0),
 137        .ipc_req = HDA_DSP_REG_HIPCI,
 138        .ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
 139        .ipc_ack = HDA_DSP_REG_HIPCIE,
 140        .ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
 141        .ipc_ctl = HDA_DSP_REG_HIPCCTL,
 142        .rom_init_timeout       = 150,
 143        .ssp_count = APL_SSP_COUNT,
 144        .ssp_base_offset = APL_SSP_BASE_OFFSET,
 145};
 146EXPORT_SYMBOL_NS(apl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 147