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11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <linux/soundwire/sdw.h>
15#include <linux/soundwire/sdw_intel.h>
16#include <sound/compress_driver.h>
17#include <sound/hda_codec.h>
18#include <sound/hdaudio_ext.h>
19#include "shim.h"
20
21
22#define PCI_TCSEL 0x44
23#define PCI_PGCTL PCI_TCSEL
24#define PCI_CGCTL 0x48
25
26
27#define PCI_PGCTL_ADSPPGD BIT(2)
28#define PCI_PGCTL_LSRMD_MASK BIT(4)
29
30
31#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
32#define PCI_CGCTL_ADSPDCGE BIT(1)
33
34
35#define SOF_HDA_GCAP 0x0
36#define SOF_HDA_GCTL 0x8
37
38#define SOF_HDA_GCTL_UNSOL BIT(8)
39#define SOF_HDA_LLCH 0x14
40#define SOF_HDA_INTCTL 0x20
41#define SOF_HDA_INTSTS 0x24
42#define SOF_HDA_WAKESTS 0x0E
43#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
44#define SOF_HDA_RIRBSTS 0x5d
45
46
47#define SOF_HDA_GCTL_RESET BIT(0)
48
49
50#define SOF_HDA_INT_GLOBAL_EN BIT(31)
51#define SOF_HDA_INT_CTRL_EN BIT(30)
52#define SOF_HDA_INT_ALL_STREAM 0xff
53
54
55#define SOF_HDA_INTSTS_GIS BIT(31)
56
57#define SOF_HDA_MAX_CAPS 10
58#define SOF_HDA_CAP_ID_OFF 16
59#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
60 SOF_HDA_CAP_ID_OFF)
61#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
62
63#define SOF_HDA_GTS_CAP_ID 0x1
64#define SOF_HDA_ML_CAP_ID 0x2
65
66#define SOF_HDA_PP_CAP_ID 0x3
67#define SOF_HDA_REG_PP_PPCH 0x10
68#define SOF_HDA_REG_PP_PPCTL 0x04
69#define SOF_HDA_REG_PP_PPSTS 0x08
70#define SOF_HDA_PPCTL_PIE BIT(31)
71#define SOF_HDA_PPCTL_GPROCEN BIT(30)
72
73
74#define SOF_HDA_VS_D0I3C 0x104A
75
76
77#define SOF_HDA_VS_D0I3C_CIP BIT(0)
78#define SOF_HDA_VS_D0I3C_I3 BIT(2)
79
80
81#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
82
83#define SOF_HDA_SPIB_CAP_ID 0x4
84#define SOF_HDA_DRSM_CAP_ID 0x5
85
86#define SOF_HDA_SPIB_BASE 0x08
87#define SOF_HDA_SPIB_INTERVAL 0x08
88#define SOF_HDA_SPIB_SPIB 0x00
89#define SOF_HDA_SPIB_MAXFIFO 0x04
90
91#define SOF_HDA_PPHC_BASE 0x10
92#define SOF_HDA_PPHC_INTERVAL 0x10
93
94#define SOF_HDA_PPLC_BASE 0x10
95#define SOF_HDA_PPLC_MULTI 0x10
96#define SOF_HDA_PPLC_INTERVAL 0x10
97
98#define SOF_HDA_DRSM_BASE 0x08
99#define SOF_HDA_DRSM_INTERVAL 0x08
100
101
102#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
103
104
105#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
106
107
108#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
109
110#define SOF_HDA_CL_DMA_SD_INT_MASK \
111 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
112 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
113 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
114#define SOF_HDA_SD_CTL_DMA_START 0x02
115
116
117#define SOF_HDA_ADSP_LOADER_BASE 0x80
118#define SOF_HDA_ADSP_DPLBASE 0x70
119#define SOF_HDA_ADSP_DPUBASE 0x74
120#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
121
122
123#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
124#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
125#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
126#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
127#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
128#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
129#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
130#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
131#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
132#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
133#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
134#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
135
136
137#define SOF_DSP_REG_CL_SPBFIFO \
138 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
139#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
140#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
141#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
142#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
143
144
145#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
146#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
147 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
148 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
149
150#define HDA_DSP_HDA_BAR 0
151#define HDA_DSP_PP_BAR 1
152#define HDA_DSP_SPIB_BAR 2
153#define HDA_DSP_DRSM_BAR 3
154#define HDA_DSP_BAR 4
155
156#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
157
158#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
159
160#define HDA_DSP_PANIC_OFFSET(x) \
161 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
162
163
164#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
165#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
166
167#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
168#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
169#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
170
171#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
172
173#define HDA_DSP_STREAM_RESET_TIMEOUT 300
174
175
176
177
178
179#define HDA_DSP_STREAM_RUN_TIMEOUT 300
180
181#define HDA_DSP_SPIB_ENABLE 1
182#define HDA_DSP_SPIB_DISABLE 0
183
184#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
185
186#define HDA_DSP_STACK_DUMP_SIZE 32
187
188
189#define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
190#define HDA_DSP_ROM_INIT 0x1
191#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
192#define HDA_DSP_ROM_FW_FW_LOADED 0x4
193#define HDA_DSP_ROM_FW_ENTERED 0x5
194#define HDA_DSP_ROM_RFW_START 0xf
195#define HDA_DSP_ROM_CSE_ERROR 40
196#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
197#define HDA_DSP_ROM_IMR_TO_SMALL 42
198#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
199#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
200#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
201#define HDA_DSP_ROM_L2_CACHE_ERROR 46
202#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
203#define HDA_DSP_ROM_API_PTR_INVALID 50
204#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
205#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
206#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
207#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
208#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
209#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
210#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
211#define HDA_DSP_IPC_PURGE_FW 0x01004000
212
213
214#define HDA_DSP_PU_TIMEOUT 50
215#define HDA_DSP_PD_TIMEOUT 50
216#define HDA_DSP_RESET_TIMEOUT_US 50000
217#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
218#define HDA_DSP_INIT_TIMEOUT_US 500000
219#define HDA_DSP_CTRL_RESET_TIMEOUT 100
220#define HDA_DSP_WAIT_TIMEOUT 500
221#define HDA_DSP_REG_POLL_INTERVAL_US 500
222#define HDA_DSP_REG_POLL_RETRY_COUNT 50
223
224#define HDA_DSP_ADSPIC_IPC 1
225#define HDA_DSP_ADSPIS_IPC 1
226
227
228#define HDA_DSP_GEN_BASE 0x0
229#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
230#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
231#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
232#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
233#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
234
235#define HDA_DSP_REG_ADSPIS2_SNDW BIT(5)
236
237
238#define HDA_DSP_IPC_BASE 0x40
239#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
240#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
241#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
242#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
243#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
244
245
246#define HDA_VS_INTEL_EM2 0x1030
247#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
248#define HDA_VS_INTEL_LTRP_GB_MASK 0x3F
249
250
251#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
252#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
253
254
255#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
256#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
257
258
259#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
260#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
261
262
263#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
264#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
265
266
267#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
268
269#define HDA_DSP_ADSPIC_CL_DMA 0x2
270#define HDA_DSP_ADSPIS_CL_DMA 0x2
271
272
273#define BXT_D0I3_DELAY 5000
274
275#define FW_CL_STREAM_NUMBER 0x1
276#define HDA_FW_BOOT_ATTEMPTS 3
277
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282
283
284#define HDA_DSP_ADSPCS_CRST_SHIFT 0
285#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
286
287
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289
290
291#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
292#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
293
294
295
296
297
298#define HDA_DSP_ADSPCS_SPA_SHIFT 16
299#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
300
301
302
303
304
305#define HDA_DSP_ADSPCS_CPA_SHIFT 24
306#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
307
308
309
310
311
312#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
313
314
315#define CNL_DSP_IPC_BASE 0xc0
316#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
317#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
318#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
319#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
320#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
321#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
322#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
323
324
325#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
326#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
327
328
329#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
330#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
331
332
333#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
334#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
335
336
337#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
338#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
339
340
341#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
342#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
343
344
345#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
346
347
348#define HDA_DSP_BDL_SIZE 4096
349#define HDA_DSP_MAX_BDL_ENTRIES \
350 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
351
352
353#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
354
355#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
356#define SOF_SKL_NUM_DAIS 16
357#else
358#define SOF_SKL_NUM_DAIS 15
359#endif
360
361#else
362#define SOF_SKL_NUM_DAIS 8
363#endif
364
365
366#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
367
368
369#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
370#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
371
372
373#define APL_SSP_BASE_OFFSET 0x2000
374#define CNL_SSP_BASE_OFFSET 0x10000
375
376
377#define SSP_DEV_MEM_SIZE 0x1000
378
379
380#define APL_SSP_COUNT 6
381#define CNL_SSP_COUNT 3
382#define ICL_SSP_COUNT 6
383
384
385#define SSP_SSC1_OFFSET 0x4
386#define SSP_SET_SCLK_SLAVE BIT(25)
387#define SSP_SET_SFRM_SLAVE BIT(24)
388#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
389
390#define HDA_IDISP_ADDR 2
391#define HDA_IDISP_CODEC(x) ((x) & BIT(HDA_IDISP_ADDR))
392
393struct sof_intel_dsp_bdl {
394 __le32 addr_l;
395 __le32 addr_h;
396 __le32 size;
397 __le32 ioc;
398} __attribute((packed));
399
400#define SOF_HDA_PLAYBACK_STREAMS 16
401#define SOF_HDA_CAPTURE_STREAMS 16
402#define SOF_HDA_PLAYBACK 0
403#define SOF_HDA_CAPTURE 1
404
405
406#define SOF_HDA_STREAM_DMI_L1_COMPATIBLE 1
407
408
409
410
411
412
413#define SOF_HDA_D0I3_WORK_DELAY_MS 5000
414
415
416enum sof_hda_D0_substate {
417 SOF_HDA_DSP_PM_D0I0,
418 SOF_HDA_DSP_PM_D0I3,
419};
420
421
422struct sof_intel_hda_dev {
423 int boot_iteration;
424
425 struct hda_bus hbus;
426
427
428 const struct sof_intel_dsp_desc *desc;
429
430
431 struct hdac_ext_stream *dtrace_stream;
432
433
434 u32 no_ipc_position;
435
436
437 u32 stream_max;
438
439
440 bool l1_support_changed;
441
442
443 struct platform_device *dmic_dev;
444
445
446 struct delayed_work d0i3_work;
447
448
449 struct sdw_intel_acpi_info info;
450
451
452 struct sdw_intel_ctx *sdw;
453
454
455 bool clk_config_lpro;
456};
457
458static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
459{
460 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
461
462 return &hda->hbus.core;
463}
464
465static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
466{
467 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
468
469 return &hda->hbus;
470}
471
472struct sof_intel_hda_stream {
473 struct snd_sof_dev *sdev;
474 struct hdac_ext_stream hda_stream;
475 struct sof_intel_stream stream;
476 int host_reserved;
477 u32 flags;
478};
479
480#define hstream_to_sof_hda_stream(hstream) \
481 container_of(hstream, struct sof_intel_hda_stream, hda_stream)
482
483#define bus_to_sof_hda(bus) \
484 container_of(bus, struct sof_intel_hda_dev, hbus.core)
485
486#define SOF_STREAM_SD_OFFSET(s) \
487 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
488 + SOF_HDA_ADSP_LOADER_BASE)
489
490
491
492
493int hda_dsp_probe(struct snd_sof_dev *sdev);
494int hda_dsp_remove(struct snd_sof_dev *sdev);
495int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
496 unsigned int core_mask);
497int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
498 unsigned int core_mask);
499int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
500int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
501int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
502int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
503int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
504bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
505 unsigned int core_mask);
506int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
507 unsigned int core_mask);
508void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
509void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
510
511int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
512 const struct sof_dsp_power_state *target_state);
513
514int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state);
515int hda_dsp_resume(struct snd_sof_dev *sdev);
516int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
517int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
518int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
519int hda_dsp_shutdown(struct snd_sof_dev *sdev);
520int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
521void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
522void hda_ipc_dump(struct snd_sof_dev *sdev);
523void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
524void hda_dsp_d0i3_work(struct work_struct *work);
525
526
527
528
529u32 hda_dsp_get_mult_div(struct snd_sof_dev *sdev, int rate);
530u32 hda_dsp_get_bits(struct snd_sof_dev *sdev, int sample_bits);
531int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
532 struct snd_pcm_substream *substream);
533int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
534 struct snd_pcm_substream *substream);
535int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
536 struct snd_pcm_substream *substream,
537 struct snd_pcm_hw_params *params,
538 struct sof_ipc_stream_params *ipc_params);
539int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
540 struct snd_pcm_substream *substream);
541int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
542 struct snd_pcm_substream *substream, int cmd);
543snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
544 struct snd_pcm_substream *substream);
545
546
547
548
549
550int hda_dsp_stream_init(struct snd_sof_dev *sdev);
551void hda_dsp_stream_free(struct snd_sof_dev *sdev);
552int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
553 struct hdac_ext_stream *stream,
554 struct snd_dma_buffer *dmab,
555 struct snd_pcm_hw_params *params);
556int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
557 struct snd_dma_buffer *dmab,
558 struct snd_pcm_hw_params *params);
559int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
560 struct hdac_ext_stream *stream, int cmd);
561irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
562int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
563 struct snd_dma_buffer *dmab,
564 struct hdac_stream *stream);
565bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
566bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
567
568struct hdac_ext_stream *
569 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
570int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
571int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
572 struct hdac_ext_stream *stream,
573 int enable, u32 size);
574
575void hda_ipc_msg_data(struct snd_sof_dev *sdev,
576 struct snd_pcm_substream *substream,
577 void *p, size_t sz);
578int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
579 struct snd_pcm_substream *substream,
580 const struct sof_ipc_pcm_params_reply *reply);
581
582#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
583
584
585
586int hda_probe_compr_assign(struct snd_sof_dev *sdev,
587 struct snd_compr_stream *cstream,
588 struct snd_soc_dai *dai);
589int hda_probe_compr_free(struct snd_sof_dev *sdev,
590 struct snd_compr_stream *cstream,
591 struct snd_soc_dai *dai);
592int hda_probe_compr_set_params(struct snd_sof_dev *sdev,
593 struct snd_compr_stream *cstream,
594 struct snd_compr_params *params,
595 struct snd_soc_dai *dai);
596int hda_probe_compr_trigger(struct snd_sof_dev *sdev,
597 struct snd_compr_stream *cstream, int cmd,
598 struct snd_soc_dai *dai);
599int hda_probe_compr_pointer(struct snd_sof_dev *sdev,
600 struct snd_compr_stream *cstream,
601 struct snd_compr_tstamp *tstamp,
602 struct snd_soc_dai *dai);
603#endif
604
605
606
607
608int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
609 struct snd_sof_ipc_msg *msg);
610void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
611int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
612int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
613
614irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
615int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
616
617
618
619
620int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
621int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev);
622int hda_dsp_cl_boot_firmware_iccmax_icl(struct snd_sof_dev *sdev);
623int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
624
625
626int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
627int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
628int hda_dsp_post_fw_run_icl(struct snd_sof_dev *sdev);
629int hda_dsp_core_stall_icl(struct snd_sof_dev *sdev, unsigned int core_mask);
630
631
632int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
633 const struct sof_ext_man_elem_header *hdr);
634
635
636
637
638int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
639void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
640void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
641int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
642void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
643int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
644int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
645void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
646
647
648
649void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
650
651#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
652
653
654
655void hda_codec_probe_bus(struct snd_sof_dev *sdev,
656 bool hda_codec_use_common_hdmi);
657void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev, bool enable);
658void hda_codec_jack_check(struct snd_sof_dev *sdev);
659
660#endif
661
662#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
663 (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
664 IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
665
666void hda_codec_i915_display_power(struct snd_sof_dev *sdev, bool enable);
667int hda_codec_i915_init(struct snd_sof_dev *sdev);
668int hda_codec_i915_exit(struct snd_sof_dev *sdev);
669
670#else
671
672static inline void hda_codec_i915_display_power(struct snd_sof_dev *sdev,
673 bool enable) { }
674static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
675static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
676
677#endif
678
679
680
681
682int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
683int hda_dsp_trace_release(struct snd_sof_dev *sdev);
684int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
685
686
687
688
689#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
690
691int hda_sdw_startup(struct snd_sof_dev *sdev);
692void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
693void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
694bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
695
696#else
697
698static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
699{
700 return 0;
701}
702
703static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
704{
705 return 0;
706}
707
708static inline int hda_sdw_startup(struct snd_sof_dev *sdev)
709{
710 return 0;
711}
712
713static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
714{
715 return 0;
716}
717
718static inline void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
719{
720}
721
722static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
723{
724 return false;
725}
726
727static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
728{
729 return IRQ_HANDLED;
730}
731
732static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
733{
734 return false;
735}
736
737static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
738{
739}
740
741static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
742{
743 return false;
744}
745
746#endif
747
748
749extern struct snd_soc_dai_driver skl_dai[];
750
751
752
753
754extern const struct snd_sof_dsp_ops sof_apl_ops;
755extern const struct snd_sof_dsp_ops sof_cnl_ops;
756extern const struct snd_sof_dsp_ops sof_tgl_ops;
757extern const struct snd_sof_dsp_ops sof_icl_ops;
758
759extern const struct sof_intel_dsp_desc apl_chip_info;
760extern const struct sof_intel_dsp_desc cnl_chip_info;
761extern const struct sof_intel_dsp_desc skl_chip_info;
762extern const struct sof_intel_dsp_desc icl_chip_info;
763extern const struct sof_intel_dsp_desc tgl_chip_info;
764extern const struct sof_intel_dsp_desc tglh_chip_info;
765extern const struct sof_intel_dsp_desc ehl_chip_info;
766extern const struct sof_intel_dsp_desc jsl_chip_info;
767extern const struct sof_intel_dsp_desc adls_chip_info;
768
769
770void hda_machine_select(struct snd_sof_dev *sdev);
771void hda_set_mach_params(const struct snd_soc_acpi_mach *mach,
772 struct snd_sof_dev *sdev);
773
774
775int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id);
776
777#endif
778