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11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/regmap.h>
17#include <linux/of.h>
18#include <linux/ioport.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/reset.h>
23#include <linux/spinlock.h>
24#include <sound/asoundef.h>
25#include <sound/dmaengine_pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28
29#define SUN4I_SPDIF_CTL (0x00)
30 #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4)
31 #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
32 #define SUN4I_SPDIF_CTL_GEN BIT(1)
33 #define SUN4I_SPDIF_CTL_RESET BIT(0)
34
35#define SUN4I_SPDIF_TXCFG (0x04)
36 #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
37 #define SUN4I_SPDIF_TXCFG_ASS BIT(17)
38 #define SUN4I_SPDIF_TXCFG_NONAUDIO BIT(16)
39 #define SUN4I_SPDIF_TXCFG_TXRATIO(v) ((v) << 4)
40 #define SUN4I_SPDIF_TXCFG_TXRATIO_MASK GENMASK(8, 4)
41 #define SUN4I_SPDIF_TXCFG_FMTRVD GENMASK(3, 2)
42 #define SUN4I_SPDIF_TXCFG_FMT16BIT (0 << 2)
43 #define SUN4I_SPDIF_TXCFG_FMT20BIT (1 << 2)
44 #define SUN4I_SPDIF_TXCFG_FMT24BIT (2 << 2)
45 #define SUN4I_SPDIF_TXCFG_CHSTMODE BIT(1)
46 #define SUN4I_SPDIF_TXCFG_TXEN BIT(0)
47
48#define SUN4I_SPDIF_RXCFG (0x08)
49 #define SUN4I_SPDIF_RXCFG_LOCKFLAG BIT(4)
50 #define SUN4I_SPDIF_RXCFG_CHSTSRC BIT(3)
51 #define SUN4I_SPDIF_RXCFG_CHSTCP BIT(1)
52 #define SUN4I_SPDIF_RXCFG_RXEN BIT(0)
53
54#define SUN4I_SPDIF_TXFIFO (0x0C)
55
56#define SUN4I_SPDIF_RXFIFO (0x10)
57
58#define SUN4I_SPDIF_FCTL (0x14)
59 #define SUN4I_SPDIF_FCTL_FIFOSRC BIT(31)
60 #define SUN4I_SPDIF_FCTL_FTX BIT(17)
61 #define SUN4I_SPDIF_FCTL_FRX BIT(16)
62 #define SUN4I_SPDIF_FCTL_TXTL(v) ((v) << 8)
63 #define SUN4I_SPDIF_FCTL_TXTL_MASK GENMASK(12, 8)
64 #define SUN4I_SPDIF_FCTL_RXTL(v) ((v) << 3)
65 #define SUN4I_SPDIF_FCTL_RXTL_MASK GENMASK(7, 3)
66 #define SUN4I_SPDIF_FCTL_TXIM BIT(2)
67 #define SUN4I_SPDIF_FCTL_RXOM(v) ((v) << 0)
68 #define SUN4I_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
69
70#define SUN50I_H6_SPDIF_FCTL (0x14)
71 #define SUN50I_H6_SPDIF_FCTL_HUB_EN BIT(31)
72 #define SUN50I_H6_SPDIF_FCTL_FTX BIT(30)
73 #define SUN50I_H6_SPDIF_FCTL_FRX BIT(29)
74 #define SUN50I_H6_SPDIF_FCTL_TXTL(v) ((v) << 12)
75 #define SUN50I_H6_SPDIF_FCTL_TXTL_MASK GENMASK(19, 12)
76 #define SUN50I_H6_SPDIF_FCTL_RXTL(v) ((v) << 4)
77 #define SUN50I_H6_SPDIF_FCTL_RXTL_MASK GENMASK(10, 4)
78 #define SUN50I_H6_SPDIF_FCTL_TXIM BIT(2)
79 #define SUN50I_H6_SPDIF_FCTL_RXOM(v) ((v) << 0)
80 #define SUN50I_H6_SPDIF_FCTL_RXOM_MASK GENMASK(1, 0)
81
82#define SUN4I_SPDIF_FSTA (0x18)
83 #define SUN4I_SPDIF_FSTA_TXE BIT(14)
84 #define SUN4I_SPDIF_FSTA_TXECNTSHT (8)
85 #define SUN4I_SPDIF_FSTA_RXA BIT(6)
86 #define SUN4I_SPDIF_FSTA_RXACNTSHT (0)
87
88#define SUN4I_SPDIF_INT (0x1C)
89 #define SUN4I_SPDIF_INT_RXLOCKEN BIT(18)
90 #define SUN4I_SPDIF_INT_RXUNLOCKEN BIT(17)
91 #define SUN4I_SPDIF_INT_RXPARERREN BIT(16)
92 #define SUN4I_SPDIF_INT_TXDRQEN BIT(7)
93 #define SUN4I_SPDIF_INT_TXUIEN BIT(6)
94 #define SUN4I_SPDIF_INT_TXOIEN BIT(5)
95 #define SUN4I_SPDIF_INT_TXEIEN BIT(4)
96 #define SUN4I_SPDIF_INT_RXDRQEN BIT(2)
97 #define SUN4I_SPDIF_INT_RXOIEN BIT(1)
98 #define SUN4I_SPDIF_INT_RXAIEN BIT(0)
99
100#define SUN4I_SPDIF_ISTA (0x20)
101 #define SUN4I_SPDIF_ISTA_RXLOCKSTA BIT(18)
102 #define SUN4I_SPDIF_ISTA_RXUNLOCKSTA BIT(17)
103 #define SUN4I_SPDIF_ISTA_RXPARERRSTA BIT(16)
104 #define SUN4I_SPDIF_ISTA_TXUSTA BIT(6)
105 #define SUN4I_SPDIF_ISTA_TXOSTA BIT(5)
106 #define SUN4I_SPDIF_ISTA_TXESTA BIT(4)
107 #define SUN4I_SPDIF_ISTA_RXOSTA BIT(1)
108 #define SUN4I_SPDIF_ISTA_RXASTA BIT(0)
109
110#define SUN8I_SPDIF_TXFIFO (0x20)
111
112#define SUN4I_SPDIF_TXCNT (0x24)
113
114#define SUN4I_SPDIF_RXCNT (0x28)
115
116#define SUN4I_SPDIF_TXCHSTA0 (0x2C)
117 #define SUN4I_SPDIF_TXCHSTA0_CLK(v) ((v) << 28)
118 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ(v) ((v) << 24)
119 #define SUN4I_SPDIF_TXCHSTA0_SAMFREQ_MASK GENMASK(27, 24)
120 #define SUN4I_SPDIF_TXCHSTA0_CHNUM(v) ((v) << 20)
121 #define SUN4I_SPDIF_TXCHSTA0_CHNUM_MASK GENMASK(23, 20)
122 #define SUN4I_SPDIF_TXCHSTA0_SRCNUM(v) ((v) << 16)
123 #define SUN4I_SPDIF_TXCHSTA0_CATACOD(v) ((v) << 8)
124 #define SUN4I_SPDIF_TXCHSTA0_MODE(v) ((v) << 6)
125 #define SUN4I_SPDIF_TXCHSTA0_EMPHASIS(v) ((v) << 3)
126 #define SUN4I_SPDIF_TXCHSTA0_CP BIT(2)
127 #define SUN4I_SPDIF_TXCHSTA0_AUDIO BIT(1)
128 #define SUN4I_SPDIF_TXCHSTA0_PRO BIT(0)
129
130#define SUN4I_SPDIF_TXCHSTA1 (0x30)
131 #define SUN4I_SPDIF_TXCHSTA1_CGMSA(v) ((v) << 8)
132 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ(v) ((v) << 4)
133 #define SUN4I_SPDIF_TXCHSTA1_ORISAMFREQ_MASK GENMASK(7, 4)
134 #define SUN4I_SPDIF_TXCHSTA1_SAMWORDLEN(v) ((v) << 1)
135 #define SUN4I_SPDIF_TXCHSTA1_MAXWORDLEN BIT(0)
136
137#define SUN4I_SPDIF_RXCHSTA0 (0x34)
138 #define SUN4I_SPDIF_RXCHSTA0_CLK(v) ((v) << 28)
139 #define SUN4I_SPDIF_RXCHSTA0_SAMFREQ(v) ((v) << 24)
140 #define SUN4I_SPDIF_RXCHSTA0_CHNUM(v) ((v) << 20)
141 #define SUN4I_SPDIF_RXCHSTA0_SRCNUM(v) ((v) << 16)
142 #define SUN4I_SPDIF_RXCHSTA0_CATACOD(v) ((v) << 8)
143 #define SUN4I_SPDIF_RXCHSTA0_MODE(v) ((v) << 6)
144 #define SUN4I_SPDIF_RXCHSTA0_EMPHASIS(v) ((v) << 3)
145 #define SUN4I_SPDIF_RXCHSTA0_CP BIT(2)
146 #define SUN4I_SPDIF_RXCHSTA0_AUDIO BIT(1)
147 #define SUN4I_SPDIF_RXCHSTA0_PRO BIT(0)
148
149#define SUN4I_SPDIF_RXCHSTA1 (0x38)
150 #define SUN4I_SPDIF_RXCHSTA1_CGMSA(v) ((v) << 8)
151 #define SUN4I_SPDIF_RXCHSTA1_ORISAMFREQ(v) ((v) << 4)
152 #define SUN4I_SPDIF_RXCHSTA1_SAMWORDLEN(v) ((v) << 1)
153 #define SUN4I_SPDIF_RXCHSTA1_MAXWORDLEN BIT(0)
154
155
156#define SUN4I_SPDIF_SAMFREQ_44_1KHZ 0x0
157#define SUN4I_SPDIF_SAMFREQ_NOT_INDICATED 0x1
158#define SUN4I_SPDIF_SAMFREQ_48KHZ 0x2
159#define SUN4I_SPDIF_SAMFREQ_32KHZ 0x3
160#define SUN4I_SPDIF_SAMFREQ_22_05KHZ 0x4
161#define SUN4I_SPDIF_SAMFREQ_24KHZ 0x6
162#define SUN4I_SPDIF_SAMFREQ_88_2KHZ 0x8
163#define SUN4I_SPDIF_SAMFREQ_76_8KHZ 0x9
164#define SUN4I_SPDIF_SAMFREQ_96KHZ 0xa
165#define SUN4I_SPDIF_SAMFREQ_176_4KHZ 0xc
166#define SUN4I_SPDIF_SAMFREQ_192KHZ 0xe
167
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174
175struct sun4i_spdif_quirks {
176 unsigned int reg_dac_txdata;
177 bool has_reset;
178 unsigned int val_fctl_ftx;
179 unsigned int mclk_multiplier;
180};
181
182struct sun4i_spdif_dev {
183 struct platform_device *pdev;
184 struct clk *spdif_clk;
185 struct clk *apb_clk;
186 struct reset_control *rst;
187 struct snd_soc_dai_driver cpu_dai_drv;
188 struct regmap *regmap;
189 struct snd_dmaengine_dai_dma_data dma_params_tx;
190 const struct sun4i_spdif_quirks *quirks;
191 spinlock_t lock;
192};
193
194static void sun4i_spdif_configure(struct sun4i_spdif_dev *host)
195{
196 const struct sun4i_spdif_quirks *quirks = host->quirks;
197
198
199 regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
200
201
202 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
203 quirks->val_fctl_ftx, quirks->val_fctl_ftx);
204
205
206 regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
207 SUN4I_SPDIF_FCTL_TXIM, 0);
208
209
210 regmap_write(host->regmap, SUN4I_SPDIF_TXCNT, 0);
211}
212
213static void sun4i_snd_txctrl_on(struct snd_pcm_substream *substream,
214 struct sun4i_spdif_dev *host)
215{
216 if (substream->runtime->channels == 1)
217 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
218 SUN4I_SPDIF_TXCFG_SINGLEMOD,
219 SUN4I_SPDIF_TXCFG_SINGLEMOD);
220
221
222 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
223 SUN4I_SPDIF_TXCFG_TXEN, SUN4I_SPDIF_TXCFG_TXEN);
224
225
226 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
227 SUN4I_SPDIF_INT_TXDRQEN, SUN4I_SPDIF_INT_TXDRQEN);
228
229
230 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
231 SUN4I_SPDIF_CTL_GEN, SUN4I_SPDIF_CTL_GEN);
232}
233
234static void sun4i_snd_txctrl_off(struct snd_pcm_substream *substream,
235 struct sun4i_spdif_dev *host)
236{
237
238 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
239 SUN4I_SPDIF_TXCFG_TXEN, 0);
240
241
242 regmap_update_bits(host->regmap, SUN4I_SPDIF_INT,
243 SUN4I_SPDIF_INT_TXDRQEN, 0);
244
245
246 regmap_update_bits(host->regmap, SUN4I_SPDIF_CTL,
247 SUN4I_SPDIF_CTL_GEN, 0);
248}
249
250static int sun4i_spdif_startup(struct snd_pcm_substream *substream,
251 struct snd_soc_dai *cpu_dai)
252{
253 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
254 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(snd_soc_rtd_to_cpu(rtd, 0));
255
256 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
257 return -EINVAL;
258
259 sun4i_spdif_configure(host);
260
261 return 0;
262}
263
264static int sun4i_spdif_hw_params(struct snd_pcm_substream *substream,
265 struct snd_pcm_hw_params *params,
266 struct snd_soc_dai *cpu_dai)
267{
268 int ret = 0;
269 int fmt;
270 unsigned long rate = params_rate(params);
271 u32 mclk_div = 0;
272 unsigned int mclk = 0;
273 u32 reg_val;
274 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
275 struct platform_device *pdev = host->pdev;
276
277
278 switch (params_channels(params)) {
279 case 1:
280 case 2:
281 fmt = 0;
282 break;
283 case 4:
284 fmt = SUN4I_SPDIF_TXCFG_NONAUDIO;
285 break;
286 default:
287 return -EINVAL;
288 }
289
290 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
291 switch (params_format(params)) {
292 case SNDRV_PCM_FORMAT_S16_LE:
293 fmt |= SUN4I_SPDIF_TXCFG_FMT16BIT;
294 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
295 break;
296 case SNDRV_PCM_FORMAT_S20_3LE:
297 fmt |= SUN4I_SPDIF_TXCFG_FMT20BIT;
298 break;
299 case SNDRV_PCM_FORMAT_S24_LE:
300 case SNDRV_PCM_FORMAT_S32_LE:
301 fmt |= SUN4I_SPDIF_TXCFG_FMT24BIT;
302 break;
303 default:
304 return -EINVAL;
305 }
306
307 switch (rate) {
308 case 22050:
309 case 44100:
310 case 88200:
311 case 176400:
312 mclk = 22579200;
313 break;
314 case 24000:
315 case 32000:
316 case 48000:
317 case 96000:
318 case 192000:
319 mclk = 24576000;
320 break;
321 default:
322 return -EINVAL;
323 }
324 mclk *= host->quirks->mclk_multiplier;
325
326 ret = clk_set_rate(host->spdif_clk, mclk);
327 if (ret < 0) {
328 dev_err(&pdev->dev,
329 "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
330 return ret;
331 }
332
333 switch (rate) {
334 case 22050:
335 case 24000:
336 mclk_div = 8;
337 break;
338 case 32000:
339 mclk_div = 6;
340 break;
341 case 44100:
342 case 48000:
343 mclk_div = 4;
344 break;
345 case 88200:
346 case 96000:
347 mclk_div = 2;
348 break;
349 case 176400:
350 case 192000:
351 mclk_div = 1;
352 break;
353 default:
354 return -EINVAL;
355 }
356 mclk_div *= host->quirks->mclk_multiplier;
357
358 reg_val = 0;
359 reg_val |= SUN4I_SPDIF_TXCFG_ASS;
360 reg_val |= fmt;
361 reg_val |= SUN4I_SPDIF_TXCFG_CHSTMODE;
362 reg_val |= SUN4I_SPDIF_TXCFG_TXRATIO(mclk_div - 1);
363 regmap_write(host->regmap, SUN4I_SPDIF_TXCFG, reg_val);
364
365 return 0;
366}
367
368static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
369 struct snd_soc_dai *dai)
370{
371 int ret = 0;
372 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
373
374 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
375 return -EINVAL;
376
377 switch (cmd) {
378 case SNDRV_PCM_TRIGGER_START:
379 case SNDRV_PCM_TRIGGER_RESUME:
380 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
381 sun4i_snd_txctrl_on(substream, host);
382 break;
383
384 case SNDRV_PCM_TRIGGER_STOP:
385 case SNDRV_PCM_TRIGGER_SUSPEND:
386 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
387 sun4i_snd_txctrl_off(substream, host);
388 break;
389
390 default:
391 ret = -EINVAL;
392 break;
393 }
394 return ret;
395}
396
397static int sun4i_spdif_info(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_info *uinfo)
399{
400 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
401 uinfo->count = 1;
402
403 return 0;
404}
405
406static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408{
409 u8 *status = ucontrol->value.iec958.status;
410
411 status[0] = 0xff;
412 status[1] = 0xff;
413 status[2] = 0xff;
414 status[3] = 0xff;
415 status[4] = 0xff;
416 status[5] = 0x03;
417
418 return 0;
419}
420
421static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
425 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
426 u8 *status = ucontrol->value.iec958.status;
427 unsigned long flags;
428 unsigned int reg;
429
430 spin_lock_irqsave(&host->lock, flags);
431
432 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®);
433
434 status[0] = reg & 0xff;
435 status[1] = (reg >> 8) & 0xff;
436 status[2] = (reg >> 16) & 0xff;
437 status[3] = (reg >> 24) & 0xff;
438
439 regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, ®);
440
441 status[4] = reg & 0xff;
442 status[5] = (reg >> 8) & 0x3;
443
444 spin_unlock_irqrestore(&host->lock, flags);
445
446 return 0;
447}
448
449static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451{
452 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
453 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
454 u8 *status = ucontrol->value.iec958.status;
455 unsigned long flags;
456 unsigned int reg;
457 bool chg0, chg1;
458
459 spin_lock_irqsave(&host->lock, flags);
460
461 reg = (u32)status[3] << 24;
462 reg |= (u32)status[2] << 16;
463 reg |= (u32)status[1] << 8;
464 reg |= (u32)status[0];
465
466 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA0,
467 GENMASK(31,0), reg, &chg0);
468
469 reg = (u32)status[5] << 8;
470 reg |= (u32)status[4];
471
472 regmap_update_bits_check(host->regmap, SUN4I_SPDIF_TXCHSTA1,
473 GENMASK(9,0), reg, &chg1);
474
475 reg = SUN4I_SPDIF_TXCFG_CHSTMODE;
476 if (status[0] & IEC958_AES0_NONAUDIO)
477 reg |= SUN4I_SPDIF_TXCFG_NONAUDIO;
478
479 regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG,
480 SUN4I_SPDIF_TXCFG_CHSTMODE |
481 SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
482
483 spin_unlock_irqrestore(&host->lock, flags);
484
485 return chg0 || chg1;
486}
487
488static struct snd_kcontrol_new sun4i_spdif_controls[] = {
489 {
490 .access = SNDRV_CTL_ELEM_ACCESS_READ,
491 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
492 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
493 .info = sun4i_spdif_info,
494 .get = sun4i_spdif_get_status_mask
495 },
496 {
497 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
498 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
499 .info = sun4i_spdif_info,
500 .get = sun4i_spdif_get_status,
501 .put = sun4i_spdif_set_status
502 }
503};
504
505static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai)
506{
507 struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai);
508
509 snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL);
510 snd_soc_add_dai_controls(dai, sun4i_spdif_controls,
511 ARRAY_SIZE(sun4i_spdif_controls));
512
513 return 0;
514}
515
516static const struct snd_soc_dai_ops sun4i_spdif_dai_ops = {
517 .probe = sun4i_spdif_soc_dai_probe,
518 .startup = sun4i_spdif_startup,
519 .trigger = sun4i_spdif_trigger,
520 .hw_params = sun4i_spdif_hw_params,
521};
522
523static const struct regmap_config sun4i_spdif_regmap_config = {
524 .reg_bits = 32,
525 .reg_stride = 4,
526 .val_bits = 32,
527 .max_register = SUN4I_SPDIF_RXCHSTA1,
528};
529
530#define SUN4I_RATES SNDRV_PCM_RATE_8000_192000
531
532#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
533 SNDRV_PCM_FMTBIT_S20_3LE | \
534 SNDRV_PCM_FMTBIT_S24_LE | \
535 SNDRV_PCM_FMTBIT_S32_LE)
536
537static struct snd_soc_dai_driver sun4i_spdif_dai = {
538 .playback = {
539 .channels_min = 1,
540 .channels_max = 2,
541 .rates = SUN4I_RATES,
542 .formats = SUN4I_FORMATS,
543 },
544 .ops = &sun4i_spdif_dai_ops,
545 .name = "spdif",
546};
547
548static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
549 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
550 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
551 .mclk_multiplier = 1,
552};
553
554static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
555 .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
556 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
557 .has_reset = true,
558 .mclk_multiplier = 1,
559};
560
561static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
562 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
563 .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
564 .has_reset = true,
565 .mclk_multiplier = 4,
566};
567
568static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
569 .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
570 .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
571 .has_reset = true,
572 .mclk_multiplier = 1,
573};
574
575static const struct of_device_id sun4i_spdif_of_match[] = {
576 {
577 .compatible = "allwinner,sun4i-a10-spdif",
578 .data = &sun4i_a10_spdif_quirks,
579 },
580 {
581 .compatible = "allwinner,sun6i-a31-spdif",
582 .data = &sun6i_a31_spdif_quirks,
583 },
584 {
585 .compatible = "allwinner,sun8i-h3-spdif",
586 .data = &sun8i_h3_spdif_quirks,
587 },
588 {
589 .compatible = "allwinner,sun50i-h6-spdif",
590 .data = &sun50i_h6_spdif_quirks,
591 },
592 {
593 .compatible = "allwinner,sun50i-h616-spdif",
594
595 .data = &sun50i_h6_spdif_quirks,
596 },
597 { }
598};
599MODULE_DEVICE_TABLE(of, sun4i_spdif_of_match);
600
601static const struct snd_soc_component_driver sun4i_spdif_component = {
602 .name = "sun4i-spdif",
603 .legacy_dai_naming = 1,
604};
605
606static int sun4i_spdif_runtime_suspend(struct device *dev)
607{
608 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
609
610 clk_disable_unprepare(host->spdif_clk);
611 clk_disable_unprepare(host->apb_clk);
612
613 return 0;
614}
615
616static int sun4i_spdif_runtime_resume(struct device *dev)
617{
618 struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
619 int ret;
620
621 ret = clk_prepare_enable(host->spdif_clk);
622 if (ret)
623 return ret;
624 ret = clk_prepare_enable(host->apb_clk);
625 if (ret)
626 clk_disable_unprepare(host->spdif_clk);
627
628 return ret;
629}
630
631static int sun4i_spdif_probe(struct platform_device *pdev)
632{
633 struct sun4i_spdif_dev *host;
634 struct resource *res;
635 const struct sun4i_spdif_quirks *quirks;
636 int ret;
637 void __iomem *base;
638
639 dev_dbg(&pdev->dev, "Entered %s\n", __func__);
640
641 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
642 if (!host)
643 return -ENOMEM;
644
645 host->pdev = pdev;
646 spin_lock_init(&host->lock);
647
648
649 memcpy(&host->cpu_dai_drv, &sun4i_spdif_dai, sizeof(sun4i_spdif_dai));
650 host->cpu_dai_drv.name = dev_name(&pdev->dev);
651
652
653 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
654 if (IS_ERR(base))
655 return PTR_ERR(base);
656
657 quirks = of_device_get_match_data(&pdev->dev);
658 if (quirks == NULL) {
659 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
660 return -ENODEV;
661 }
662 host->quirks = quirks;
663
664 host->regmap = devm_regmap_init_mmio(&pdev->dev, base,
665 &sun4i_spdif_regmap_config);
666
667
668 host->apb_clk = devm_clk_get(&pdev->dev, "apb");
669 if (IS_ERR(host->apb_clk)) {
670 dev_err(&pdev->dev, "failed to get a apb clock.\n");
671 return PTR_ERR(host->apb_clk);
672 }
673
674 host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
675 if (IS_ERR(host->spdif_clk)) {
676 dev_err(&pdev->dev, "failed to get a spdif clock.\n");
677 return PTR_ERR(host->spdif_clk);
678 }
679
680 host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
681 host->dma_params_tx.maxburst = 8;
682 host->dma_params_tx.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
683
684 platform_set_drvdata(pdev, host);
685
686 if (quirks->has_reset) {
687 host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
688 NULL);
689 if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
690 ret = -EPROBE_DEFER;
691 dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
692 return ret;
693 }
694 if (!IS_ERR(host->rst))
695 reset_control_deassert(host->rst);
696 }
697
698 ret = devm_snd_soc_register_component(&pdev->dev,
699 &sun4i_spdif_component, &sun4i_spdif_dai, 1);
700 if (ret)
701 return ret;
702
703 pm_runtime_enable(&pdev->dev);
704 if (!pm_runtime_enabled(&pdev->dev)) {
705 ret = sun4i_spdif_runtime_resume(&pdev->dev);
706 if (ret)
707 goto err_unregister;
708 }
709
710 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
711 if (ret)
712 goto err_suspend;
713 return 0;
714err_suspend:
715 if (!pm_runtime_status_suspended(&pdev->dev))
716 sun4i_spdif_runtime_suspend(&pdev->dev);
717err_unregister:
718 pm_runtime_disable(&pdev->dev);
719 return ret;
720}
721
722static void sun4i_spdif_remove(struct platform_device *pdev)
723{
724 pm_runtime_disable(&pdev->dev);
725 if (!pm_runtime_status_suspended(&pdev->dev))
726 sun4i_spdif_runtime_suspend(&pdev->dev);
727}
728
729static const struct dev_pm_ops sun4i_spdif_pm = {
730 RUNTIME_PM_OPS(sun4i_spdif_runtime_suspend,
731 sun4i_spdif_runtime_resume, NULL)
732};
733
734static struct platform_driver sun4i_spdif_driver = {
735 .driver = {
736 .name = "sun4i-spdif",
737 .of_match_table = sun4i_spdif_of_match,
738 .pm = pm_ptr(&sun4i_spdif_pm),
739 },
740 .probe = sun4i_spdif_probe,
741 .remove = sun4i_spdif_remove,
742};
743
744module_platform_driver(sun4i_spdif_driver);
745
746MODULE_AUTHOR("Marcus Cooper <codekipper@gmail.com>");
747MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
748MODULE_DESCRIPTION("Allwinner sun4i SPDIF SoC Interface");
749MODULE_LICENSE("GPL");
750MODULE_ALIAS("platform:sun4i-spdif");
751
