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6
7#include <linux/module.h>
8
9#include "aio.h"
10
11static const struct uniphier_aio_spec uniphier_aio_pxs2[] = {
12
13 {
14 .name = AUD_NAME_PCMIN1,
15 .gname = AUD_GNAME_LINE,
16 .swm = {
17 .type = PORT_TYPE_I2S,
18 .dir = PORT_DIR_INPUT,
19 .rb = { 16, 11, },
20 .ch = { 16, 11, },
21 .iif = { 0, 0, },
22 .iport = { 0, AUD_HW_PCMIN1, },
23 },
24 },
25
26
27 {
28 .name = AUD_NAME_PCMIN2,
29 .gname = AUD_GNAME_AUX,
30 .swm = {
31 .type = PORT_TYPE_I2S,
32 .dir = PORT_DIR_INPUT,
33 .rb = { 17, 12, },
34 .ch = { 17, 12, },
35 .iif = { 1, 1, },
36 .iport = { 1, AUD_HW_PCMIN2, },
37 },
38 },
39
40
41 {
42 .name = AUD_NAME_HPCMOUT1,
43 .gname = AUD_GNAME_HDMI,
44 .swm = {
45 .type = PORT_TYPE_I2S,
46 .dir = PORT_DIR_OUTPUT,
47 .rb = { 0, 0, },
48 .ch = { 0, 0, },
49 .oif = { 0, 0, },
50 .oport = { 3, AUD_HW_HPCMOUT1, },
51 },
52 },
53
54
55 {
56 .name = AUD_NAME_PCMOUT1,
57 .gname = AUD_GNAME_LINE,
58 .swm = {
59 .type = PORT_TYPE_I2S,
60 .dir = PORT_DIR_OUTPUT,
61 .rb = { 1, 1, },
62 .ch = { 1, 1, },
63 .oif = { 1, 1, },
64 .oport = { 0, AUD_HW_PCMOUT1, },
65 },
66 },
67
68
69 {
70 .name = AUD_NAME_PCMOUT2,
71 .gname = AUD_GNAME_AUX,
72 .swm = {
73 .type = PORT_TYPE_I2S,
74 .dir = PORT_DIR_OUTPUT,
75 .rb = { 2, 2, },
76 .ch = { 2, 2, },
77 .oif = { 2, 2, },
78 .oport = { 1, AUD_HW_PCMOUT2, },
79 },
80 },
81
82
83 {
84 .name = AUD_NAME_HIECOUT1,
85 .swm = {
86 .type = PORT_TYPE_SPDIF,
87 .dir = PORT_DIR_OUTPUT,
88 .rb = { 6, 4, },
89 .ch = { 6, 4, },
90 .oif = { 6, 4, },
91 .oport = { 12, AUD_HW_HIECOUT1, },
92 },
93 },
94
95
96 {
97 .name = AUD_NAME_HIECCOMPOUT1,
98 .swm = {
99 .type = PORT_TYPE_SPDIF,
100 .dir = PORT_DIR_OUTPUT,
101 .rb = { 6, 4, },
102 .ch = { 6, 4, },
103 .oif = { 6, 4, },
104 .oport = { 12, AUD_HW_HIECOUT1, },
105 },
106 },
107
108
109 {
110 .name = AUD_NAME_IECOUT1,
111 .swm = {
112 .type = PORT_TYPE_SPDIF,
113 .dir = PORT_DIR_OUTPUT,
114 .rb = { 7, 5, },
115 .ch = { 7, 5, },
116 .oif = { 7, 5, },
117 .oport = { 13, AUD_HW_IECOUT1, },
118 },
119 },
120
121
122 {
123 .name = AUD_NAME_IECCOMPOUT1,
124 .swm = {
125 .type = PORT_TYPE_SPDIF,
126 .dir = PORT_DIR_OUTPUT,
127 .rb = { 7, 5, },
128 .ch = { 7, 5, },
129 .oif = { 7, 5, },
130 .oport = { 13, AUD_HW_IECOUT1, },
131 },
132 },
133};
134
135static const struct uniphier_aio_pll uniphier_aio_pll_pxs2[] = {
136 [AUD_PLL_A1] = { .enable = true, },
137 [AUD_PLL_F1] = { .enable = true, },
138 [AUD_PLL_A2] = { .enable = true, },
139 [AUD_PLL_F2] = { .enable = true, },
140 [AUD_PLL_APLL] = { .enable = true, },
141 [AUD_PLL_HSC0] = { .enable = true, },
142};
143
144static struct snd_soc_dai_driver uniphier_aio_dai_pxs2[] = {
145 {
146 .name = AUD_GNAME_HDMI,
147 .playback = {
148 .stream_name = AUD_NAME_HPCMOUT1,
149 .formats = SNDRV_PCM_FMTBIT_S32_LE,
150 .rates = SNDRV_PCM_RATE_48000,
151 .channels_min = 2,
152 .channels_max = 2,
153 },
154 .ops = &uniphier_aio_i2s_pxs2_ops,
155 },
156 {
157 .name = AUD_GNAME_LINE,
158 .playback = {
159 .stream_name = AUD_NAME_PCMOUT1,
160 .formats = SNDRV_PCM_FMTBIT_S32_LE,
161 .rates = SNDRV_PCM_RATE_48000,
162 .channels_min = 2,
163 .channels_max = 2,
164 },
165 .capture = {
166 .stream_name = AUD_NAME_PCMIN1,
167 .formats = SNDRV_PCM_FMTBIT_S32_LE,
168 .rates = SNDRV_PCM_RATE_48000,
169 .channels_min = 2,
170 .channels_max = 2,
171 },
172 .ops = &uniphier_aio_i2s_pxs2_ops,
173 },
174 {
175 .name = AUD_GNAME_AUX,
176 .playback = {
177 .stream_name = AUD_NAME_PCMOUT2,
178 .formats = SNDRV_PCM_FMTBIT_S32_LE,
179 .rates = SNDRV_PCM_RATE_48000,
180 .channels_min = 2,
181 .channels_max = 2,
182 },
183 .capture = {
184 .stream_name = AUD_NAME_PCMIN2,
185 .formats = SNDRV_PCM_FMTBIT_S32_LE,
186 .rates = SNDRV_PCM_RATE_48000,
187 .channels_min = 2,
188 .channels_max = 2,
189 },
190 .ops = &uniphier_aio_i2s_pxs2_ops,
191 },
192 {
193 .name = AUD_NAME_HIECOUT1,
194 .playback = {
195 .stream_name = AUD_NAME_HIECOUT1,
196 .formats = SNDRV_PCM_FMTBIT_S32_LE,
197 .rates = SNDRV_PCM_RATE_48000,
198 .channels_min = 2,
199 .channels_max = 2,
200 },
201 .ops = &uniphier_aio_spdif_pxs2_ops,
202 },
203 {
204 .name = AUD_NAME_IECOUT1,
205 .playback = {
206 .stream_name = AUD_NAME_IECOUT1,
207 .formats = SNDRV_PCM_FMTBIT_S32_LE,
208 .rates = SNDRV_PCM_RATE_48000,
209 .channels_min = 2,
210 .channels_max = 2,
211 },
212 .ops = &uniphier_aio_spdif_pxs2_ops,
213 },
214 {
215 .name = AUD_NAME_HIECCOMPOUT1,
216 .playback = {
217 .stream_name = AUD_NAME_HIECCOMPOUT1,
218 .channels_min = 1,
219 .channels_max = 1,
220 },
221 .ops = &uniphier_aio_spdif_pxs2_ops2,
222 },
223 {
224 .name = AUD_NAME_IECCOMPOUT1,
225 .playback = {
226 .stream_name = AUD_NAME_IECCOMPOUT1,
227 .channels_min = 1,
228 .channels_max = 1,
229 },
230 .ops = &uniphier_aio_spdif_pxs2_ops2,
231 },
232};
233
234static const struct uniphier_aio_chip_spec uniphier_aio_pxs2_spec = {
235 .specs = uniphier_aio_pxs2,
236 .num_specs = ARRAY_SIZE(uniphier_aio_pxs2),
237 .dais = uniphier_aio_dai_pxs2,
238 .num_dais = ARRAY_SIZE(uniphier_aio_dai_pxs2),
239 .plls = uniphier_aio_pll_pxs2,
240 .num_plls = ARRAY_SIZE(uniphier_aio_pll_pxs2),
241 .addr_ext = 0,
242};
243
244static const struct of_device_id uniphier_aio_of_match[] __maybe_unused = {
245 {
246 .compatible = "socionext,uniphier-pxs2-aio",
247 .data = &uniphier_aio_pxs2_spec,
248 },
249 {},
250};
251MODULE_DEVICE_TABLE(of, uniphier_aio_of_match);
252
253static struct platform_driver uniphier_aio_driver = {
254 .driver = {
255 .name = "snd-uniphier-aio-pxs2",
256 .of_match_table = of_match_ptr(uniphier_aio_of_match),
257 },
258 .probe = uniphier_aio_probe,
259 .remove = uniphier_aio_remove,
260};
261module_platform_driver(uniphier_aio_driver);
262
263MODULE_AUTHOR("Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>");
264MODULE_DESCRIPTION("UniPhier PXs2 AIO driver.");
265MODULE_LICENSE("GPL v2");
266
