1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5#include <linux/bits.h> 6 7/* 8 * CPU model specific register (MSR) numbers. 9 * 10 * Do not add new entries to this file unless the definitions are shared 11 * between multiple compilation units. 12 */ 13 14/* x86-64 specific MSRs */ 15#define MSR_EFER 0xc0000080 /* extended feature register */ 16#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 17#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 18#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 19#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 20#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 21#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 22#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 23#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 24 25/* EFER bits: */ 26#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 27#define _EFER_LME 8 /* Long mode enable */ 28#define _EFER_LMA 10 /* Long mode active (read-only) */ 29#define _EFER_NX 11 /* No execute enable */ 30#define _EFER_SVME 12 /* Enable virtualization */ 31#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 32#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 33 34#define EFER_SCE (1<<_EFER_SCE) 35#define EFER_LME (1<<_EFER_LME) 36#define EFER_LMA (1<<_EFER_LMA) 37#define EFER_NX (1<<_EFER_NX) 38#define EFER_SVME (1<<_EFER_SVME) 39#define EFER_LMSLE (1<<_EFER_LMSLE) 40#define EFER_FFXSR (1<<_EFER_FFXSR) 41 42/* Intel MSRs. Some also available on other CPUs */ 43 44#define MSR_TEST_CTRL 0x00000033 45#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 46#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) 47 48#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 49#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */ 50#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */ 51#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */ 52#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 53#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 54 55#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 56#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ 57 58#define MSR_PPIN_CTL 0x0000004e 59#define MSR_PPIN 0x0000004f 60 61#define MSR_IA32_PERFCTR0 0x000000c1 62#define MSR_IA32_PERFCTR1 0x000000c2 63#define MSR_FSB_FREQ 0x000000cd 64#define MSR_PLATFORM_INFO 0x000000ce 65#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 66#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 67 68#define MSR_IA32_UMWAIT_CONTROL 0xe1 69#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0) 70#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1) 71/* 72 * The time field is bit[31:2], but representing a 32bit value with 73 * bit[1:0] zero. 74 */ 75#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U) 76 77/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */ 78#define MSR_IA32_CORE_CAPS 0x000000cf 79#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5 80#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT) 81 82#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 83#define NHM_C3_AUTO_DEMOTE (1UL << 25) 84#define NHM_C1_AUTO_DEMOTE (1UL << 26) 85#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 86#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 87#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 88 89#define MSR_MTRRcap 0x000000fe 90 91#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 92#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */ 93#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */ 94#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */ 95#define ARCH_CAP_SSB_NO BIT(4) /* 96 * Not susceptible to Speculative Store Bypass 97 * attack, so no Speculative Store Bypass 98 * control required. 99 */ 100#define ARCH_CAP_MDS_NO BIT(5) /* 101 * Not susceptible to 102 * Microarchitectural Data 103 * Sampling (MDS) vulnerabilities. 104 */ 105#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /* 106 * The processor is not susceptible to a 107 * machine check error due to modifying the 108 * code page size along with either the 109 * physical address or cache type 110 * without TLB invalidation. 111 */ 112#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */ 113#define ARCH_CAP_TAA_NO BIT(8) /* 114 * Not susceptible to 115 * TSX Async Abort (TAA) vulnerabilities. 116 */ 117 118#define MSR_IA32_FLUSH_CMD 0x0000010b 119#define L1D_FLUSH BIT(0) /* 120 * Writeback and invalidate the 121 * L1 data cache. 122 */ 123 124#define MSR_IA32_BBL_CR_CTL 0x00000119 125#define MSR_IA32_BBL_CR_CTL3 0x0000011e 126 127#define MSR_IA32_TSX_CTRL 0x00000122 128#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */ 129#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */ 130 131/* SRBDS support */ 132#define MSR_IA32_MCU_OPT_CTRL 0x00000123 133#define RNGDS_MITG_DIS BIT(0) 134 135#define MSR_IA32_SYSENTER_CS 0x00000174 136#define MSR_IA32_SYSENTER_ESP 0x00000175 137#define MSR_IA32_SYSENTER_EIP 0x00000176 138 139#define MSR_IA32_MCG_CAP 0x00000179 140#define MSR_IA32_MCG_STATUS 0x0000017a 141#define MSR_IA32_MCG_CTL 0x0000017b 142#define MSR_ERROR_CONTROL 0x0000017f 143#define MSR_IA32_MCG_EXT_CTL 0x000004d0 144 145#define MSR_OFFCORE_RSP_0 0x000001a6 146#define MSR_OFFCORE_RSP_1 0x000001a7 147#define MSR_TURBO_RATIO_LIMIT 0x000001ad 148#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 149#define MSR_TURBO_RATIO_LIMIT2 0x000001af 150 151#define MSR_LBR_SELECT 0x000001c8 152#define MSR_LBR_TOS 0x000001c9 153 154#define MSR_IA32_POWER_CTL 0x000001fc 155#define MSR_IA32_POWER_CTL_BIT_EE 19 156 157#define MSR_LBR_NHM_FROM 0x00000680 158#define MSR_LBR_NHM_TO 0x000006c0 159#define MSR_LBR_CORE_FROM 0x00000040 160#define MSR_LBR_CORE_TO 0x00000060 161 162#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 163#define LBR_INFO_MISPRED BIT_ULL(63) 164#define LBR_INFO_IN_TX BIT_ULL(62) 165#define LBR_INFO_ABORT BIT_ULL(61) 166#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) 167#define LBR_INFO_CYCLES 0xffff 168#define LBR_INFO_BR_TYPE_OFFSET 56 169#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) 170 171#define MSR_ARCH_LBR_CTL 0x000014ce 172#define ARCH_LBR_CTL_LBREN BIT(0) 173#define ARCH_LBR_CTL_CPL_OFFSET 1 174#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET) 175#define ARCH_LBR_CTL_STACK_OFFSET 3 176#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET) 177#define ARCH_LBR_CTL_FILTER_OFFSET 16 178#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET) 179#define MSR_ARCH_LBR_DEPTH 0x000014cf 180#define MSR_ARCH_LBR_FROM_0 0x00001500 181#define MSR_ARCH_LBR_TO_0 0x00001600 182#define MSR_ARCH_LBR_INFO_0 0x00001200 183 184#define MSR_IA32_PEBS_ENABLE 0x000003f1 185#define MSR_PEBS_DATA_CFG 0x000003f2 186#define MSR_IA32_DS_AREA 0x00000600 187#define MSR_IA32_PERF_CAPABILITIES 0x00000345 188#define PERF_CAP_METRICS_IDX 15 189#define PERF_CAP_PT_IDX 16 190 191#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 192 193#define MSR_IA32_RTIT_CTL 0x00000570 194#define RTIT_CTL_TRACEEN BIT(0) 195#define RTIT_CTL_CYCLEACC BIT(1) 196#define RTIT_CTL_OS BIT(2) 197#define RTIT_CTL_USR BIT(3) 198#define RTIT_CTL_PWR_EVT_EN BIT(4) 199#define RTIT_CTL_FUP_ON_PTW BIT(5) 200#define RTIT_CTL_FABRIC_EN BIT(6) 201#define RTIT_CTL_CR3EN BIT(7) 202#define RTIT_CTL_TOPA BIT(8) 203#define RTIT_CTL_MTC_EN BIT(9) 204#define RTIT_CTL_TSC_EN BIT(10) 205#define RTIT_CTL_DISRETC BIT(11) 206#define RTIT_CTL_PTW_EN BIT(12) 207#define RTIT_CTL_BRANCH_EN BIT(13) 208#define RTIT_CTL_MTC_RANGE_OFFSET 14 209#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET) 210#define RTIT_CTL_CYC_THRESH_OFFSET 19 211#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET) 212#define RTIT_CTL_PSB_FREQ_OFFSET 24 213#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET) 214#define RTIT_CTL_ADDR0_OFFSET 32 215#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET) 216#define RTIT_CTL_ADDR1_OFFSET 36 217#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET) 218#define RTIT_CTL_ADDR2_OFFSET 40 219#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET) 220#define RTIT_CTL_ADDR3_OFFSET 44 221#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET) 222#define MSR_IA32_RTIT_STATUS 0x00000571 223#define RTIT_STATUS_FILTEREN BIT(0) 224#define RTIT_STATUS_CONTEXTEN BIT(1) 225#define RTIT_STATUS_TRIGGEREN BIT(2) 226#define RTIT_STATUS_BUFFOVF BIT(3) 227#define RTIT_STATUS_ERROR BIT(4) 228#define RTIT_STATUS_STOPPED BIT(5) 229#define RTIT_STATUS_BYTECNT_OFFSET 32 230#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET) 231#define MSR_IA32_RTIT_ADDR0_A 0x00000580 232#define MSR_IA32_RTIT_ADDR0_B 0x00000581 233#define MSR_IA32_RTIT_ADDR1_A 0x00000582 234#define MSR_IA32_RTIT_ADDR1_B 0x00000583 235#define MSR_IA32_RTIT_ADDR2_A 0x00000584 236#define MSR_IA32_RTIT_ADDR2_B 0x00000585 237#define MSR_IA32_RTIT_ADDR3_A 0x00000586 238#define MSR_IA32_RTIT_ADDR3_B 0x00000587 239#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 240#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 241#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 242 243#define MSR_MTRRfix64K_00000 0x00000250 244#define MSR_MTRRfix16K_80000 0x00000258 245#define MSR_MTRRfix16K_A0000 0x00000259 246#define MSR_MTRRfix4K_C0000 0x00000268 247#define MSR_MTRRfix4K_C8000 0x00000269 248#define MSR_MTRRfix4K_D0000 0x0000026a 249#define MSR_MTRRfix4K_D8000 0x0000026b 250#define MSR_MTRRfix4K_E0000 0x0000026c 251#define MSR_MTRRfix4K_E8000 0x0000026d 252#define MSR_MTRRfix4K_F0000 0x0000026e 253#define MSR_MTRRfix4K_F8000 0x0000026f 254#define MSR_MTRRdefType 0x000002ff 255 256#define MSR_IA32_CR_PAT 0x00000277 257 258#define MSR_IA32_DEBUGCTLMSR 0x000001d9 259#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 260#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 261#define MSR_IA32_LASTINTFROMIP 0x000001dd 262#define MSR_IA32_LASTINTTOIP 0x000001de 263 264#define MSR_IA32_PASID 0x00000d93 265#define MSR_IA32_PASID_VALID BIT_ULL(31) 266 267/* DEBUGCTLMSR bits (others vary by model): */ 268#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 269#define DEBUGCTLMSR_BTF_SHIFT 1 270#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 271#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2) 272#define DEBUGCTLMSR_TR (1UL << 6) 273#define DEBUGCTLMSR_BTS (1UL << 7) 274#define DEBUGCTLMSR_BTINT (1UL << 8) 275#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 276#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 277#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 278#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12) 279#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 280#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 281 282#define MSR_PEBS_FRONTEND 0x000003f7 283 284#define MSR_IA32_MC0_CTL 0x00000400 285#define MSR_IA32_MC0_STATUS 0x00000401 286#define MSR_IA32_MC0_ADDR 0x00000402 287#define MSR_IA32_MC0_MISC 0x00000403 288 289/* C-state Residency Counters */ 290#define MSR_PKG_C3_RESIDENCY 0x000003f8 291#define MSR_PKG_C6_RESIDENCY 0x000003f9 292#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 293#define MSR_PKG_C7_RESIDENCY 0x000003fa 294#define MSR_CORE_C3_RESIDENCY 0x000003fc 295#define MSR_CORE_C6_RESIDENCY 0x000003fd 296#define MSR_CORE_C7_RESIDENCY 0x000003fe 297#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 298#define MSR_PKG_C2_RESIDENCY 0x0000060d 299#define MSR_PKG_C8_RESIDENCY 0x00000630 300#define MSR_PKG_C9_RESIDENCY 0x00000631 301#define MSR_PKG_C10_RESIDENCY 0x00000632 302 303/* Interrupt Response Limit */ 304#define MSR_PKGC3_IRTL 0x0000060a 305#define MSR_PKGC6_IRTL 0x0000060b 306#define MSR_PKGC7_IRTL 0x0000060c 307#define MSR_PKGC8_IRTL 0x00000633 308#define MSR_PKGC9_IRTL 0x00000634 309#define MSR_PKGC10_IRTL 0x00000635 310 311/* Run Time Average Power Limiting (RAPL) Interface */ 312 313#define MSR_RAPL_POWER_UNIT 0x00000606 314 315#define MSR_PKG_POWER_LIMIT 0x00000610 316#define MSR_PKG_ENERGY_STATUS 0x00000611 317#define MSR_PKG_PERF_STATUS 0x00000613 318#define MSR_PKG_POWER_INFO 0x00000614 319 320#define MSR_DRAM_POWER_LIMIT 0x00000618 321#define MSR_DRAM_ENERGY_STATUS 0x00000619 322#define MSR_DRAM_PERF_STATUS 0x0000061b 323#define MSR_DRAM_POWER_INFO 0x0000061c 324 325#define MSR_PP0_POWER_LIMIT 0x00000638 326#define MSR_PP0_ENERGY_STATUS 0x00000639 327#define MSR_PP0_POLICY 0x0000063a 328#define MSR_PP0_PERF_STATUS 0x0000063b 329 330#define MSR_PP1_POWER_LIMIT 0x00000640 331#define MSR_PP1_ENERGY_STATUS 0x00000641 332#define MSR_PP1_POLICY 0x00000642 333 334#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299 335#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a 336#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b 337 338/* Config TDP MSRs */ 339#define MSR_CONFIG_TDP_NOMINAL 0x00000648 340#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 341#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 342#define MSR_CONFIG_TDP_CONTROL 0x0000064B 343#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 344 345#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 346 347#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 348#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 349#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 350#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 351 352#define MSR_CORE_C1_RES 0x00000660 353#define MSR_MODULE_C6_RES_MS 0x00000664 354 355#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 356#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 357 358#define MSR_ATOM_CORE_RATIOS 0x0000066a 359#define MSR_ATOM_CORE_VIDS 0x0000066b 360#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 361#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 362 363 364#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 365#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 366#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 367 368/* Hardware P state interface */ 369#define MSR_PPERF 0x0000064e 370#define MSR_PERF_LIMIT_REASONS 0x0000064f 371#define MSR_PM_ENABLE 0x00000770 372#define MSR_HWP_CAPABILITIES 0x00000771 373#define MSR_HWP_REQUEST_PKG 0x00000772 374#define MSR_HWP_INTERRUPT 0x00000773 375#define MSR_HWP_REQUEST 0x00000774 376#define MSR_HWP_STATUS 0x00000777 377 378/* CPUID.6.EAX */ 379#define HWP_BASE_BIT (1<<7) 380#define HWP_NOTIFICATIONS_BIT (1<<8) 381#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 382#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 383#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 384 385/* IA32_HWP_CAPABILITIES */ 386#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 387#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 388#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 389#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 390 391/* IA32_HWP_REQUEST */ 392#define HWP_MIN_PERF(x) (x & 0xff) 393#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 394#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 395#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 396#define HWP_EPP_PERFORMANCE 0x00 397#define HWP_EPP_BALANCE_PERFORMANCE 0x80 398#define HWP_EPP_BALANCE_POWERSAVE 0xC0 399#define HWP_EPP_POWERSAVE 0xFF 400#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 401#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 402 403/* IA32_HWP_STATUS */ 404#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 405#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 406 407/* IA32_HWP_INTERRUPT */ 408#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 409#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 410 411#define MSR_AMD64_MC0_MASK 0xc0010044 412 413#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 414#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 415#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 416#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 417 418#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 419 420/* These are consecutive and not in the normal 4er MCE bank block */ 421#define MSR_IA32_MC0_CTL2 0x00000280 422#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 423 424#define MSR_P6_PERFCTR0 0x000000c1 425#define MSR_P6_PERFCTR1 0x000000c2 426#define MSR_P6_EVNTSEL0 0x00000186 427#define MSR_P6_EVNTSEL1 0x00000187 428 429#define MSR_KNC_PERFCTR0 0x00000020 430#define MSR_KNC_PERFCTR1 0x00000021 431#define MSR_KNC_EVNTSEL0 0x00000028 432#define MSR_KNC_EVNTSEL1 0x00000029 433 434/* Alternative perfctr range with full access. */ 435#define MSR_IA32_PMC0 0x000004c1 436 437/* Auto-reload via MSR instead of DS area */ 438#define MSR_RELOAD_PMC0 0x000014c1 439#define MSR_RELOAD_FIXED_CTR0 0x00001309 440 441/* 442 * AMD64 MSRs. Not complete. See the architecture manual for a more 443 * complete list. 444 */ 445#define MSR_AMD64_PATCH_LEVEL 0x0000008b 446#define MSR_AMD64_TSC_RATIO 0xc0000104 447#define MSR_AMD64_NB_CFG 0xc001001f 448#define MSR_AMD64_PATCH_LOADER 0xc0010020 449#define MSR_AMD_PERF_CTL 0xc0010062 450#define MSR_AMD_PERF_STATUS 0xc0010063 451#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 452#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 453#define MSR_AMD64_OSVW_STATUS 0xc0010141 454#define MSR_AMD_PPIN_CTL 0xc00102f0 455#define MSR_AMD_PPIN 0xc00102f1 456#define MSR_AMD64_CPUID_FN_1 0xc0011004 457#define MSR_AMD64_LS_CFG 0xc0011020 458#define MSR_AMD64_DC_CFG 0xc0011022 459#define MSR_AMD64_BU_CFG2 0xc001102a 460#define MSR_AMD64_IBSFETCHCTL 0xc0011030 461#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 462#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 463#define MSR_AMD64_IBSFETCH_REG_COUNT 3 464#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 465#define MSR_AMD64_IBSOPCTL 0xc0011033 466#define MSR_AMD64_IBSOPRIP 0xc0011034 467#define MSR_AMD64_IBSOPDATA 0xc0011035 468#define MSR_AMD64_IBSOPDATA2 0xc0011036 469#define MSR_AMD64_IBSOPDATA3 0xc0011037 470#define MSR_AMD64_IBSDCLINAD 0xc0011038 471#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 472#define MSR_AMD64_IBSOP_REG_COUNT 7 473#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 474#define MSR_AMD64_IBSCTL 0xc001103a 475#define MSR_AMD64_IBSBRTARGET 0xc001103b 476#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c 477#define MSR_AMD64_IBSOPDATA4 0xc001103d 478#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 479#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e 480#define MSR_AMD64_SEV_ES_GHCB 0xc0010130 481#define MSR_AMD64_SEV 0xc0010131 482#define MSR_AMD64_SEV_ENABLED_BIT 0 483#define MSR_AMD64_SEV_ES_ENABLED_BIT 1 484#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 485#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) 486 487#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 488 489/* Fam 17h MSRs */ 490#define MSR_F17H_IRPERF 0xc00000e9 491 492/* Fam 16h MSRs */ 493#define MSR_F16H_L2I_PERF_CTL 0xc0010230 494#define MSR_F16H_L2I_PERF_CTR 0xc0010231 495#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 496#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 497#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 498#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 499 500/* Fam 15h MSRs */ 501#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a 502#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b 503#define MSR_F15H_PERF_CTL 0xc0010200 504#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 505#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 506#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 507#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 508#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 509#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 510 511#define MSR_F15H_PERF_CTR 0xc0010201 512#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 513#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 514#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 515#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 516#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 517#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 518 519#define MSR_F15H_NB_PERF_CTL 0xc0010240 520#define MSR_F15H_NB_PERF_CTR 0xc0010241 521#define MSR_F15H_PTSC 0xc0010280 522#define MSR_F15H_IC_CFG 0xc0011021 523#define MSR_F15H_EX_CFG 0xc001102c 524 525/* Fam 10h MSRs */ 526#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 527#define FAM10H_MMIO_CONF_ENABLE (1<<0) 528#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 529#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 530#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 531#define FAM10H_MMIO_CONF_BASE_SHIFT 20 532#define MSR_FAM10H_NODE_ID 0xc001100c 533#define MSR_F10H_DECFG 0xc0011029 534#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 535#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 536 537/* K8 MSRs */ 538#define MSR_K8_TOP_MEM1 0xc001001a 539#define MSR_K8_TOP_MEM2 0xc001001d 540#define MSR_AMD64_SYSCFG 0xc0010010 541#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 542#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) 543#define MSR_K8_INT_PENDING_MSG 0xc0010055 544/* C1E active bits in int pending message */ 545#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 546#define MSR_K8_TSEG_ADDR 0xc0010112 547#define MSR_K8_TSEG_MASK 0xc0010113 548#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 549#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 550#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 551 552/* K7 MSRs */ 553#define MSR_K7_EVNTSEL0 0xc0010000 554#define MSR_K7_PERFCTR0 0xc0010004 555#define MSR_K7_EVNTSEL1 0xc0010001 556#define MSR_K7_PERFCTR1 0xc0010005 557#define MSR_K7_EVNTSEL2 0xc0010002 558#define MSR_K7_PERFCTR2 0xc0010006 559#define MSR_K7_EVNTSEL3 0xc0010003 560#define MSR_K7_PERFCTR3 0xc0010007 561#define MSR_K7_CLK_CTL 0xc001001b 562#define MSR_K7_HWCR 0xc0010015 563#define MSR_K7_HWCR_SMMLOCK_BIT 0 564#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 565#define MSR_K7_HWCR_IRPERF_EN_BIT 30 566#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) 567#define MSR_K7_FID_VID_CTL 0xc0010041 568#define MSR_K7_FID_VID_STATUS 0xc0010042 569 570/* K6 MSRs */ 571#define MSR_K6_WHCR 0xc0000082 572#define MSR_K6_UWCCR 0xc0000085 573#define MSR_K6_EPMR 0xc0000086 574#define MSR_K6_PSOR 0xc0000087 575#define MSR_K6_PFIR 0xc0000088 576 577/* Centaur-Hauls/IDT defined MSRs. */ 578#define MSR_IDT_FCR1 0x00000107 579#define MSR_IDT_FCR2 0x00000108 580#define MSR_IDT_FCR3 0x00000109 581#define MSR_IDT_FCR4 0x0000010a 582 583#define MSR_IDT_MCR0 0x00000110 584#define MSR_IDT_MCR1 0x00000111 585#define MSR_IDT_MCR2 0x00000112 586#define MSR_IDT_MCR3 0x00000113 587#define MSR_IDT_MCR4 0x00000114 588#define MSR_IDT_MCR5 0x00000115 589#define MSR_IDT_MCR6 0x00000116 590#define MSR_IDT_MCR7 0x00000117 591#define MSR_IDT_MCR_CTRL 0x00000120 592 593/* VIA Cyrix defined MSRs*/ 594#define MSR_VIA_FCR 0x00001107 595#define MSR_VIA_LONGHAUL 0x0000110a 596#define MSR_VIA_RNG 0x0000110b 597#define MSR_VIA_BCR2 0x00001147 598 599/* Transmeta defined MSRs */ 600#define MSR_TMTA_LONGRUN_CTRL 0x80868010 601#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 602#define MSR_TMTA_LRTI_READOUT 0x80868018 603#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 604 605/* Intel defined MSRs. */ 606#define MSR_IA32_P5_MC_ADDR 0x00000000 607#define MSR_IA32_P5_MC_TYPE 0x00000001 608#define MSR_IA32_TSC 0x00000010 609#define MSR_IA32_PLATFORM_ID 0x00000017 610#define MSR_IA32_EBL_CR_POWERON 0x0000002a 611#define MSR_EBC_FREQUENCY_ID 0x0000002c 612#define MSR_SMI_COUNT 0x00000034 613 614/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */ 615#define MSR_IA32_FEAT_CTL 0x0000003a 616#define FEAT_CTL_LOCKED BIT(0) 617#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1) 618#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2) 619#define FEAT_CTL_SGX_LC_ENABLED BIT(17) 620#define FEAT_CTL_SGX_ENABLED BIT(18) 621#define FEAT_CTL_LMCE_ENABLED BIT(20) 622 623#define MSR_IA32_TSC_ADJUST 0x0000003b 624#define MSR_IA32_BNDCFGS 0x00000d90 625 626#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 627 628#define MSR_IA32_XSS 0x00000da0 629 630#define MSR_IA32_APICBASE 0x0000001b 631#define MSR_IA32_APICBASE_BSP (1<<8) 632#define MSR_IA32_APICBASE_ENABLE (1<<11) 633#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 634 635#define MSR_IA32_UCODE_WRITE 0x00000079 636#define MSR_IA32_UCODE_REV 0x0000008b 637 638/* Intel SGX Launch Enclave Public Key Hash MSRs */ 639#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C 640#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D 641#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E 642#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F 643 644#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 645#define MSR_IA32_SMBASE 0x0000009e 646 647#define MSR_IA32_PERF_STATUS 0x00000198 648#define MSR_IA32_PERF_CTL 0x00000199 649#define INTEL_PERF_CTL_MASK 0xffff 650 651#define MSR_IA32_MPERF 0x000000e7 652#define MSR_IA32_APERF 0x000000e8 653 654#define MSR_IA32_THERM_CONTROL 0x0000019a 655#define MSR_IA32_THERM_INTERRUPT 0x0000019b 656 657#define THERM_INT_HIGH_ENABLE (1 << 0) 658#define THERM_INT_LOW_ENABLE (1 << 1) 659#define THERM_INT_PLN_ENABLE (1 << 24) 660 661#define MSR_IA32_THERM_STATUS 0x0000019c 662 663#define THERM_STATUS_PROCHOT (1 << 0) 664#define THERM_STATUS_POWER_LIMIT (1 << 10) 665 666#define MSR_THERM2_CTL 0x0000019d 667 668#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 669 670#define MSR_IA32_MISC_ENABLE 0x000001a0 671 672#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 673 674#define MSR_MISC_FEATURE_CONTROL 0x000001a4 675#define MSR_MISC_PWR_MGMT 0x000001aa 676 677#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 678#define ENERGY_PERF_BIAS_PERFORMANCE 0 679#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 680#define ENERGY_PERF_BIAS_NORMAL 6 681#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 682#define ENERGY_PERF_BIAS_POWERSAVE 15 683 684#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 685 686#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 687#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 688 689#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 690 691#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 692#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 693#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 694 695/* Thermal Thresholds Support */ 696#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 697#define THERM_SHIFT_THRESHOLD0 8 698#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 699#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 700#define THERM_SHIFT_THRESHOLD1 16 701#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 702#define THERM_STATUS_THRESHOLD0 (1 << 6) 703#define THERM_LOG_THRESHOLD0 (1 << 7) 704#define THERM_STATUS_THRESHOLD1 (1 << 8) 705#define THERM_LOG_THRESHOLD1 (1 << 9) 706 707/* MISC_ENABLE bits: architectural */ 708#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 709#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 710#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 711#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 712#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 713#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 714#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 715#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 716#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 717#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 718#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 719#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 720#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 721#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 722#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 723#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 724#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 725#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 726#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 727#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 728 729/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 730#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 731#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 732#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 733#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 734#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 735#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 736#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 737#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 738#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 739#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 740#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 741#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 742#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 743#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 744#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 745#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 746#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 747#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 748#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 749#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 750#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 751#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 752#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 753#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 754#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 755#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 756#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 757#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 758#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 759#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 760 761/* MISC_FEATURES_ENABLES non-architectural features */ 762#define MSR_MISC_FEATURES_ENABLES 0x00000140 763 764#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 765#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 766#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 767 768#define MSR_IA32_TSC_DEADLINE 0x000006E0 769 770 771#define MSR_TSX_FORCE_ABORT 0x0000010F 772 773#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 774#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) 775#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1 776#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT) 777#define MSR_TFA_SDV_ENABLE_RTM_BIT 2 778#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT) 779 780/* P4/Xeon+ specific */ 781#define MSR_IA32_MCG_EAX 0x00000180 782#define MSR_IA32_MCG_EBX 0x00000181 783#define MSR_IA32_MCG_ECX 0x00000182 784#define MSR_IA32_MCG_EDX 0x00000183 785#define MSR_IA32_MCG_ESI 0x00000184 786#define MSR_IA32_MCG_EDI 0x00000185 787#define MSR_IA32_MCG_EBP 0x00000186 788#define MSR_IA32_MCG_ESP 0x00000187 789#define MSR_IA32_MCG_EFLAGS 0x00000188 790#define MSR_IA32_MCG_EIP 0x00000189 791#define MSR_IA32_MCG_RESERVED 0x0000018a 792 793/* Pentium IV performance counter MSRs */ 794#define MSR_P4_BPU_PERFCTR0 0x00000300 795#define MSR_P4_BPU_PERFCTR1 0x00000301 796#define MSR_P4_BPU_PERFCTR2 0x00000302 797#define MSR_P4_BPU_PERFCTR3 0x00000303 798#define MSR_P4_MS_PERFCTR0 0x00000304 799#define MSR_P4_MS_PERFCTR1 0x00000305 800#define MSR_P4_MS_PERFCTR2 0x00000306 801#define MSR_P4_MS_PERFCTR3 0x00000307 802#define MSR_P4_FLAME_PERFCTR0 0x00000308 803#define MSR_P4_FLAME_PERFCTR1 0x00000309 804#define MSR_P4_FLAME_PERFCTR2 0x0000030a 805#define MSR_P4_FLAME_PERFCTR3 0x0000030b 806#define MSR_P4_IQ_PERFCTR0 0x0000030c 807#define MSR_P4_IQ_PERFCTR1 0x0000030d 808#define MSR_P4_IQ_PERFCTR2 0x0000030e 809#define MSR_P4_IQ_PERFCTR3 0x0000030f 810#define MSR_P4_IQ_PERFCTR4 0x00000310 811#define MSR_P4_IQ_PERFCTR5 0x00000311 812#define MSR_P4_BPU_CCCR0 0x00000360 813#define MSR_P4_BPU_CCCR1 0x00000361 814#define MSR_P4_BPU_CCCR2 0x00000362 815#define MSR_P4_BPU_CCCR3 0x00000363 816#define MSR_P4_MS_CCCR0 0x00000364 817#define MSR_P4_MS_CCCR1 0x00000365 818#define MSR_P4_MS_CCCR2 0x00000366 819#define MSR_P4_MS_CCCR3 0x00000367 820#define MSR_P4_FLAME_CCCR0 0x00000368 821#define MSR_P4_FLAME_CCCR1 0x00000369 822#define MSR_P4_FLAME_CCCR2 0x0000036a 823#define MSR_P4_FLAME_CCCR3 0x0000036b 824#define MSR_P4_IQ_CCCR0 0x0000036c 825#define MSR_P4_IQ_CCCR1 0x0000036d 826#define MSR_P4_IQ_CCCR2 0x0000036e 827#define MSR_P4_IQ_CCCR3 0x0000036f 828#define MSR_P4_IQ_CCCR4 0x00000370 829#define MSR_P4_IQ_CCCR5 0x00000371 830#define MSR_P4_ALF_ESCR0 0x000003ca 831#define MSR_P4_ALF_ESCR1 0x000003cb 832#define MSR_P4_BPU_ESCR0 0x000003b2 833#define MSR_P4_BPU_ESCR1 0x000003b3 834#define MSR_P4_BSU_ESCR0 0x000003a0 835#define MSR_P4_BSU_ESCR1 0x000003a1 836#define MSR_P4_CRU_ESCR0 0x000003b8 837#define MSR_P4_CRU_ESCR1 0x000003b9 838#define MSR_P4_CRU_ESCR2 0x000003cc 839#define MSR_P4_CRU_ESCR3 0x000003cd 840#define MSR_P4_CRU_ESCR4 0x000003e0 841#define MSR_P4_CRU_ESCR5 0x000003e1 842#define MSR_P4_DAC_ESCR0 0x000003a8 843#define MSR_P4_DAC_ESCR1 0x000003a9 844#define MSR_P4_FIRM_ESCR0 0x000003a4 845#define MSR_P4_FIRM_ESCR1 0x000003a5 846#define MSR_P4_FLAME_ESCR0 0x000003a6 847#define MSR_P4_FLAME_ESCR1 0x000003a7 848#define MSR_P4_FSB_ESCR0 0x000003a2 849#define MSR_P4_FSB_ESCR1 0x000003a3 850#define MSR_P4_IQ_ESCR0 0x000003ba 851#define MSR_P4_IQ_ESCR1 0x000003bb 852#define MSR_P4_IS_ESCR0 0x000003b4 853#define MSR_P4_IS_ESCR1 0x000003b5 854#define MSR_P4_ITLB_ESCR0 0x000003b6 855#define MSR_P4_ITLB_ESCR1 0x000003b7 856#define MSR_P4_IX_ESCR0 0x000003c8 857#define MSR_P4_IX_ESCR1 0x000003c9 858#define MSR_P4_MOB_ESCR0 0x000003aa 859#define MSR_P4_MOB_ESCR1 0x000003ab 860#define MSR_P4_MS_ESCR0 0x000003c0 861#define MSR_P4_MS_ESCR1 0x000003c1 862#define MSR_P4_PMH_ESCR0 0x000003ac 863#define MSR_P4_PMH_ESCR1 0x000003ad 864#define MSR_P4_RAT_ESCR0 0x000003bc 865#define MSR_P4_RAT_ESCR1 0x000003bd 866#define MSR_P4_SAAT_ESCR0 0x000003ae 867#define MSR_P4_SAAT_ESCR1 0x000003af 868#define MSR_P4_SSU_ESCR0 0x000003be 869#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 870 871#define MSR_P4_TBPU_ESCR0 0x000003c2 872#define MSR_P4_TBPU_ESCR1 0x000003c3 873#define MSR_P4_TC_ESCR0 0x000003c4 874#define MSR_P4_TC_ESCR1 0x000003c5 875#define MSR_P4_U2L_ESCR0 0x000003b0 876#define MSR_P4_U2L_ESCR1 0x000003b1 877 878#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 879 880/* Intel Core-based CPU performance counters */ 881#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 882#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 883#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 884#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c 885#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 886#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 887#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 888#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 889 890#define MSR_PERF_METRICS 0x00000329 891 892/* PERF_GLOBAL_OVF_CTL bits */ 893#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55 894#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT) 895#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62 896#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT) 897#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63 898#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT) 899 900/* Geode defined MSRs */ 901#define MSR_GEODE_BUSCONT_CONF0 0x00001900 902 903/* Intel VT MSRs */ 904#define MSR_IA32_VMX_BASIC 0x00000480 905#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 906#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 907#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 908#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 909#define MSR_IA32_VMX_MISC 0x00000485 910#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 911#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 912#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 913#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 914#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 915#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 916#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 917#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 918#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 919#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 920#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 921#define MSR_IA32_VMX_VMFUNC 0x00000491 922 923/* VMX_BASIC bits and bitmasks */ 924#define VMX_BASIC_VMCS_SIZE_SHIFT 32 925#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 926#define VMX_BASIC_64 0x0001000000000000LLU 927#define VMX_BASIC_MEM_TYPE_SHIFT 50 928#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 929#define VMX_BASIC_MEM_TYPE_WB 6LLU 930#define VMX_BASIC_INOUT 0x0040000000000000LLU 931 932/* MSR_IA32_VMX_MISC bits */ 933#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) 934#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 935#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 936/* AMD-V MSRs */ 937 938#define MSR_VM_CR 0xc0010114 939#define MSR_VM_IGNNE 0xc0010115 940#define MSR_VM_HSAVE_PA 0xc0010117 941 942#endif /* _ASM_X86_MSR_INDEX_H */ 943