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8#ifndef SELFTEST_KVM_SVM_H
9#define SELFTEST_KVM_SVM_H
10
11enum {
12 INTERCEPT_INTR,
13 INTERCEPT_NMI,
14 INTERCEPT_SMI,
15 INTERCEPT_INIT,
16 INTERCEPT_VINTR,
17 INTERCEPT_SELECTIVE_CR0,
18 INTERCEPT_STORE_IDTR,
19 INTERCEPT_STORE_GDTR,
20 INTERCEPT_STORE_LDTR,
21 INTERCEPT_STORE_TR,
22 INTERCEPT_LOAD_IDTR,
23 INTERCEPT_LOAD_GDTR,
24 INTERCEPT_LOAD_LDTR,
25 INTERCEPT_LOAD_TR,
26 INTERCEPT_RDTSC,
27 INTERCEPT_RDPMC,
28 INTERCEPT_PUSHF,
29 INTERCEPT_POPF,
30 INTERCEPT_CPUID,
31 INTERCEPT_RSM,
32 INTERCEPT_IRET,
33 INTERCEPT_INTn,
34 INTERCEPT_INVD,
35 INTERCEPT_PAUSE,
36 INTERCEPT_HLT,
37 INTERCEPT_INVLPG,
38 INTERCEPT_INVLPGA,
39 INTERCEPT_IOIO_PROT,
40 INTERCEPT_MSR_PROT,
41 INTERCEPT_TASK_SWITCH,
42 INTERCEPT_FERR_FREEZE,
43 INTERCEPT_SHUTDOWN,
44 INTERCEPT_VMRUN,
45 INTERCEPT_VMMCALL,
46 INTERCEPT_VMLOAD,
47 INTERCEPT_VMSAVE,
48 INTERCEPT_STGI,
49 INTERCEPT_CLGI,
50 INTERCEPT_SKINIT,
51 INTERCEPT_RDTSCP,
52 INTERCEPT_ICEBP,
53 INTERCEPT_WBINVD,
54 INTERCEPT_MONITOR,
55 INTERCEPT_MWAIT,
56 INTERCEPT_MWAIT_COND,
57 INTERCEPT_XSETBV,
58 INTERCEPT_RDPRU,
59};
60
61
62struct __attribute__ ((__packed__)) vmcb_control_area {
63 u32 intercept_cr;
64 u32 intercept_dr;
65 u32 intercept_exceptions;
66 u64 intercept;
67 u8 reserved_1[40];
68 u16 pause_filter_thresh;
69 u16 pause_filter_count;
70 u64 iopm_base_pa;
71 u64 msrpm_base_pa;
72 u64 tsc_offset;
73 u32 asid;
74 u8 tlb_ctl;
75 u8 reserved_2[3];
76 u32 int_ctl;
77 u32 int_vector;
78 u32 int_state;
79 u8 reserved_3[4];
80 u32 exit_code;
81 u32 exit_code_hi;
82 u64 exit_info_1;
83 u64 exit_info_2;
84 u32 exit_int_info;
85 u32 exit_int_info_err;
86 u64 nested_ctl;
87 u64 avic_vapic_bar;
88 u8 reserved_4[8];
89 u32 event_inj;
90 u32 event_inj_err;
91 u64 nested_cr3;
92 u64 virt_ext;
93 u32 clean;
94 u32 reserved_5;
95 u64 next_rip;
96 u8 insn_len;
97 u8 insn_bytes[15];
98 u64 avic_backing_page;
99 u8 reserved_6[8];
100 u64 avic_logical_id;
101 u64 avic_physical_id;
102 u8 reserved_7[768];
103};
104
105
106#define TLB_CONTROL_DO_NOTHING 0
107#define TLB_CONTROL_FLUSH_ALL_ASID 1
108#define TLB_CONTROL_FLUSH_ASID 3
109#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
110
111#define V_TPR_MASK 0x0f
112
113#define V_IRQ_SHIFT 8
114#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
115
116#define V_GIF_SHIFT 9
117#define V_GIF_MASK (1 << V_GIF_SHIFT)
118
119#define V_INTR_PRIO_SHIFT 16
120#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
121
122#define V_IGN_TPR_SHIFT 20
123#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
124
125#define V_INTR_MASKING_SHIFT 24
126#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
127
128#define V_GIF_ENABLE_SHIFT 25
129#define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
130
131#define AVIC_ENABLE_SHIFT 31
132#define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
133
134#define LBR_CTL_ENABLE_MASK BIT_ULL(0)
135#define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
136
137#define SVM_INTERRUPT_SHADOW_MASK 1
138
139#define SVM_IOIO_STR_SHIFT 2
140#define SVM_IOIO_REP_SHIFT 3
141#define SVM_IOIO_SIZE_SHIFT 4
142#define SVM_IOIO_ASIZE_SHIFT 7
143
144#define SVM_IOIO_TYPE_MASK 1
145#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
146#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
147#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
148#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
149
150#define SVM_VM_CR_VALID_MASK 0x001fULL
151#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
152#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
153
154#define SVM_NESTED_CTL_NP_ENABLE BIT(0)
155#define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
156
157struct __attribute__ ((__packed__)) vmcb_seg {
158 u16 selector;
159 u16 attrib;
160 u32 limit;
161 u64 base;
162};
163
164struct __attribute__ ((__packed__)) vmcb_save_area {
165 struct vmcb_seg es;
166 struct vmcb_seg cs;
167 struct vmcb_seg ss;
168 struct vmcb_seg ds;
169 struct vmcb_seg fs;
170 struct vmcb_seg gs;
171 struct vmcb_seg gdtr;
172 struct vmcb_seg ldtr;
173 struct vmcb_seg idtr;
174 struct vmcb_seg tr;
175 u8 reserved_1[43];
176 u8 cpl;
177 u8 reserved_2[4];
178 u64 efer;
179 u8 reserved_3[112];
180 u64 cr4;
181 u64 cr3;
182 u64 cr0;
183 u64 dr7;
184 u64 dr6;
185 u64 rflags;
186 u64 rip;
187 u8 reserved_4[88];
188 u64 rsp;
189 u8 reserved_5[24];
190 u64 rax;
191 u64 star;
192 u64 lstar;
193 u64 cstar;
194 u64 sfmask;
195 u64 kernel_gs_base;
196 u64 sysenter_cs;
197 u64 sysenter_esp;
198 u64 sysenter_eip;
199 u64 cr2;
200 u8 reserved_6[32];
201 u64 g_pat;
202 u64 dbgctl;
203 u64 br_from;
204 u64 br_to;
205 u64 last_excp_from;
206 u64 last_excp_to;
207};
208
209struct __attribute__ ((__packed__)) vmcb {
210 struct vmcb_control_area control;
211 struct vmcb_save_area save;
212};
213
214#define SVM_CPUID_FUNC 0x8000000a
215
216#define SVM_VM_CR_SVM_DISABLE 4
217
218#define SVM_SELECTOR_S_SHIFT 4
219#define SVM_SELECTOR_DPL_SHIFT 5
220#define SVM_SELECTOR_P_SHIFT 7
221#define SVM_SELECTOR_AVL_SHIFT 8
222#define SVM_SELECTOR_L_SHIFT 9
223#define SVM_SELECTOR_DB_SHIFT 10
224#define SVM_SELECTOR_G_SHIFT 11
225
226#define SVM_SELECTOR_TYPE_MASK (0xf)
227#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
228#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
229#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
230#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
231#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
232#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
233#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
234
235#define SVM_SELECTOR_WRITE_MASK (1 << 1)
236#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
237#define SVM_SELECTOR_CODE_MASK (1 << 3)
238
239#define INTERCEPT_CR0_READ 0
240#define INTERCEPT_CR3_READ 3
241#define INTERCEPT_CR4_READ 4
242#define INTERCEPT_CR8_READ 8
243#define INTERCEPT_CR0_WRITE (16 + 0)
244#define INTERCEPT_CR3_WRITE (16 + 3)
245#define INTERCEPT_CR4_WRITE (16 + 4)
246#define INTERCEPT_CR8_WRITE (16 + 8)
247
248#define INTERCEPT_DR0_READ 0
249#define INTERCEPT_DR1_READ 1
250#define INTERCEPT_DR2_READ 2
251#define INTERCEPT_DR3_READ 3
252#define INTERCEPT_DR4_READ 4
253#define INTERCEPT_DR5_READ 5
254#define INTERCEPT_DR6_READ 6
255#define INTERCEPT_DR7_READ 7
256#define INTERCEPT_DR0_WRITE (16 + 0)
257#define INTERCEPT_DR1_WRITE (16 + 1)
258#define INTERCEPT_DR2_WRITE (16 + 2)
259#define INTERCEPT_DR3_WRITE (16 + 3)
260#define INTERCEPT_DR4_WRITE (16 + 4)
261#define INTERCEPT_DR5_WRITE (16 + 5)
262#define INTERCEPT_DR6_WRITE (16 + 6)
263#define INTERCEPT_DR7_WRITE (16 + 7)
264
265#define SVM_EVTINJ_VEC_MASK 0xff
266
267#define SVM_EVTINJ_TYPE_SHIFT 8
268#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
269
270#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
271#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
272#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
273#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
274
275#define SVM_EVTINJ_VALID (1 << 31)
276#define SVM_EVTINJ_VALID_ERR (1 << 11)
277
278#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
279#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
280
281#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
282#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
283#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
284#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
285
286#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
287#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
288
289#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
290#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
291#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
292
293#define SVM_EXITINFO_REG_MASK 0x0F
294
295#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
296
297#endif
298
