LXR linux/tools/testing/selftests/sgx/test_encl

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright(c) 2016-20 Intel Corporation.
   4 */
   5
   6        .macro ENCLU
   7        .byte 0x0f, 0x01, 0xd7
   8        .endm
   9
  10        .section ".tcs", "aw"
  11        .balign 4096
  12
  13        .fill   1, 8, 0                 # STATE (set by CPU)
  14        .fill   1, 8, 0                 # FLAGS
  15        .quad   encl_ssa                # OSSA
  16        .fill   1, 4, 0                 # CSSA (set by CPU)
  17        .fill   1, 4, 1                 # NSSA
  18        .quad   encl_entry              # OENTRY
  19        .fill   1, 8, 0                 # AEP (set by EENTER and ERESUME)
  20        .fill   1, 8, 0                 # OFSBASE
  21        .fill   1, 8, 0                 # OGSBASE
  22        .fill   1, 4, 0xFFFFFFFF        # FSLIMIT
  23        .fill   1, 4, 0xFFFFFFFF        # GSLIMIT
  24        .fill   4024, 1, 0              # Reserved
  25
  26        # Identical to the previous TCS.
  27        .fill   1, 8, 0                 # STATE (set by CPU)
  28        .fill   1, 8, 0                 # FLAGS
  29        .quad   encl_ssa                # OSSA
  30        .fill   1, 4, 0                 # CSSA (set by CPU)
  31        .fill   1, 4, 1                 # NSSA
  32        .quad   encl_entry              # OENTRY
  33        .fill   1, 8, 0                 # AEP (set by EENTER and ERESUME)
  34        .fill   1, 8, 0                 # OFSBASE
  35        .fill   1, 8, 0                 # OGSBASE
  36        .fill   1, 4, 0xFFFFFFFF        # FSLIMIT
  37        .fill   1, 4, 0xFFFFFFFF        # GSLIMIT
  38        .fill   4024, 1, 0              # Reserved
  39
  40        .text
  41
  42encl_entry:
  43        # RBX contains the base address for TCS, which is also the first address
  44        # inside the enclave. By adding the value of le_stack_end to it, we get
  45        # the absolute address for the stack.
  46        lea     (encl_stack)(%rbx), %rax
  47        xchg    %rsp, %rax
  48        push    %rax
  49
  50        push    %rcx # push the address after EENTER
  51        push    %rbx # push the enclave base address
  52
  53        call    encl_body
  54
  55        pop     %rbx # pop the enclave base address
  56
  57        /* Clear volatile GPRs, except RAX (EEXIT function). */
  58        xor     %rcx, %rcx
  59        xor     %rdx, %rdx
  60        xor     %rdi, %rdi
  61        xor     %rsi, %rsi
  62        xor     %r8, %r8
  63        xor     %r9, %r9
  64        xor     %r10, %r10
  65        xor     %r11, %r11
  66
  67        # Reset status flags.
  68        add     %rdx, %rdx # OF = SF = AF = CF = 0; ZF = PF = 1
  69
  70        # Prepare EEXIT target by popping the address of the instruction after
  71        # EENTER to RBX.
  72        pop     %rbx
  73
  74        # Restore the caller stack.
  75        pop     %rax
  76        mov     %rax, %rsp
  77
  78        # EEXIT
  79        mov     $4, %rax
  80        enclu
  81
  82        .section ".data", "aw"
  83
  84encl_ssa:
  85        .space 4096
  86
  87        .balign 4096
  88        .space 8192
  89encl_stack:
  90