1#include "hw/hw.h"
2#include "hw/boards.h"
3
4void register_machines(void)
5{
6 qemu_register_machine(&integratorcp_machine);
7 qemu_register_machine(&versatilepb_machine);
8 qemu_register_machine(&versatileab_machine);
9 qemu_register_machine(&realview_machine);
10 qemu_register_machine(&akitapda_machine);
11 qemu_register_machine(&spitzpda_machine);
12 qemu_register_machine(&borzoipda_machine);
13 qemu_register_machine(&terrierpda_machine);
14 qemu_register_machine(&sx1_machine_v1);
15 qemu_register_machine(&sx1_machine_v2);
16 qemu_register_machine(&palmte_machine);
17 qemu_register_machine(&n800_machine);
18 qemu_register_machine(&n810_machine);
19 qemu_register_machine(&lm3s811evb_machine);
20 qemu_register_machine(&lm3s6965evb_machine);
21 qemu_register_machine(&connex_machine);
22 qemu_register_machine(&verdex_machine);
23 qemu_register_machine(&mainstone2_machine);
24 qemu_register_machine(&musicpal_machine);
25 qemu_register_machine(&tosapda_machine);
26}
27
28void cpu_save(QEMUFile *f, void *opaque)
29{
30 int i;
31 CPUARMState *env = (CPUARMState *)opaque;
32
33 for (i = 0; i < 16; i++) {
34 qemu_put_be32(f, env->regs[i]);
35 }
36 qemu_put_be32(f, cpsr_read(env));
37 qemu_put_be32(f, env->spsr);
38 for (i = 0; i < 6; i++) {
39 qemu_put_be32(f, env->banked_spsr[i]);
40 qemu_put_be32(f, env->banked_r13[i]);
41 qemu_put_be32(f, env->banked_r14[i]);
42 }
43 for (i = 0; i < 5; i++) {
44 qemu_put_be32(f, env->usr_regs[i]);
45 qemu_put_be32(f, env->fiq_regs[i]);
46 }
47 qemu_put_be32(f, env->cp15.c0_cpuid);
48 qemu_put_be32(f, env->cp15.c0_cachetype);
49 qemu_put_be32(f, env->cp15.c1_sys);
50 qemu_put_be32(f, env->cp15.c1_coproc);
51 qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
52 qemu_put_be32(f, env->cp15.c2_base0);
53 qemu_put_be32(f, env->cp15.c2_base1);
54 qemu_put_be32(f, env->cp15.c2_mask);
55 qemu_put_be32(f, env->cp15.c2_data);
56 qemu_put_be32(f, env->cp15.c2_insn);
57 qemu_put_be32(f, env->cp15.c3);
58 qemu_put_be32(f, env->cp15.c5_insn);
59 qemu_put_be32(f, env->cp15.c5_data);
60 for (i = 0; i < 8; i++) {
61 qemu_put_be32(f, env->cp15.c6_region[i]);
62 }
63 qemu_put_be32(f, env->cp15.c6_insn);
64 qemu_put_be32(f, env->cp15.c6_data);
65 qemu_put_be32(f, env->cp15.c9_insn);
66 qemu_put_be32(f, env->cp15.c9_data);
67 qemu_put_be32(f, env->cp15.c13_fcse);
68 qemu_put_be32(f, env->cp15.c13_context);
69 qemu_put_be32(f, env->cp15.c13_tls1);
70 qemu_put_be32(f, env->cp15.c13_tls2);
71 qemu_put_be32(f, env->cp15.c13_tls3);
72 qemu_put_be32(f, env->cp15.c15_cpar);
73
74 qemu_put_be32(f, env->features);
75
76 if (arm_feature(env, ARM_FEATURE_VFP)) {
77 for (i = 0; i < 16; i++) {
78 CPU_DoubleU u;
79 u.d = env->vfp.regs[i];
80 qemu_put_be32(f, u.l.upper);
81 qemu_put_be32(f, u.l.lower);
82 }
83 for (i = 0; i < 16; i++) {
84 qemu_put_be32(f, env->vfp.xregs[i]);
85 }
86
87
88 qemu_put_be32(f, env->vfp.vec_len);
89 qemu_put_be32(f, env->vfp.vec_stride);
90
91 if (arm_feature(env, ARM_FEATURE_VFP3)) {
92 for (i = 16; i < 32; i++) {
93 CPU_DoubleU u;
94 u.d = env->vfp.regs[i];
95 qemu_put_be32(f, u.l.upper);
96 qemu_put_be32(f, u.l.lower);
97 }
98 }
99 }
100
101 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
102 for (i = 0; i < 16; i++) {
103 qemu_put_be64(f, env->iwmmxt.regs[i]);
104 }
105 for (i = 0; i < 16; i++) {
106 qemu_put_be32(f, env->iwmmxt.cregs[i]);
107 }
108 }
109
110 if (arm_feature(env, ARM_FEATURE_M)) {
111 qemu_put_be32(f, env->v7m.other_sp);
112 qemu_put_be32(f, env->v7m.vecbase);
113 qemu_put_be32(f, env->v7m.basepri);
114 qemu_put_be32(f, env->v7m.control);
115 qemu_put_be32(f, env->v7m.current_sp);
116 qemu_put_be32(f, env->v7m.exception);
117 }
118}
119
120int cpu_load(QEMUFile *f, void *opaque, int version_id)
121{
122 CPUARMState *env = (CPUARMState *)opaque;
123 int i;
124
125 if (version_id != CPU_SAVE_VERSION)
126 return -EINVAL;
127
128 for (i = 0; i < 16; i++) {
129 env->regs[i] = qemu_get_be32(f);
130 }
131 cpsr_write(env, qemu_get_be32(f), 0xffffffff);
132 env->spsr = qemu_get_be32(f);
133 for (i = 0; i < 6; i++) {
134 env->banked_spsr[i] = qemu_get_be32(f);
135 env->banked_r13[i] = qemu_get_be32(f);
136 env->banked_r14[i] = qemu_get_be32(f);
137 }
138 for (i = 0; i < 5; i++) {
139 env->usr_regs[i] = qemu_get_be32(f);
140 env->fiq_regs[i] = qemu_get_be32(f);
141 }
142 env->cp15.c0_cpuid = qemu_get_be32(f);
143 env->cp15.c0_cachetype = qemu_get_be32(f);
144 env->cp15.c1_sys = qemu_get_be32(f);
145 env->cp15.c1_coproc = qemu_get_be32(f);
146 env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
147 env->cp15.c2_base0 = qemu_get_be32(f);
148 env->cp15.c2_base1 = qemu_get_be32(f);
149 env->cp15.c2_mask = qemu_get_be32(f);
150 env->cp15.c2_data = qemu_get_be32(f);
151 env->cp15.c2_insn = qemu_get_be32(f);
152 env->cp15.c3 = qemu_get_be32(f);
153 env->cp15.c5_insn = qemu_get_be32(f);
154 env->cp15.c5_data = qemu_get_be32(f);
155 for (i = 0; i < 8; i++) {
156 env->cp15.c6_region[i] = qemu_get_be32(f);
157 }
158 env->cp15.c6_insn = qemu_get_be32(f);
159 env->cp15.c6_data = qemu_get_be32(f);
160 env->cp15.c9_insn = qemu_get_be32(f);
161 env->cp15.c9_data = qemu_get_be32(f);
162 env->cp15.c13_fcse = qemu_get_be32(f);
163 env->cp15.c13_context = qemu_get_be32(f);
164 env->cp15.c13_tls1 = qemu_get_be32(f);
165 env->cp15.c13_tls2 = qemu_get_be32(f);
166 env->cp15.c13_tls3 = qemu_get_be32(f);
167 env->cp15.c15_cpar = qemu_get_be32(f);
168
169 env->features = qemu_get_be32(f);
170
171 if (arm_feature(env, ARM_FEATURE_VFP)) {
172 for (i = 0; i < 16; i++) {
173 CPU_DoubleU u;
174 u.l.upper = qemu_get_be32(f);
175 u.l.lower = qemu_get_be32(f);
176 env->vfp.regs[i] = u.d;
177 }
178 for (i = 0; i < 16; i++) {
179 env->vfp.xregs[i] = qemu_get_be32(f);
180 }
181
182
183 env->vfp.vec_len = qemu_get_be32(f);
184 env->vfp.vec_stride = qemu_get_be32(f);
185
186 if (arm_feature(env, ARM_FEATURE_VFP3)) {
187 for (i = 0; i < 16; i++) {
188 CPU_DoubleU u;
189 u.l.upper = qemu_get_be32(f);
190 u.l.lower = qemu_get_be32(f);
191 env->vfp.regs[i] = u.d;
192 }
193 }
194 }
195
196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
197 for (i = 0; i < 16; i++) {
198 env->iwmmxt.regs[i] = qemu_get_be64(f);
199 }
200 for (i = 0; i < 16; i++) {
201 env->iwmmxt.cregs[i] = qemu_get_be32(f);
202 }
203 }
204
205 if (arm_feature(env, ARM_FEATURE_M)) {
206 env->v7m.other_sp = qemu_get_be32(f);
207 env->v7m.vecbase = qemu_get_be32(f);
208 env->v7m.basepri = qemu_get_be32(f);
209 env->v7m.control = qemu_get_be32(f);
210 env->v7m.current_sp = qemu_get_be32(f);
211 env->v7m.exception = qemu_get_be32(f);
212 }
213
214 return 0;
215}
216
