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10#include "hw.h"
11#include "pxa.h"
12
13#define PXA2XX_GPIO_BANKS 4
14
15struct PXA2xxGPIOInfo {
16 qemu_irq *pic;
17 int lines;
18 CPUState *cpu_env;
19 qemu_irq *in;
20
21
22 uint32_t ilevel[PXA2XX_GPIO_BANKS];
23 uint32_t olevel[PXA2XX_GPIO_BANKS];
24 uint32_t dir[PXA2XX_GPIO_BANKS];
25 uint32_t rising[PXA2XX_GPIO_BANKS];
26 uint32_t falling[PXA2XX_GPIO_BANKS];
27 uint32_t status[PXA2XX_GPIO_BANKS];
28 uint32_t gpsr[PXA2XX_GPIO_BANKS];
29 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
30
31 uint32_t prev_level[PXA2XX_GPIO_BANKS];
32 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
33 qemu_irq read_notify;
34};
35
36static struct {
37 enum {
38 GPIO_NONE,
39 GPLR,
40 GPSR,
41 GPCR,
42 GPDR,
43 GRER,
44 GFER,
45 GEDR,
46 GAFR_L,
47 GAFR_U,
48 } reg;
49 int bank;
50} pxa2xx_gpio_regs[0x200] = {
51 [0 ... 0x1ff] = { GPIO_NONE, 0 },
52#define PXA2XX_REG(reg, a0, a1, a2, a3) \
53 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
54
55 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
56 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
57 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
58 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
59 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
60 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
61 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
62 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
63 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
64};
65
66static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
67{
68 if (s->status[0] & (1 << 0))
69 qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
70 else
71 qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
72
73 if (s->status[0] & (1 << 1))
74 qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
75 else
76 qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
77
78 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
79 qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
80 else
81 qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
82}
83
84
85static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
86 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
87};
88
89static void pxa2xx_gpio_set(void *opaque, int line, int level)
90{
91 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
92 int bank;
93 uint32_t mask;
94
95 if (line >= s->lines) {
96 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
97 return;
98 }
99
100 bank = line >> 5;
101 mask = 1 << (line & 31);
102
103 if (level) {
104 s->status[bank] |= s->rising[bank] & mask &
105 ~s->ilevel[bank] & ~s->dir[bank];
106 s->ilevel[bank] |= mask;
107 } else {
108 s->status[bank] |= s->falling[bank] & mask &
109 s->ilevel[bank] & ~s->dir[bank];
110 s->ilevel[bank] &= ~mask;
111 }
112
113 if (s->status[bank] & mask)
114 pxa2xx_gpio_irq_update(s);
115
116
117 if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
118 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
119}
120
121static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
122 uint32_t level, diff;
123 int i, bit, line;
124 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
125 level = s->olevel[i] & s->dir[i];
126
127 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
128 bit = ffs(diff) - 1;
129 line = bit + 32 * i;
130 qemu_set_irq(s->handler[line], (level >> bit) & 1);
131 }
132
133 s->prev_level[i] = level;
134 }
135}
136
137static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
138{
139 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
140 uint32_t ret;
141 int bank;
142 if (offset >= 0x200)
143 return 0;
144
145 bank = pxa2xx_gpio_regs[offset].bank;
146 switch (pxa2xx_gpio_regs[offset].reg) {
147 case GPDR:
148 return s->dir[bank];
149
150 case GPSR:
151 printf("%s: Read from a write-only register " REG_FMT "\n",
152 __FUNCTION__, offset);
153 return s->gpsr[bank];
154
155 case GPCR:
156 printf("%s: Read from a write-only register " REG_FMT "\n",
157 __FUNCTION__, offset);
158 return 31337;
159
160 case GRER:
161 return s->rising[bank];
162
163 case GFER:
164 return s->falling[bank];
165
166 case GAFR_L:
167 return s->gafr[bank * 2];
168
169 case GAFR_U:
170 return s->gafr[bank * 2 + 1];
171
172 case GPLR:
173 ret = (s->olevel[bank] & s->dir[bank]) |
174 (s->ilevel[bank] & ~s->dir[bank]);
175 qemu_irq_raise(s->read_notify);
176 return ret;
177
178 case GEDR:
179 return s->status[bank];
180
181 default:
182 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
183 }
184
185 return 0;
186}
187
188static void pxa2xx_gpio_write(void *opaque,
189 target_phys_addr_t offset, uint32_t value)
190{
191 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
192 int bank;
193 if (offset >= 0x200)
194 return;
195
196 bank = pxa2xx_gpio_regs[offset].bank;
197 switch (pxa2xx_gpio_regs[offset].reg) {
198 case GPDR:
199 s->dir[bank] = value;
200 pxa2xx_gpio_handler_update(s);
201 break;
202
203 case GPSR:
204 s->olevel[bank] |= value;
205 pxa2xx_gpio_handler_update(s);
206 s->gpsr[bank] = value;
207 break;
208
209 case GPCR:
210 s->olevel[bank] &= ~value;
211 pxa2xx_gpio_handler_update(s);
212 break;
213
214 case GRER:
215 s->rising[bank] = value;
216 break;
217
218 case GFER:
219 s->falling[bank] = value;
220 break;
221
222 case GAFR_L:
223 s->gafr[bank * 2] = value;
224 break;
225
226 case GAFR_U:
227 s->gafr[bank * 2 + 1] = value;
228 break;
229
230 case GEDR:
231 s->status[bank] &= ~value;
232 pxa2xx_gpio_irq_update(s);
233 break;
234
235 default:
236 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
237 }
238}
239
240static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
241 pxa2xx_gpio_read,
242 pxa2xx_gpio_read,
243 pxa2xx_gpio_read
244};
245
246static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
247 pxa2xx_gpio_write,
248 pxa2xx_gpio_write,
249 pxa2xx_gpio_write
250};
251
252static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
253{
254 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
255 int i;
256
257 qemu_put_be32(f, s->lines);
258
259 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
260 qemu_put_be32s(f, &s->ilevel[i]);
261 qemu_put_be32s(f, &s->olevel[i]);
262 qemu_put_be32s(f, &s->dir[i]);
263 qemu_put_be32s(f, &s->rising[i]);
264 qemu_put_be32s(f, &s->falling[i]);
265 qemu_put_be32s(f, &s->status[i]);
266 qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
267 qemu_put_be32s(f, &s->gafr[i * 2 + 1]);
268
269 qemu_put_be32s(f, &s->prev_level[i]);
270 }
271}
272
273static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
274{
275 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
276 int i;
277
278 if (qemu_get_be32(f) != s->lines)
279 return -EINVAL;
280
281 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
282 qemu_get_be32s(f, &s->ilevel[i]);
283 qemu_get_be32s(f, &s->olevel[i]);
284 qemu_get_be32s(f, &s->dir[i]);
285 qemu_get_be32s(f, &s->rising[i]);
286 qemu_get_be32s(f, &s->falling[i]);
287 qemu_get_be32s(f, &s->status[i]);
288 qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
289 qemu_get_be32s(f, &s->gafr[i * 2 + 1]);
290
291 qemu_get_be32s(f, &s->prev_level[i]);
292 }
293
294 return 0;
295}
296
297PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
298 CPUState *env, qemu_irq *pic, int lines)
299{
300 int iomemtype;
301 PXA2xxGPIOInfo *s;
302
303 s = (PXA2xxGPIOInfo *)
304 qemu_mallocz(sizeof(PXA2xxGPIOInfo));
305 memset(s, 0, sizeof(PXA2xxGPIOInfo));
306 s->pic = pic;
307 s->lines = lines;
308 s->cpu_env = env;
309 s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines);
310
311 iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
312 pxa2xx_gpio_writefn, s);
313 cpu_register_physical_memory(base, 0x00001000, iomemtype);
314
315 register_savevm("pxa2xx_gpio", 0, 0,
316 pxa2xx_gpio_save, pxa2xx_gpio_load, s);
317
318 return s;
319}
320
321qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s)
322{
323 return s->in;
324}
325
326void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
327 int line, qemu_irq handler)
328{
329 if (line >= s->lines) {
330 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
331 return;
332 }
333
334 s->handler[line] = handler;
335}
336
337
338
339
340
341void pxa2xx_gpio_read_notifier(PXA2xxGPIOInfo *s, qemu_irq handler)
342{
343 s->read_notify = handler;
344}
345
