1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include "sysbus.h"
25#include "qemu-timer.h"
26#include "sun4m.h"
27#include "nvram.h"
28#include "sparc32_dma.h"
29#include "fdc.h"
30#include "sysemu.h"
31#include "net.h"
32#include "boards.h"
33#include "firmware_abi.h"
34#include "esp.h"
35#include "pc.h"
36#include "isa.h"
37#include "fw_cfg.h"
38#include "escc.h"
39#include "qdev-addr.h"
40#include "loader.h"
41#include "elf.h"
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73#ifdef DEBUG_IRQ
74#define DPRINTF(fmt, ...) \
75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
76#else
77#define DPRINTF(fmt, ...)
78#endif
79
80#define KERNEL_LOAD_ADDR 0x00004000
81#define CMDLINE_ADDR 0x007ff000
82#define INITRD_LOAD_ADDR 0x00800000
83#define PROM_SIZE_MAX (1024 * 1024)
84#define PROM_VADDR 0xffd00000
85#define PROM_FILENAME "openbios-sparc32"
86#define CFG_ADDR 0xd00000510ULL
87#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
88
89#define MAX_CPUS 16
90#define MAX_PILS 16
91
92#define ESCC_CLOCK 4915200
93
94struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 uint8_t nvram_machine_id;
103 uint16_t machine_id;
104 uint32_t iommu_version;
105 uint64_t max_mem;
106 const char * const default_cpu_model;
107};
108
109#define MAX_IOUNITS 5
110
111struct sun4d_hwdef {
112 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114 target_phys_addr_t serial_base;
115 target_phys_addr_t espdma_base, esp_base;
116 target_phys_addr_t ledma_base, le_base;
117 target_phys_addr_t tcx_base;
118 target_phys_addr_t sbi_base;
119 uint8_t nvram_machine_id;
120 uint16_t machine_id;
121 uint32_t iounit_version;
122 uint64_t max_mem;
123 const char * const default_cpu_model;
124};
125
126struct sun4c_hwdef {
127 target_phys_addr_t iommu_base, slavio_base;
128 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
129 target_phys_addr_t serial_base, fd_base;
130 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
131 target_phys_addr_t tcx_base, aux1_base;
132 uint8_t nvram_machine_id;
133 uint16_t machine_id;
134 uint32_t iommu_version;
135 uint64_t max_mem;
136 const char * const default_cpu_model;
137};
138
139int DMA_get_channel_mode (int nchan)
140{
141 return 0;
142}
143int DMA_read_memory (int nchan, void *buf, int pos, int size)
144{
145 return 0;
146}
147int DMA_write_memory (int nchan, void *buf, int pos, int size)
148{
149 return 0;
150}
151void DMA_hold_DREQ (int nchan) {}
152void DMA_release_DREQ (int nchan) {}
153void DMA_schedule(int nchan) {}
154void DMA_init (int high_page_enable) {}
155void DMA_register_channel (int nchan,
156 DMA_transfer_handler transfer_handler,
157 void *opaque)
158{
159}
160
161static int fw_cfg_boot_set(void *opaque, const char *boot_device)
162{
163 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
164 return 0;
165}
166
167static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
168 const char *boot_devices, ram_addr_t RAM_size,
169 uint32_t kernel_size,
170 int width, int height, int depth,
171 int nvram_machine_id, const char *arch)
172{
173 unsigned int i;
174 uint32_t start, end;
175 uint8_t image[0x1ff0];
176 struct OpenBIOS_nvpart_v1 *part_header;
177
178 memset(image, '\0', sizeof(image));
179
180 start = 0;
181
182
183
184 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
185 part_header->signature = OPENBIOS_PART_SYSTEM;
186 pstrcpy(part_header->name, sizeof(part_header->name), "system");
187
188 end = start + sizeof(struct OpenBIOS_nvpart_v1);
189 for (i = 0; i < nb_prom_envs; i++)
190 end = OpenBIOS_set_var(image, end, prom_envs[i]);
191
192
193 image[end++] = '\0';
194
195 end = start + ((end - start + 15) & ~15);
196 OpenBIOS_finish_partition(part_header, end - start);
197
198
199 start = end;
200 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
201 part_header->signature = OPENBIOS_PART_FREE;
202 pstrcpy(part_header->name, sizeof(part_header->name), "free");
203
204 end = 0x1fd0;
205 OpenBIOS_finish_partition(part_header, end - start);
206
207 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
208 nvram_machine_id);
209
210 for (i = 0; i < sizeof(image); i++)
211 m48t59_write(nvram, i, image[i]);
212}
213
214static DeviceState *slavio_intctl;
215
216void pic_info(Monitor *mon)
217{
218 if (slavio_intctl)
219 slavio_pic_info(mon, slavio_intctl);
220}
221
222void irq_info(Monitor *mon)
223{
224 if (slavio_intctl)
225 slavio_irq_info(mon, slavio_intctl);
226}
227
228void cpu_check_irqs(CPUState *env)
229{
230 if (env->pil_in && (env->interrupt_index == 0 ||
231 (env->interrupt_index & ~15) == TT_EXTINT)) {
232 unsigned int i;
233
234 for (i = 15; i > 0; i--) {
235 if (env->pil_in & (1 << i)) {
236 int old_interrupt = env->interrupt_index;
237
238 env->interrupt_index = TT_EXTINT | i;
239 if (old_interrupt != env->interrupt_index) {
240 DPRINTF("Set CPU IRQ %d\n", i);
241 cpu_interrupt(env, CPU_INTERRUPT_HARD);
242 }
243 break;
244 }
245 }
246 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
247 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
248 env->interrupt_index = 0;
249 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
250 }
251}
252
253static void cpu_set_irq(void *opaque, int irq, int level)
254{
255 CPUState *env = opaque;
256
257 if (level) {
258 DPRINTF("Raise CPU IRQ %d\n", irq);
259 env->halted = 0;
260 env->pil_in |= 1 << irq;
261 cpu_check_irqs(env);
262 } else {
263 DPRINTF("Lower CPU IRQ %d\n", irq);
264 env->pil_in &= ~(1 << irq);
265 cpu_check_irqs(env);
266 }
267}
268
269static void dummy_cpu_set_irq(void *opaque, int irq, int level)
270{
271}
272
273static void main_cpu_reset(void *opaque)
274{
275 CPUState *env = opaque;
276
277 cpu_reset(env);
278 env->halted = 0;
279}
280
281static void secondary_cpu_reset(void *opaque)
282{
283 CPUState *env = opaque;
284
285 cpu_reset(env);
286 env->halted = 1;
287}
288
289static void cpu_halt_signal(void *opaque, int irq, int level)
290{
291 if (level && cpu_single_env)
292 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
293}
294
295static unsigned long sun4m_load_kernel(const char *kernel_filename,
296 const char *initrd_filename,
297 ram_addr_t RAM_size)
298{
299 int linux_boot;
300 unsigned int i;
301 long initrd_size, kernel_size;
302 uint8_t *ptr;
303
304 linux_boot = (kernel_filename != NULL);
305
306 kernel_size = 0;
307 if (linux_boot) {
308 int bswap_needed;
309
310#ifdef BSWAP_NEEDED
311 bswap_needed = 1;
312#else
313 bswap_needed = 0;
314#endif
315 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
316 NULL, 1, ELF_MACHINE, 0);
317 if (kernel_size < 0)
318 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
319 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
320 TARGET_PAGE_SIZE);
321 if (kernel_size < 0)
322 kernel_size = load_image_targphys(kernel_filename,
323 KERNEL_LOAD_ADDR,
324 RAM_size - KERNEL_LOAD_ADDR);
325 if (kernel_size < 0) {
326 fprintf(stderr, "qemu: could not load kernel '%s'\n",
327 kernel_filename);
328 exit(1);
329 }
330
331
332 initrd_size = 0;
333 if (initrd_filename) {
334 initrd_size = load_image_targphys(initrd_filename,
335 INITRD_LOAD_ADDR,
336 RAM_size - INITRD_LOAD_ADDR);
337 if (initrd_size < 0) {
338 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
339 initrd_filename);
340 exit(1);
341 }
342 }
343 if (initrd_size > 0) {
344 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
345 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
346 if (ldl_p(ptr) == 0x48647253) {
347 stl_p(ptr + 16, INITRD_LOAD_ADDR);
348 stl_p(ptr + 20, initrd_size);
349 break;
350 }
351 }
352 }
353 }
354 return kernel_size;
355}
356
357static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
358{
359 DeviceState *dev;
360 SysBusDevice *s;
361
362 dev = qdev_create(NULL, "iommu");
363 qdev_prop_set_uint32(dev, "version", version);
364 qdev_init_nofail(dev);
365 s = sysbus_from_qdev(dev);
366 sysbus_connect_irq(s, 0, irq);
367 sysbus_mmio_map(s, 0, addr);
368
369 return s;
370}
371
372static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
373 void *iommu, qemu_irq *dev_irq)
374{
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "sparc32_dma");
379 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, parent_irq);
383 *dev_irq = qdev_get_gpio_in(dev, 0);
384 sysbus_mmio_map(s, 0, daddr);
385
386 return s;
387}
388
389static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
390 void *dma_opaque, qemu_irq irq)
391{
392 DeviceState *dev;
393 SysBusDevice *s;
394 qemu_irq reset;
395
396 qemu_check_nic_model(&nd_table[0], "lance");
397
398 dev = qdev_create(NULL, "lance");
399 qdev_set_nic_properties(dev, nd);
400 qdev_prop_set_ptr(dev, "dma", dma_opaque);
401 qdev_init_nofail(dev);
402 s = sysbus_from_qdev(dev);
403 sysbus_mmio_map(s, 0, leaddr);
404 sysbus_connect_irq(s, 0, irq);
405 reset = qdev_get_gpio_in(dev, 0);
406 qdev_connect_gpio_out(dma_opaque, 0, reset);
407}
408
409static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
410 target_phys_addr_t addrg,
411 qemu_irq **parent_irq)
412{
413 DeviceState *dev;
414 SysBusDevice *s;
415 unsigned int i, j;
416
417 dev = qdev_create(NULL, "slavio_intctl");
418 qdev_init_nofail(dev);
419
420 s = sysbus_from_qdev(dev);
421
422 for (i = 0; i < MAX_CPUS; i++) {
423 for (j = 0; j < MAX_PILS; j++) {
424 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
425 }
426 }
427 sysbus_mmio_map(s, 0, addrg);
428 for (i = 0; i < MAX_CPUS; i++) {
429 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
430 }
431
432 return dev;
433}
434
435#define SYS_TIMER_OFFSET 0x10000ULL
436#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
437
438static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
439 qemu_irq *cpu_irqs, unsigned int num_cpus)
440{
441 DeviceState *dev;
442 SysBusDevice *s;
443 unsigned int i;
444
445 dev = qdev_create(NULL, "slavio_timer");
446 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
447 qdev_init_nofail(dev);
448 s = sysbus_from_qdev(dev);
449 sysbus_connect_irq(s, 0, master_irq);
450 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
451
452 for (i = 0; i < MAX_CPUS; i++) {
453 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
454 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
455 }
456}
457
458#define MISC_LEDS 0x01600000
459#define MISC_CFG 0x01800000
460#define MISC_DIAG 0x01a00000
461#define MISC_MDM 0x01b00000
462#define MISC_SYS 0x01f00000
463
464static void slavio_misc_init(target_phys_addr_t base,
465 target_phys_addr_t aux1_base,
466 target_phys_addr_t aux2_base, qemu_irq irq,
467 qemu_irq fdc_tc)
468{
469 DeviceState *dev;
470 SysBusDevice *s;
471
472 dev = qdev_create(NULL, "slavio_misc");
473 qdev_init_nofail(dev);
474 s = sysbus_from_qdev(dev);
475 if (base) {
476
477
478 sysbus_mmio_map(s, 0, base + MISC_CFG);
479
480 sysbus_mmio_map(s, 1, base + MISC_DIAG);
481
482 sysbus_mmio_map(s, 2, base + MISC_MDM);
483
484
485 sysbus_mmio_map(s, 3, base + MISC_LEDS);
486
487
488 sysbus_mmio_map(s, 4, base + MISC_SYS);
489 }
490 if (aux1_base) {
491
492 sysbus_mmio_map(s, 5, aux1_base);
493 }
494 if (aux2_base) {
495
496 sysbus_mmio_map(s, 6, aux2_base);
497 }
498 sysbus_connect_irq(s, 0, irq);
499 sysbus_connect_irq(s, 1, fdc_tc);
500 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
501}
502
503static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
504{
505 DeviceState *dev;
506 SysBusDevice *s;
507
508 dev = qdev_create(NULL, "eccmemctl");
509 qdev_prop_set_uint32(dev, "version", version);
510 qdev_init_nofail(dev);
511 s = sysbus_from_qdev(dev);
512 sysbus_connect_irq(s, 0, irq);
513 sysbus_mmio_map(s, 0, base);
514 if (version == 0) {
515 sysbus_mmio_map(s, 1, base + 0x1000);
516 }
517}
518
519static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
520{
521 DeviceState *dev;
522 SysBusDevice *s;
523
524 dev = qdev_create(NULL, "apc");
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527
528 sysbus_mmio_map(s, 0, power_base);
529 sysbus_connect_irq(s, 0, cpu_halt);
530}
531
532static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
533 int height, int depth)
534{
535 DeviceState *dev;
536 SysBusDevice *s;
537
538 dev = qdev_create(NULL, "SUNW,tcx");
539 qdev_prop_set_taddr(dev, "addr", addr);
540 qdev_prop_set_uint32(dev, "vram_size", vram_size);
541 qdev_prop_set_uint16(dev, "width", width);
542 qdev_prop_set_uint16(dev, "height", height);
543 qdev_prop_set_uint16(dev, "depth", depth);
544 qdev_init_nofail(dev);
545 s = sysbus_from_qdev(dev);
546
547 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
548
549 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
550
551 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
552
553 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
554 if (depth == 24) {
555
556 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
557
558 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
559 } else {
560
561 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
562 }
563}
564
565
566static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
567
568static void idreg_init(target_phys_addr_t addr)
569{
570 DeviceState *dev;
571 SysBusDevice *s;
572
573 dev = qdev_create(NULL, "macio_idreg");
574 qdev_init_nofail(dev);
575 s = sysbus_from_qdev(dev);
576
577 sysbus_mmio_map(s, 0, addr);
578 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
579}
580
581static int idreg_init1(SysBusDevice *dev)
582{
583 ram_addr_t idreg_offset;
584
585 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
586 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
587 return 0;
588}
589
590static SysBusDeviceInfo idreg_info = {
591 .init = idreg_init1,
592 .qdev.name = "macio_idreg",
593 .qdev.size = sizeof(SysBusDevice),
594};
595
596static void idreg_register_devices(void)
597{
598 sysbus_register_withprop(&idreg_info);
599}
600
601device_init(idreg_register_devices);
602
603
604static void prom_init(target_phys_addr_t addr, const char *bios_name)
605{
606 DeviceState *dev;
607 SysBusDevice *s;
608 char *filename;
609 int ret;
610
611 dev = qdev_create(NULL, "openprom");
612 qdev_init_nofail(dev);
613 s = sysbus_from_qdev(dev);
614
615 sysbus_mmio_map(s, 0, addr);
616
617
618 if (bios_name == NULL) {
619 bios_name = PROM_FILENAME;
620 }
621 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
622 if (filename) {
623 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
624 1, ELF_MACHINE, 0);
625 if (ret < 0 || ret > PROM_SIZE_MAX) {
626 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
627 }
628 qemu_free(filename);
629 } else {
630 ret = -1;
631 }
632 if (ret < 0 || ret > PROM_SIZE_MAX) {
633 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
634 exit(1);
635 }
636}
637
638static int prom_init1(SysBusDevice *dev)
639{
640 ram_addr_t prom_offset;
641
642 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
643 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
644 return 0;
645}
646
647static SysBusDeviceInfo prom_info = {
648 .init = prom_init1,
649 .qdev.name = "openprom",
650 .qdev.size = sizeof(SysBusDevice),
651 .qdev.props = (Property[]) {
652 {}
653 }
654};
655
656static void prom_register_devices(void)
657{
658 sysbus_register_withprop(&prom_info);
659}
660
661device_init(prom_register_devices);
662
663typedef struct RamDevice
664{
665 SysBusDevice busdev;
666 uint64_t size;
667} RamDevice;
668
669
670static int ram_init1(SysBusDevice *dev)
671{
672 ram_addr_t RAM_size, ram_offset;
673 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
674
675 RAM_size = d->size;
676
677 ram_offset = qemu_ram_alloc(RAM_size);
678 sysbus_init_mmio(dev, RAM_size, ram_offset);
679 return 0;
680}
681
682static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
683 uint64_t max_mem)
684{
685 DeviceState *dev;
686 SysBusDevice *s;
687 RamDevice *d;
688
689
690 if ((uint64_t)RAM_size > max_mem) {
691 fprintf(stderr,
692 "qemu: Too much memory for this machine: %d, maximum %d\n",
693 (unsigned int)(RAM_size / (1024 * 1024)),
694 (unsigned int)(max_mem / (1024 * 1024)));
695 exit(1);
696 }
697 dev = qdev_create(NULL, "memory");
698 s = sysbus_from_qdev(dev);
699
700 d = FROM_SYSBUS(RamDevice, s);
701 d->size = RAM_size;
702 qdev_init_nofail(dev);
703
704 sysbus_mmio_map(s, 0, addr);
705}
706
707static SysBusDeviceInfo ram_info = {
708 .init = ram_init1,
709 .qdev.name = "memory",
710 .qdev.size = sizeof(RamDevice),
711 .qdev.props = (Property[]) {
712 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
713 DEFINE_PROP_END_OF_LIST(),
714 }
715};
716
717static void ram_register_devices(void)
718{
719 sysbus_register_withprop(&ram_info);
720}
721
722device_init(ram_register_devices);
723
724static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
725 uint64_t prom_addr, qemu_irq **cpu_irqs)
726{
727 CPUState *env;
728
729 env = cpu_init(cpu_model);
730 if (!env) {
731 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
732 exit(1);
733 }
734
735 cpu_sparc_set_id(env, id);
736 if (id == 0) {
737 qemu_register_reset(main_cpu_reset, env);
738 } else {
739 qemu_register_reset(secondary_cpu_reset, env);
740 env->halted = 1;
741 }
742 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
743 env->prom_addr = prom_addr;
744
745 return env;
746}
747
748static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
749 const char *boot_device,
750 const char *kernel_filename,
751 const char *kernel_cmdline,
752 const char *initrd_filename, const char *cpu_model)
753{
754 CPUState *envs[MAX_CPUS];
755 unsigned int i;
756 void *iommu, *espdma, *ledma, *nvram;
757 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
758 espdma_irq, ledma_irq;
759 qemu_irq esp_reset;
760 qemu_irq fdc_tc;
761 qemu_irq *cpu_halt;
762 unsigned long kernel_size;
763 DriveInfo *fd[MAX_FD];
764 void *fw_cfg;
765
766
767 if (!cpu_model)
768 cpu_model = hwdef->default_cpu_model;
769
770 for(i = 0; i < smp_cpus; i++) {
771 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
772 }
773
774 for (i = smp_cpus; i < MAX_CPUS; i++)
775 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
776
777
778
779 ram_init(0, RAM_size, hwdef->max_mem);
780
781 prom_init(hwdef->slavio_base, bios_name);
782
783 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
784 hwdef->intctl_base + 0x10000ULL,
785 cpu_irqs);
786
787 for (i = 0; i < 32; i++) {
788 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
789 }
790 for (i = 0; i < MAX_CPUS; i++) {
791 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
792 }
793
794 if (hwdef->idreg_base) {
795 idreg_init(hwdef->idreg_base);
796 }
797
798 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
799 slavio_irq[30]);
800
801 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
802 iommu, &espdma_irq);
803
804 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
805 slavio_irq[16], iommu, &ledma_irq);
806
807 if (graphic_depth != 8 && graphic_depth != 24) {
808 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
809 exit (1);
810 }
811 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
812 graphic_depth);
813
814 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
815
816 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
817
818 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
819
820 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
821 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
822
823
824 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
825 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
826
827 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
828 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
829 slavio_irq[30], fdc_tc);
830
831 if (hwdef->apc_base) {
832 apc_init(hwdef->apc_base, cpu_halt[0]);
833 }
834
835 if (hwdef->fd_base) {
836
837 memset(fd, 0, sizeof(fd));
838 fd[0] = drive_get(IF_FLOPPY, 0, 0);
839 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
840 &fdc_tc);
841 }
842
843 if (drive_get_max_bus(IF_SCSI) > 0) {
844 fprintf(stderr, "qemu: too many SCSI bus\n");
845 exit(1);
846 }
847
848 esp_reset = qdev_get_gpio_in(espdma, 0);
849 esp_init(hwdef->esp_base, 2,
850 espdma_memory_read, espdma_memory_write,
851 espdma, espdma_irq, &esp_reset);
852
853
854 if (hwdef->cs_base) {
855 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
856 slavio_irq[5]);
857 }
858
859 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
860 RAM_size);
861
862 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
863 boot_device, RAM_size, kernel_size, graphic_width,
864 graphic_height, graphic_depth, hwdef->nvram_machine_id,
865 "Sun4m");
866
867 if (hwdef->ecc_base)
868 ecc_init(hwdef->ecc_base, slavio_irq[28],
869 hwdef->ecc_version);
870
871 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
872 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
873 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
874 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
875 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
876 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
877 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
878 if (kernel_cmdline) {
879 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
880 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
881 } else {
882 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
883 }
884 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
885 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
886 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
887 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
888}
889
890enum {
891 ss2_id = 0,
892 ss5_id = 32,
893 vger_id,
894 lx_id,
895 ss4_id,
896 scls_id,
897 sbook_id,
898 ss10_id = 64,
899 ss20_id,
900 ss600mp_id,
901 ss1000_id = 96,
902 ss2000_id,
903};
904
905static const struct sun4m_hwdef sun4m_hwdefs[] = {
906
907 {
908 .iommu_base = 0x10000000,
909 .tcx_base = 0x50000000,
910 .cs_base = 0x6c000000,
911 .slavio_base = 0x70000000,
912 .ms_kb_base = 0x71000000,
913 .serial_base = 0x71100000,
914 .nvram_base = 0x71200000,
915 .fd_base = 0x71400000,
916 .counter_base = 0x71d00000,
917 .intctl_base = 0x71e00000,
918 .idreg_base = 0x78000000,
919 .dma_base = 0x78400000,
920 .esp_base = 0x78800000,
921 .le_base = 0x78c00000,
922 .apc_base = 0x6a000000,
923 .aux1_base = 0x71900000,
924 .aux2_base = 0x71910000,
925 .nvram_machine_id = 0x80,
926 .machine_id = ss5_id,
927 .iommu_version = 0x05000000,
928 .max_mem = 0x10000000,
929 .default_cpu_model = "Fujitsu MB86904",
930 },
931
932 {
933 .iommu_base = 0xfe0000000ULL,
934 .tcx_base = 0xe20000000ULL,
935 .slavio_base = 0xff0000000ULL,
936 .ms_kb_base = 0xff1000000ULL,
937 .serial_base = 0xff1100000ULL,
938 .nvram_base = 0xff1200000ULL,
939 .fd_base = 0xff1700000ULL,
940 .counter_base = 0xff1300000ULL,
941 .intctl_base = 0xff1400000ULL,
942 .idreg_base = 0xef0000000ULL,
943 .dma_base = 0xef0400000ULL,
944 .esp_base = 0xef0800000ULL,
945 .le_base = 0xef0c00000ULL,
946 .apc_base = 0xefa000000ULL,
947 .aux1_base = 0xff1800000ULL,
948 .aux2_base = 0xff1a01000ULL,
949 .ecc_base = 0xf00000000ULL,
950 .ecc_version = 0x10000000,
951 .nvram_machine_id = 0x72,
952 .machine_id = ss10_id,
953 .iommu_version = 0x03000000,
954 .max_mem = 0xf00000000ULL,
955 .default_cpu_model = "TI SuperSparc II",
956 },
957
958 {
959 .iommu_base = 0xfe0000000ULL,
960 .tcx_base = 0xe20000000ULL,
961 .slavio_base = 0xff0000000ULL,
962 .ms_kb_base = 0xff1000000ULL,
963 .serial_base = 0xff1100000ULL,
964 .nvram_base = 0xff1200000ULL,
965 .counter_base = 0xff1300000ULL,
966 .intctl_base = 0xff1400000ULL,
967 .dma_base = 0xef0081000ULL,
968 .esp_base = 0xef0080000ULL,
969 .le_base = 0xef0060000ULL,
970 .apc_base = 0xefa000000ULL,
971 .aux1_base = 0xff1800000ULL,
972 .aux2_base = 0xff1a01000ULL,
973 .ecc_base = 0xf00000000ULL,
974 .ecc_version = 0x00000000,
975 .nvram_machine_id = 0x71,
976 .machine_id = ss600mp_id,
977 .iommu_version = 0x01000000,
978 .max_mem = 0xf00000000ULL,
979 .default_cpu_model = "TI SuperSparc II",
980 },
981
982 {
983 .iommu_base = 0xfe0000000ULL,
984 .tcx_base = 0xe20000000ULL,
985 .slavio_base = 0xff0000000ULL,
986 .ms_kb_base = 0xff1000000ULL,
987 .serial_base = 0xff1100000ULL,
988 .nvram_base = 0xff1200000ULL,
989 .fd_base = 0xff1700000ULL,
990 .counter_base = 0xff1300000ULL,
991 .intctl_base = 0xff1400000ULL,
992 .idreg_base = 0xef0000000ULL,
993 .dma_base = 0xef0400000ULL,
994 .esp_base = 0xef0800000ULL,
995 .le_base = 0xef0c00000ULL,
996 .apc_base = 0xefa000000ULL,
997 .aux1_base = 0xff1800000ULL,
998 .aux2_base = 0xff1a01000ULL,
999 .ecc_base = 0xf00000000ULL,
1000 .ecc_version = 0x20000000,
1001 .nvram_machine_id = 0x72,
1002 .machine_id = ss20_id,
1003 .iommu_version = 0x13000000,
1004 .max_mem = 0xf00000000ULL,
1005 .default_cpu_model = "TI SuperSparc II",
1006 },
1007
1008 {
1009 .iommu_base = 0x10000000,
1010 .tcx_base = 0x50000000,
1011 .slavio_base = 0x70000000,
1012 .ms_kb_base = 0x71000000,
1013 .serial_base = 0x71100000,
1014 .nvram_base = 0x71200000,
1015 .fd_base = 0x71400000,
1016 .counter_base = 0x71d00000,
1017 .intctl_base = 0x71e00000,
1018 .idreg_base = 0x78000000,
1019 .dma_base = 0x78400000,
1020 .esp_base = 0x78800000,
1021 .le_base = 0x78c00000,
1022 .apc_base = 0x71300000,
1023 .aux1_base = 0x71900000,
1024 .aux2_base = 0x71910000,
1025 .nvram_machine_id = 0x80,
1026 .machine_id = vger_id,
1027 .iommu_version = 0x05000000,
1028 .max_mem = 0x10000000,
1029 .default_cpu_model = "Fujitsu MB86904",
1030 },
1031
1032 {
1033 .iommu_base = 0x10000000,
1034 .tcx_base = 0x50000000,
1035 .slavio_base = 0x70000000,
1036 .ms_kb_base = 0x71000000,
1037 .serial_base = 0x71100000,
1038 .nvram_base = 0x71200000,
1039 .fd_base = 0x71400000,
1040 .counter_base = 0x71d00000,
1041 .intctl_base = 0x71e00000,
1042 .idreg_base = 0x78000000,
1043 .dma_base = 0x78400000,
1044 .esp_base = 0x78800000,
1045 .le_base = 0x78c00000,
1046 .aux1_base = 0x71900000,
1047 .aux2_base = 0x71910000,
1048 .nvram_machine_id = 0x80,
1049 .machine_id = lx_id,
1050 .iommu_version = 0x04000000,
1051 .max_mem = 0x10000000,
1052 .default_cpu_model = "TI MicroSparc I",
1053 },
1054
1055 {
1056 .iommu_base = 0x10000000,
1057 .tcx_base = 0x50000000,
1058 .cs_base = 0x6c000000,
1059 .slavio_base = 0x70000000,
1060 .ms_kb_base = 0x71000000,
1061 .serial_base = 0x71100000,
1062 .nvram_base = 0x71200000,
1063 .fd_base = 0x71400000,
1064 .counter_base = 0x71d00000,
1065 .intctl_base = 0x71e00000,
1066 .idreg_base = 0x78000000,
1067 .dma_base = 0x78400000,
1068 .esp_base = 0x78800000,
1069 .le_base = 0x78c00000,
1070 .apc_base = 0x6a000000,
1071 .aux1_base = 0x71900000,
1072 .aux2_base = 0x71910000,
1073 .nvram_machine_id = 0x80,
1074 .machine_id = ss4_id,
1075 .iommu_version = 0x05000000,
1076 .max_mem = 0x10000000,
1077 .default_cpu_model = "Fujitsu MB86904",
1078 },
1079
1080 {
1081 .iommu_base = 0x10000000,
1082 .tcx_base = 0x50000000,
1083 .slavio_base = 0x70000000,
1084 .ms_kb_base = 0x71000000,
1085 .serial_base = 0x71100000,
1086 .nvram_base = 0x71200000,
1087 .fd_base = 0x71400000,
1088 .counter_base = 0x71d00000,
1089 .intctl_base = 0x71e00000,
1090 .idreg_base = 0x78000000,
1091 .dma_base = 0x78400000,
1092 .esp_base = 0x78800000,
1093 .le_base = 0x78c00000,
1094 .apc_base = 0x6a000000,
1095 .aux1_base = 0x71900000,
1096 .aux2_base = 0x71910000,
1097 .nvram_machine_id = 0x80,
1098 .machine_id = scls_id,
1099 .iommu_version = 0x05000000,
1100 .max_mem = 0x10000000,
1101 .default_cpu_model = "TI MicroSparc I",
1102 },
1103
1104 {
1105 .iommu_base = 0x10000000,
1106 .tcx_base = 0x50000000,
1107 .slavio_base = 0x70000000,
1108 .ms_kb_base = 0x71000000,
1109 .serial_base = 0x71100000,
1110 .nvram_base = 0x71200000,
1111 .fd_base = 0x71400000,
1112 .counter_base = 0x71d00000,
1113 .intctl_base = 0x71e00000,
1114 .idreg_base = 0x78000000,
1115 .dma_base = 0x78400000,
1116 .esp_base = 0x78800000,
1117 .le_base = 0x78c00000,
1118 .apc_base = 0x6a000000,
1119 .aux1_base = 0x71900000,
1120 .aux2_base = 0x71910000,
1121 .nvram_machine_id = 0x80,
1122 .machine_id = sbook_id,
1123 .iommu_version = 0x05000000,
1124 .max_mem = 0x10000000,
1125 .default_cpu_model = "TI MicroSparc I",
1126 },
1127};
1128
1129
1130static void ss5_init(ram_addr_t RAM_size,
1131 const char *boot_device,
1132 const char *kernel_filename, const char *kernel_cmdline,
1133 const char *initrd_filename, const char *cpu_model)
1134{
1135 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1136 kernel_cmdline, initrd_filename, cpu_model);
1137}
1138
1139
1140static void ss10_init(ram_addr_t RAM_size,
1141 const char *boot_device,
1142 const char *kernel_filename, const char *kernel_cmdline,
1143 const char *initrd_filename, const char *cpu_model)
1144{
1145 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1146 kernel_cmdline, initrd_filename, cpu_model);
1147}
1148
1149
1150static void ss600mp_init(ram_addr_t RAM_size,
1151 const char *boot_device,
1152 const char *kernel_filename,
1153 const char *kernel_cmdline,
1154 const char *initrd_filename, const char *cpu_model)
1155{
1156 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1157 kernel_cmdline, initrd_filename, cpu_model);
1158}
1159
1160
1161static void ss20_init(ram_addr_t RAM_size,
1162 const char *boot_device,
1163 const char *kernel_filename, const char *kernel_cmdline,
1164 const char *initrd_filename, const char *cpu_model)
1165{
1166 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1167 kernel_cmdline, initrd_filename, cpu_model);
1168}
1169
1170
1171static void vger_init(ram_addr_t RAM_size,
1172 const char *boot_device,
1173 const char *kernel_filename, const char *kernel_cmdline,
1174 const char *initrd_filename, const char *cpu_model)
1175{
1176 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1177 kernel_cmdline, initrd_filename, cpu_model);
1178}
1179
1180
1181static void ss_lx_init(ram_addr_t RAM_size,
1182 const char *boot_device,
1183 const char *kernel_filename, const char *kernel_cmdline,
1184 const char *initrd_filename, const char *cpu_model)
1185{
1186 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1187 kernel_cmdline, initrd_filename, cpu_model);
1188}
1189
1190
1191static void ss4_init(ram_addr_t RAM_size,
1192 const char *boot_device,
1193 const char *kernel_filename, const char *kernel_cmdline,
1194 const char *initrd_filename, const char *cpu_model)
1195{
1196 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1197 kernel_cmdline, initrd_filename, cpu_model);
1198}
1199
1200
1201static void scls_init(ram_addr_t RAM_size,
1202 const char *boot_device,
1203 const char *kernel_filename, const char *kernel_cmdline,
1204 const char *initrd_filename, const char *cpu_model)
1205{
1206 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1207 kernel_cmdline, initrd_filename, cpu_model);
1208}
1209
1210
1211static void sbook_init(ram_addr_t RAM_size,
1212 const char *boot_device,
1213 const char *kernel_filename, const char *kernel_cmdline,
1214 const char *initrd_filename, const char *cpu_model)
1215{
1216 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1217 kernel_cmdline, initrd_filename, cpu_model);
1218}
1219
1220static QEMUMachine ss5_machine = {
1221 .name = "SS-5",
1222 .desc = "Sun4m platform, SPARCstation 5",
1223 .init = ss5_init,
1224 .use_scsi = 1,
1225 .is_default = 1,
1226};
1227
1228static QEMUMachine ss10_machine = {
1229 .name = "SS-10",
1230 .desc = "Sun4m platform, SPARCstation 10",
1231 .init = ss10_init,
1232 .use_scsi = 1,
1233 .max_cpus = 4,
1234};
1235
1236static QEMUMachine ss600mp_machine = {
1237 .name = "SS-600MP",
1238 .desc = "Sun4m platform, SPARCserver 600MP",
1239 .init = ss600mp_init,
1240 .use_scsi = 1,
1241 .max_cpus = 4,
1242};
1243
1244static QEMUMachine ss20_machine = {
1245 .name = "SS-20",
1246 .desc = "Sun4m platform, SPARCstation 20",
1247 .init = ss20_init,
1248 .use_scsi = 1,
1249 .max_cpus = 4,
1250};
1251
1252static QEMUMachine voyager_machine = {
1253 .name = "Voyager",
1254 .desc = "Sun4m platform, SPARCstation Voyager",
1255 .init = vger_init,
1256 .use_scsi = 1,
1257};
1258
1259static QEMUMachine ss_lx_machine = {
1260 .name = "LX",
1261 .desc = "Sun4m platform, SPARCstation LX",
1262 .init = ss_lx_init,
1263 .use_scsi = 1,
1264};
1265
1266static QEMUMachine ss4_machine = {
1267 .name = "SS-4",
1268 .desc = "Sun4m platform, SPARCstation 4",
1269 .init = ss4_init,
1270 .use_scsi = 1,
1271};
1272
1273static QEMUMachine scls_machine = {
1274 .name = "SPARCClassic",
1275 .desc = "Sun4m platform, SPARCClassic",
1276 .init = scls_init,
1277 .use_scsi = 1,
1278};
1279
1280static QEMUMachine sbook_machine = {
1281 .name = "SPARCbook",
1282 .desc = "Sun4m platform, SPARCbook",
1283 .init = sbook_init,
1284 .use_scsi = 1,
1285};
1286
1287static const struct sun4d_hwdef sun4d_hwdefs[] = {
1288
1289 {
1290 .iounit_bases = {
1291 0xfe0200000ULL,
1292 0xfe1200000ULL,
1293 0xfe2200000ULL,
1294 0xfe3200000ULL,
1295 -1,
1296 },
1297 .tcx_base = 0x820000000ULL,
1298 .slavio_base = 0xf00000000ULL,
1299 .ms_kb_base = 0xf00240000ULL,
1300 .serial_base = 0xf00200000ULL,
1301 .nvram_base = 0xf00280000ULL,
1302 .counter_base = 0xf00300000ULL,
1303 .espdma_base = 0x800081000ULL,
1304 .esp_base = 0x800080000ULL,
1305 .ledma_base = 0x800040000ULL,
1306 .le_base = 0x800060000ULL,
1307 .sbi_base = 0xf02800000ULL,
1308 .nvram_machine_id = 0x80,
1309 .machine_id = ss1000_id,
1310 .iounit_version = 0x03000000,
1311 .max_mem = 0xf00000000ULL,
1312 .default_cpu_model = "TI SuperSparc II",
1313 },
1314
1315 {
1316 .iounit_bases = {
1317 0xfe0200000ULL,
1318 0xfe1200000ULL,
1319 0xfe2200000ULL,
1320 0xfe3200000ULL,
1321 0xfe4200000ULL,
1322 },
1323 .tcx_base = 0x820000000ULL,
1324 .slavio_base = 0xf00000000ULL,
1325 .ms_kb_base = 0xf00240000ULL,
1326 .serial_base = 0xf00200000ULL,
1327 .nvram_base = 0xf00280000ULL,
1328 .counter_base = 0xf00300000ULL,
1329 .espdma_base = 0x800081000ULL,
1330 .esp_base = 0x800080000ULL,
1331 .ledma_base = 0x800040000ULL,
1332 .le_base = 0x800060000ULL,
1333 .sbi_base = 0xf02800000ULL,
1334 .nvram_machine_id = 0x80,
1335 .machine_id = ss2000_id,
1336 .iounit_version = 0x03000000,
1337 .max_mem = 0xf00000000ULL,
1338 .default_cpu_model = "TI SuperSparc II",
1339 },
1340};
1341
1342static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1343{
1344 DeviceState *dev;
1345 SysBusDevice *s;
1346 unsigned int i;
1347
1348 dev = qdev_create(NULL, "sbi");
1349 qdev_init_nofail(dev);
1350
1351 s = sysbus_from_qdev(dev);
1352
1353 for (i = 0; i < MAX_CPUS; i++) {
1354 sysbus_connect_irq(s, i, *parent_irq[i]);
1355 }
1356
1357 sysbus_mmio_map(s, 0, addr);
1358
1359 return dev;
1360}
1361
1362static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1363 const char *boot_device,
1364 const char *kernel_filename,
1365 const char *kernel_cmdline,
1366 const char *initrd_filename, const char *cpu_model)
1367{
1368 CPUState *envs[MAX_CPUS];
1369 unsigned int i;
1370 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1371 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1372 espdma_irq, ledma_irq;
1373 qemu_irq esp_reset;
1374 unsigned long kernel_size;
1375 void *fw_cfg;
1376 DeviceState *dev;
1377
1378
1379 if (!cpu_model)
1380 cpu_model = hwdef->default_cpu_model;
1381
1382 for(i = 0; i < smp_cpus; i++) {
1383 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1384 }
1385
1386 for (i = smp_cpus; i < MAX_CPUS; i++)
1387 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1388
1389
1390 ram_init(0, RAM_size, hwdef->max_mem);
1391
1392 prom_init(hwdef->slavio_base, bios_name);
1393
1394 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1395
1396 for (i = 0; i < 32; i++) {
1397 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1398 }
1399 for (i = 0; i < MAX_CPUS; i++) {
1400 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1401 }
1402
1403 for (i = 0; i < MAX_IOUNITS; i++)
1404 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1405 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1406 hwdef->iounit_version,
1407 sbi_irq[0]);
1408
1409 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1410 iounits[0], &espdma_irq);
1411
1412 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1413 iounits[0], &ledma_irq);
1414
1415 if (graphic_depth != 8 && graphic_depth != 24) {
1416 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1417 exit (1);
1418 }
1419 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1420 graphic_depth);
1421
1422 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1423
1424 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1425
1426 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1427
1428 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1429 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1430
1431
1432 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1433 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1434
1435 if (drive_get_max_bus(IF_SCSI) > 0) {
1436 fprintf(stderr, "qemu: too many SCSI bus\n");
1437 exit(1);
1438 }
1439
1440 esp_reset = qdev_get_gpio_in(espdma, 0);
1441 esp_init(hwdef->esp_base, 2,
1442 espdma_memory_read, espdma_memory_write,
1443 espdma, espdma_irq, &esp_reset);
1444
1445 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1446 RAM_size);
1447
1448 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1449 boot_device, RAM_size, kernel_size, graphic_width,
1450 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1451 "Sun4d");
1452
1453 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1454 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1455 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1456 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1457 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1458 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1459 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1460 if (kernel_cmdline) {
1461 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1462 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1463 } else {
1464 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1465 }
1466 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1467 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1468 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1469 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1470}
1471
1472
1473static void ss1000_init(ram_addr_t RAM_size,
1474 const char *boot_device,
1475 const char *kernel_filename, const char *kernel_cmdline,
1476 const char *initrd_filename, const char *cpu_model)
1477{
1478 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1479 kernel_cmdline, initrd_filename, cpu_model);
1480}
1481
1482
1483static void ss2000_init(ram_addr_t RAM_size,
1484 const char *boot_device,
1485 const char *kernel_filename, const char *kernel_cmdline,
1486 const char *initrd_filename, const char *cpu_model)
1487{
1488 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1489 kernel_cmdline, initrd_filename, cpu_model);
1490}
1491
1492static QEMUMachine ss1000_machine = {
1493 .name = "SS-1000",
1494 .desc = "Sun4d platform, SPARCserver 1000",
1495 .init = ss1000_init,
1496 .use_scsi = 1,
1497 .max_cpus = 8,
1498};
1499
1500static QEMUMachine ss2000_machine = {
1501 .name = "SS-2000",
1502 .desc = "Sun4d platform, SPARCcenter 2000",
1503 .init = ss2000_init,
1504 .use_scsi = 1,
1505 .max_cpus = 20,
1506};
1507
1508static const struct sun4c_hwdef sun4c_hwdefs[] = {
1509
1510 {
1511 .iommu_base = 0xf8000000,
1512 .tcx_base = 0xfe000000,
1513 .slavio_base = 0xf6000000,
1514 .intctl_base = 0xf5000000,
1515 .counter_base = 0xf3000000,
1516 .ms_kb_base = 0xf0000000,
1517 .serial_base = 0xf1000000,
1518 .nvram_base = 0xf2000000,
1519 .fd_base = 0xf7200000,
1520 .dma_base = 0xf8400000,
1521 .esp_base = 0xf8800000,
1522 .le_base = 0xf8c00000,
1523 .aux1_base = 0xf7400003,
1524 .nvram_machine_id = 0x55,
1525 .machine_id = ss2_id,
1526 .max_mem = 0x10000000,
1527 .default_cpu_model = "Cypress CY7C601",
1528 },
1529};
1530
1531static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1532 qemu_irq *parent_irq)
1533{
1534 DeviceState *dev;
1535 SysBusDevice *s;
1536 unsigned int i;
1537
1538 dev = qdev_create(NULL, "sun4c_intctl");
1539 qdev_init_nofail(dev);
1540
1541 s = sysbus_from_qdev(dev);
1542
1543 for (i = 0; i < MAX_PILS; i++) {
1544 sysbus_connect_irq(s, i, parent_irq[i]);
1545 }
1546 sysbus_mmio_map(s, 0, addr);
1547
1548 return dev;
1549}
1550
1551static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1552 const char *boot_device,
1553 const char *kernel_filename,
1554 const char *kernel_cmdline,
1555 const char *initrd_filename, const char *cpu_model)
1556{
1557 CPUState *env;
1558 void *iommu, *espdma, *ledma, *nvram;
1559 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1560 qemu_irq esp_reset;
1561 qemu_irq fdc_tc;
1562 unsigned long kernel_size;
1563 DriveInfo *fd[MAX_FD];
1564 void *fw_cfg;
1565 DeviceState *dev;
1566 unsigned int i;
1567
1568
1569 if (!cpu_model)
1570 cpu_model = hwdef->default_cpu_model;
1571
1572 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1573
1574
1575 ram_init(0, RAM_size, hwdef->max_mem);
1576
1577 prom_init(hwdef->slavio_base, bios_name);
1578
1579 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1580
1581 for (i = 0; i < 8; i++) {
1582 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1583 }
1584
1585 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1586 slavio_irq[1]);
1587
1588 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1589 iommu, &espdma_irq);
1590
1591 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1592 slavio_irq[3], iommu, &ledma_irq);
1593
1594 if (graphic_depth != 8 && graphic_depth != 24) {
1595 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1596 exit (1);
1597 }
1598 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1599 graphic_depth);
1600
1601 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1602
1603 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1604
1605 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1606 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1607
1608
1609 escc_init(hwdef->serial_base, slavio_irq[1],
1610 slavio_irq[1], serial_hds[0], serial_hds[1],
1611 ESCC_CLOCK, 1);
1612
1613 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1614
1615 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1616
1617 memset(fd, 0, sizeof(fd));
1618 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1619 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1620 &fdc_tc);
1621 }
1622
1623 if (drive_get_max_bus(IF_SCSI) > 0) {
1624 fprintf(stderr, "qemu: too many SCSI bus\n");
1625 exit(1);
1626 }
1627
1628 esp_reset = qdev_get_gpio_in(espdma, 0);
1629 esp_init(hwdef->esp_base, 2,
1630 espdma_memory_read, espdma_memory_write,
1631 espdma, espdma_irq, &esp_reset);
1632
1633 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1634 RAM_size);
1635
1636 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1637 boot_device, RAM_size, kernel_size, graphic_width,
1638 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1639 "Sun4c");
1640
1641 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1642 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1643 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1644 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1645 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1646 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1647 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1648 if (kernel_cmdline) {
1649 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1650 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1651 } else {
1652 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1653 }
1654 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1655 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1656 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1657 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1658}
1659
1660
1661static void ss2_init(ram_addr_t RAM_size,
1662 const char *boot_device,
1663 const char *kernel_filename, const char *kernel_cmdline,
1664 const char *initrd_filename, const char *cpu_model)
1665{
1666 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1667 kernel_cmdline, initrd_filename, cpu_model);
1668}
1669
1670static QEMUMachine ss2_machine = {
1671 .name = "SS-2",
1672 .desc = "Sun4c platform, SPARCstation 2",
1673 .init = ss2_init,
1674 .use_scsi = 1,
1675};
1676
1677static void ss2_machine_init(void)
1678{
1679 qemu_register_machine(&ss5_machine);
1680 qemu_register_machine(&ss10_machine);
1681 qemu_register_machine(&ss600mp_machine);
1682 qemu_register_machine(&ss20_machine);
1683 qemu_register_machine(&voyager_machine);
1684 qemu_register_machine(&ss_lx_machine);
1685 qemu_register_machine(&ss4_machine);
1686 qemu_register_machine(&scls_machine);
1687 qemu_register_machine(&sbook_machine);
1688 qemu_register_machine(&ss1000_machine);
1689 qemu_register_machine(&ss2000_machine);
1690 qemu_register_machine(&ss2_machine);
1691}
1692
1693machine_init(ss2_machine_init);
1694
