LXR qemu/hw/isa

   1/*
   2 * Memory mapped access to ISA IO space.
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "hw.h"
  26#include "isa.h"
  27
  28static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
  29                                  uint32_t val)
  30{
  31    cpu_outb(addr & IOPORTS_MASK, val);
  32}
  33
  34static void isa_mmio_writew_be(void *opaque, target_phys_addr_t addr,
  35                               uint32_t val)
  36{
  37    val = bswap16(val);
  38    cpu_outw(addr & IOPORTS_MASK, val);
  39}
  40
  41static void isa_mmio_writew_le(void *opaque, target_phys_addr_t addr,
  42                               uint32_t val)
  43{
  44    cpu_outw(addr & IOPORTS_MASK, val);
  45}
  46
  47static void isa_mmio_writel_be(void *opaque, target_phys_addr_t addr,
  48                               uint32_t val)
  49{
  50    val = bswap32(val);
  51    cpu_outl(addr & IOPORTS_MASK, val);
  52}
  53
  54static void isa_mmio_writel_le(void *opaque, target_phys_addr_t addr,
  55                               uint32_t val)
  56{
  57    cpu_outl(addr & IOPORTS_MASK, val);
  58}
  59
  60static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
  61{
  62    uint32_t val;
  63
  64    val = cpu_inb(addr & IOPORTS_MASK);
  65    return val;
  66}
  67
  68static uint32_t isa_mmio_readw_be(void *opaque, target_phys_addr_t addr)
  69{
  70    uint32_t val;
  71
  72    val = cpu_inw(addr & IOPORTS_MASK);
  73    val = bswap16(val);
  74    return val;
  75}
  76
  77static uint32_t isa_mmio_readw_le(void *opaque, target_phys_addr_t addr)
  78{
  79    uint32_t val;
  80
  81    val = cpu_inw(addr & IOPORTS_MASK);
  82    return val;
  83}
  84
  85static uint32_t isa_mmio_readl_be(void *opaque, target_phys_addr_t addr)
  86{
  87    uint32_t val;
  88
  89    val = cpu_inl(addr & IOPORTS_MASK);
  90    val = bswap32(val);
  91    return val;
  92}
  93
  94static uint32_t isa_mmio_readl_le(void *opaque, target_phys_addr_t addr)
  95{
  96    uint32_t val;
  97
  98    val = cpu_inl(addr & IOPORTS_MASK);
  99    return val;
 100}
 101
 102static CPUWriteMemoryFunc * const isa_mmio_write_be[] = {
 103    &isa_mmio_writeb,
 104    &isa_mmio_writew_be,
 105    &isa_mmio_writel_be,
 106};
 107
 108static CPUReadMemoryFunc * const isa_mmio_read_be[] = {
 109    &isa_mmio_readb,
 110    &isa_mmio_readw_be,
 111    &isa_mmio_readl_be,
 112};
 113
 114static CPUWriteMemoryFunc * const isa_mmio_write_le[] = {
 115    &isa_mmio_writeb,
 116    &isa_mmio_writew_le,
 117    &isa_mmio_writel_le,
 118};
 119
 120static CPUReadMemoryFunc * const isa_mmio_read_le[] = {
 121    &isa_mmio_readb,
 122    &isa_mmio_readw_le,
 123    &isa_mmio_readl_le,
 124};
 125
 126static int isa_mmio_iomemtype = 0;
 127
 128void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int be)
 129{
 130    if (!isa_mmio_iomemtype) {
 131        if (be) {
 132            isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_be,
 133                                                        isa_mmio_write_be,
 134                                                        NULL);
 135        } else {
 136            isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read_le,
 137                                                        isa_mmio_write_le,
 138                                                        NULL);
 139        }
 140    }
 141    cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
 142}
 143