1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include "hw.h"
26#include "mips.h"
27#include "mips_cpudevs.h"
28#include "pc.h"
29#include "isa.h"
30#include "fdc.h"
31#include "sysemu.h"
32#include "audio/audio.h"
33#include "boards.h"
34#include "net.h"
35#include "esp.h"
36#include "mips-bios.h"
37#include "loader.h"
38#include "mc146818rtc.h"
39
40enum jazz_model_e
41{
42 JAZZ_MAGNUM,
43 JAZZ_PICA61,
44};
45
46static void main_cpu_reset(void *opaque)
47{
48 CPUState *env = opaque;
49 cpu_reset(env);
50}
51
52static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
53{
54 return cpu_inw(0x71);
55}
56
57static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
58{
59 cpu_outw(0x71, val & 0xff);
60}
61
62static CPUReadMemoryFunc * const rtc_read[3] = {
63 rtc_readb,
64 rtc_readb,
65 rtc_readb,
66};
67
68static CPUWriteMemoryFunc * const rtc_write[3] = {
69 rtc_writeb,
70 rtc_writeb,
71 rtc_writeb,
72};
73
74static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
75{
76
77
78}
79
80static CPUReadMemoryFunc * const dma_dummy_read[3] = {
81 NULL,
82 NULL,
83 NULL,
84};
85
86static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
87 dma_dummy_writeb,
88 dma_dummy_writeb,
89 dma_dummy_writeb,
90};
91
92static void audio_init(qemu_irq *pic)
93{
94 struct soundhw *c;
95 int audio_enabled = 0;
96
97 for (c = soundhw; !audio_enabled && c->name; ++c) {
98 audio_enabled = c->enabled;
99 }
100
101 if (audio_enabled) {
102 for (c = soundhw; c->name; ++c) {
103 if (c->enabled) {
104 if (c->isa) {
105 c->init.init_isa(pic);
106 }
107 }
108 }
109 }
110}
111
112#define MAGNUM_BIOS_SIZE_MAX 0x7e000
113#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
114
115static void cpu_request_exit(void *opaque, int irq, int level)
116{
117 CPUState *env = cpu_single_env;
118
119 if (env && level) {
120 cpu_exit(env);
121 }
122}
123
124static
125void mips_jazz_init (ram_addr_t ram_size,
126 const char *cpu_model,
127 enum jazz_model_e jazz_model)
128{
129 char *filename;
130 int bios_size, n;
131 CPUState *env;
132 qemu_irq *rc4030, *i8259;
133 rc4030_dma *dmas;
134 void* rc4030_opaque;
135 int s_rtc, s_dma_dummy;
136 NICInfo *nd;
137 PITState *pit;
138 DriveInfo *fds[MAX_FD];
139 qemu_irq esp_reset;
140 qemu_irq *cpu_exit_irq;
141 ram_addr_t ram_offset;
142 ram_addr_t bios_offset;
143
144
145 if (cpu_model == NULL) {
146#ifdef TARGET_MIPS64
147 cpu_model = "R4000";
148#else
149
150 cpu_model = "24Kf";
151#endif
152 }
153 env = cpu_init(cpu_model);
154 if (!env) {
155 fprintf(stderr, "Unable to find CPU definition\n");
156 exit(1);
157 }
158 qemu_register_reset(main_cpu_reset, env);
159
160
161 ram_offset = qemu_ram_alloc(NULL, "mips_jazz.ram", ram_size);
162 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
163
164 bios_offset = qemu_ram_alloc(NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
165 cpu_register_physical_memory(0x1fc00000LL,
166 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
167 cpu_register_physical_memory(0xfff00000LL,
168 MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
169
170
171 if (bios_name == NULL)
172 bios_name = BIOS_FILENAME;
173 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
174 if (filename) {
175 bios_size = load_image_targphys(filename, 0xfff00000LL,
176 MAGNUM_BIOS_SIZE);
177 qemu_free(filename);
178 } else {
179 bios_size = -1;
180 }
181 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
182 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
183 bios_name);
184 exit(1);
185 }
186
187
188 cpu_mips_irq_init_cpu(env);
189 cpu_mips_clock_init(env);
190
191
192 rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
193 s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
194 cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
195
196
197 i8259 = i8259_init(env->irq[4]);
198 isa_bus_new(NULL);
199 isa_bus_irqs(i8259);
200 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
201 DMA_init(0, cpu_exit_irq);
202 pit = pit_init(0x40, i8259[0]);
203 pcspk_init(pit);
204
205
206#ifdef TARGET_WORDS_BIGENDIAN
207 isa_mmio_init(0x90000000, 0x01000000, 1);
208#else
209 isa_mmio_init(0x90000000, 0x01000000, 0);
210#endif
211
212 isa_mem_base = 0x11000000;
213
214
215 switch (jazz_model) {
216 case JAZZ_MAGNUM:
217 g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
218 break;
219 case JAZZ_PICA61:
220 isa_vga_mm_init(0x40000000, 0x60000000, 0);
221 break;
222 default:
223 break;
224 }
225
226
227 for (n = 0; n < nb_nics; n++) {
228 nd = &nd_table[n];
229 if (!nd->model)
230 nd->model = qemu_strdup("dp83932");
231 if (strcmp(nd->model, "dp83932") == 0) {
232 dp83932_init(nd, 0x80001000, 2, rc4030[4],
233 rc4030_opaque, rc4030_dma_memory_rw);
234 break;
235 } else if (strcmp(nd->model, "?") == 0) {
236 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
237 exit(1);
238 } else {
239 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
240 exit(1);
241 }
242 }
243
244
245 esp_init(0x80002000, 0,
246 rc4030_dma_read, rc4030_dma_write, dmas[0],
247 rc4030[5], &esp_reset);
248
249
250 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
251 fprintf(stderr, "qemu: too many floppy drives\n");
252 exit(1);
253 }
254 for (n = 0; n < MAX_FD; n++) {
255 fds[n] = drive_get(IF_FLOPPY, 0, n);
256 }
257 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
258
259
260 rtc_init(1980, NULL);
261 s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
262 cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
263
264
265 i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
266
267
268 if (serial_hds[0]) {
269#ifdef TARGET_WORDS_BIGENDIAN
270 serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
271#else
272 serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
273#endif
274 }
275 if (serial_hds[1]) {
276#ifdef TARGET_WORDS_BIGENDIAN
277 serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
278#else
279 serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
280#endif
281 }
282
283
284 if (parallel_hds[0])
285 parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
286
287
288
289 audio_init(i8259);
290
291
292 ds1225y_init(0x80009000, "nvram");
293
294
295 jazz_led_init(0x8000f000);
296}
297
298static
299void mips_magnum_init (ram_addr_t ram_size,
300 const char *boot_device,
301 const char *kernel_filename, const char *kernel_cmdline,
302 const char *initrd_filename, const char *cpu_model)
303{
304 mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
305}
306
307static
308void mips_pica61_init (ram_addr_t ram_size,
309 const char *boot_device,
310 const char *kernel_filename, const char *kernel_cmdline,
311 const char *initrd_filename, const char *cpu_model)
312{
313 mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
314}
315
316static QEMUMachine mips_magnum_machine = {
317 .name = "magnum",
318 .desc = "MIPS Magnum",
319 .init = mips_magnum_init,
320 .use_scsi = 1,
321};
322
323static QEMUMachine mips_pica61_machine = {
324 .name = "pica61",
325 .desc = "Acer Pica 61",
326 .init = mips_pica61_init,
327 .use_scsi = 1,
328};
329
330static void mips_jazz_machine_init(void)
331{
332 qemu_register_machine(&mips_magnum_machine);
333 qemu_register_machine(&mips_pica61_machine);
334}
335
336machine_init(mips_jazz_machine_init);
337
