LXR qemu/hw/pci.h

   1#ifndef QEMU_PCI_H
   2#define QEMU_PCI_H
   3
   4#include "qemu-common.h"
   5#include "qobject.h"
   6
   7#include "qdev.h"
   8
   9/* PCI includes legacy ISA access.  */
  10#include "isa.h"
  11
  12/* PCI bus */
  13
  14#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  16#define PCI_FUNC(devfn)         ((devfn) & 0x07)
  17#define PCI_FUNC_MAX            8
  18
  19/* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20#include "pci_ids.h"
  21
  22/* QEMU-specific Vendor and Device ID definitions */
  23
  24/* IBM (0x1014) */
  25#define PCI_DEVICE_ID_IBM_440GX          0x027f
  26#define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28/* Hitachi (0x1054) */
  29#define PCI_VENDOR_ID_HITACHI            0x1054
  30#define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32/* Apple (0x106b) */
  33#define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35#define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37#define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39/* Realtek (0x10ec) */
  40#define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42/* Xilinx (0x10ee) */
  43#define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45/* Marvell (0x11ab) */
  46#define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48/* QEMU/Bochs VGA (0x1234) */
  49#define PCI_VENDOR_ID_QEMU               0x1234
  50#define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52/* VMWare (0x15ad) */
  53#define PCI_VENDOR_ID_VMWARE             0x15ad
  54#define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55#define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56#define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58#define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60/* Intel (0x8086) */
  61#define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62#define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67#define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72#define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74#define FMT_PCIBUS                      PRIx64
  75
  76typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                uint32_t address, uint32_t data, int len);
  78typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                   uint32_t address, int len);
  80typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                pcibus_t addr, pcibus_t size, int type);
  82typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84typedef struct PCIIORegion {
  85    pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87    pcibus_t size;
  88    pcibus_t filtered_size;
  89    uint8_t type;
  90    PCIMapIORegionFunc *map_func;
  91} PCIIORegion;
  92
  93#define PCI_ROM_SLOT 6
  94#define PCI_NUM_REGIONS 7
  95
  96#include "pci_regs.h"
  97
  98/* PCI HEADER_TYPE */
  99#define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 100
 101/* Size of the standard PCI config header */
 102#define PCI_CONFIG_HEADER_SIZE 0x40
 103/* Size of the standard PCI config space */
 104#define PCI_CONFIG_SPACE_SIZE 0x100
 105/* Size of the standart PCIe config space: 4KB */
 106#define PCIE_CONFIG_SPACE_SIZE  0x1000
 107
 108#define PCI_NUM_PINS 4 /* A-D */
 109
 110/* Bits in cap_present field. */
 111enum {
 112    QEMU_PCI_CAP_MSIX = 0x1,
 113    QEMU_PCI_CAP_EXPRESS = 0x2,
 114
 115    /* multifunction capable device */
 116#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        2
 117    QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 118};
 119
 120struct PCIDevice {
 121    DeviceState qdev;
 122    /* PCI config space */
 123    uint8_t *config;
 124
 125    /* Used to enable config checks on load. Note that writeable bits are
 126     * never checked even if set in cmask. */
 127    uint8_t *cmask;
 128
 129    /* Used to implement R/W bytes */
 130    uint8_t *wmask;
 131
 132    /* Used to allocate config space for capabilities. */
 133    uint8_t *used;
 134
 135    /* the following fields are read only */
 136    PCIBus *bus;
 137    uint32_t devfn;
 138    char name[64];
 139    PCIIORegion io_regions[PCI_NUM_REGIONS];
 140
 141    /* do not access the following fields */
 142    PCIConfigReadFunc *config_read;
 143    PCIConfigWriteFunc *config_write;
 144
 145    /* IRQ objects for the INTA-INTD pins.  */
 146    qemu_irq *irq;
 147
 148    /* Current IRQ levels.  Used internally by the generic PCI code.  */
 149    uint8_t irq_state;
 150
 151    /* Capability bits */
 152    uint32_t cap_present;
 153
 154    /* Offset of MSI-X capability in config space */
 155    uint8_t msix_cap;
 156
 157    /* MSI-X entries */
 158    int msix_entries_nr;
 159
 160    /* Space to store MSIX table */
 161    uint8_t *msix_table_page;
 162    /* MMIO index used to map MSIX table and pending bit entries. */
 163    int msix_mmio_index;
 164    /* Reference-count for entries actually in use by driver. */
 165    unsigned *msix_entry_used;
 166    /* Region including the MSI-X table */
 167    uint32_t msix_bar_size;
 168    /* Version id needed for VMState */
 169    int32_t version_id;
 170
 171    /* Location of option rom */
 172    char *romfile;
 173    ram_addr_t rom_offset;
 174    uint32_t rom_bar;
 175};
 176
 177PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 178                               int instance_size, int devfn,
 179                               PCIConfigReadFunc *config_read,
 180                               PCIConfigWriteFunc *config_write);
 181
 182void pci_register_bar(PCIDevice *pci_dev, int region_num,
 183                            pcibus_t size, int type,
 184                            PCIMapIORegionFunc *map_func);
 185
 186int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 187int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
 188                                 uint8_t cap_offset, uint8_t cap_size);
 189
 190void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 191
 192void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 193
 194uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 195
 196
 197uint32_t pci_default_read_config(PCIDevice *d,
 198                                 uint32_t address, int len);
 199void pci_default_write_config(PCIDevice *d,
 200                              uint32_t address, uint32_t val, int len);
 201void pci_device_save(PCIDevice *s, QEMUFile *f);
 202int pci_device_load(PCIDevice *s, QEMUFile *f);
 203
 204typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 205typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 206typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 207void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 208                         const char *name, int devfn_min);
 209PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 210void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 211                  void *irq_opaque, int nirq);
 212void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 213PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 214                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 215                         void *irq_opaque, int devfn_min, int nirq);
 216
 217void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 218
 219PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 220                        const char *default_devaddr);
 221PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 222                               const char *default_devaddr);
 223int pci_bus_num(PCIBus *s);
 224void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 225PCIBus *pci_find_root_bus(int domain);
 226int pci_find_domain(const PCIBus *bus);
 227PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 228PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 229PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 230
 231int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 232                     unsigned *slotp);
 233
 234void do_pci_info_print(Monitor *mon, const QObject *data);
 235void do_pci_info(Monitor *mon, QObject **ret_data);
 236PCIBus *pci_bridge_init(PCIBus *bus, int devfn, bool multifunction,
 237                        uint16_t vid, uint16_t did,
 238                        pci_map_irq_fn map_irq, const char *name);
 239PCIDevice *pci_bridge_get_device(PCIBus *bus);
 240
 241static inline void
 242pci_set_byte(uint8_t *config, uint8_t val)
 243{
 244    *config = val;
 245}
 246
 247static inline uint8_t
 248pci_get_byte(const uint8_t *config)
 249{
 250    return *config;
 251}
 252
 253static inline void
 254pci_set_word(uint8_t *config, uint16_t val)
 255{
 256    cpu_to_le16wu((uint16_t *)config, val);
 257}
 258
 259static inline uint16_t
 260pci_get_word(const uint8_t *config)
 261{
 262    return le16_to_cpupu((const uint16_t *)config);
 263}
 264
 265static inline void
 266pci_set_long(uint8_t *config, uint32_t val)
 267{
 268    cpu_to_le32wu((uint32_t *)config, val);
 269}
 270
 271static inline uint32_t
 272pci_get_long(const uint8_t *config)
 273{
 274    return le32_to_cpupu((const uint32_t *)config);
 275}
 276
 277static inline void
 278pci_set_quad(uint8_t *config, uint64_t val)
 279{
 280    cpu_to_le64w((uint64_t *)config, val);
 281}
 282
 283static inline uint64_t
 284pci_get_quad(const uint8_t *config)
 285{
 286    return le64_to_cpup((const uint64_t *)config);
 287}
 288
 289static inline void
 290pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 291{
 292    pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 293}
 294
 295static inline void
 296pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 297{
 298    pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 299}
 300
 301static inline void
 302pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 303{
 304    pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 305}
 306
 307static inline void
 308pci_config_set_class(uint8_t *pci_config, uint16_t val)
 309{
 310    pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 311}
 312
 313static inline void
 314pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 315{
 316    pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 317}
 318
 319static inline void
 320pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 321{
 322    pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 323}
 324
 325typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 326typedef struct {
 327    DeviceInfo qdev;
 328    pci_qdev_initfn init;
 329    PCIUnregisterFunc *exit;
 330    PCIConfigReadFunc *config_read;
 331    PCIConfigWriteFunc *config_write;
 332
 333    /*
 334     * pci-to-pci bridge or normal device.
 335     * This doesn't mean pci host switch.
 336     * When card bus bridge is supported, this would be enhanced.
 337     */
 338    int is_bridge;
 339
 340    /* pcie stuff */
 341    int is_express;   /* is this device pci express? */
 342
 343    /* rom bar */
 344    const char *romfile;
 345} PCIDeviceInfo;
 346
 347void pci_qdev_register(PCIDeviceInfo *info);
 348void pci_qdev_register_many(PCIDeviceInfo *info);
 349
 350PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 351                                    const char *name);
 352PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 353                                           bool multifunction,
 354                                           const char *name);
 355PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 356PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 357
 358static inline int pci_is_express(const PCIDevice *d)
 359{
 360    return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 361}
 362
 363static inline uint32_t pci_config_size(const PCIDevice *d)
 364{
 365    return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 366}
 367
 368/* These are not pci specific. Should move into a separate header.
 369 * Only pci.c uses them, so keep them here for now.
 370 */
 371
 372/* Get last byte of a range from offset + length.
 373 * Undefined for ranges that wrap around 0. */
 374static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 375{
 376    return offset + len - 1;
 377}
 378
 379/* Check whether a given range covers a given byte. */
 380static inline int range_covers_byte(uint64_t offset, uint64_t len,
 381                                    uint64_t byte)
 382{
 383    return offset <= byte && byte <= range_get_last(offset, len);
 384}
 385
 386/* Check whether 2 given ranges overlap.
 387 * Undefined if ranges that wrap around 0. */
 388static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 389                                 uint64_t first2, uint64_t len2)
 390{
 391    uint64_t last1 = range_get_last(first1, len1);
 392    uint64_t last2 = range_get_last(first2, len2);
 393
 394    return !(last2 < first1 || last1 < first2);
 395}
 396
 397#endif
 398