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19#include <stdarg.h>
20#include <stdlib.h>
21#include <stdio.h>
22#include <string.h>
23#include <inttypes.h>
24#include <signal.h>
25
26#include "cpu.h"
27#include "exec-all.h"
28
29enum {
30 TLBRET_DIRTY = -4,
31 TLBRET_INVALID = -3,
32 TLBRET_NOMATCH = -2,
33 TLBRET_BADADDR = -1,
34 TLBRET_MATCH = 0
35};
36
37#if !defined(CONFIG_USER_ONLY)
38
39
40int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
41 target_ulong address, int rw, int access_type)
42{
43 *physical = address;
44 *prot = PAGE_READ | PAGE_WRITE;
45 return TLBRET_MATCH;
46}
47
48
49int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
50 target_ulong address, int rw, int access_type)
51{
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
55 else
56 *physical = address;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
59 else
60 *physical = address;
61
62 *prot = PAGE_READ | PAGE_WRITE;
63 return TLBRET_MATCH;
64}
65
66
67int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
68 target_ulong address, int rw, int access_type)
69{
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
71 int i;
72
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
79#if defined(TARGET_MIPS64)
80 tag &= env->SEGMask;
81#endif
82
83
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
85
86 int n = !!(address & mask & ~(mask >> 1));
87
88 if (!(n ? tlb->V1 : tlb->V0))
89 return TLBRET_INVALID;
90 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 *physical = tlb->PFN[n] | (address & (mask >> 1));
92 *prot = PAGE_READ;
93 if (n ? tlb->D1 : tlb->D0)
94 *prot |= PAGE_WRITE;
95 return TLBRET_MATCH;
96 }
97 return TLBRET_DIRTY;
98 }
99 }
100 return TLBRET_NOMATCH;
101}
102
103static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
104 int *prot, target_ulong address,
105 int rw, int access_type)
106{
107
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110 int kernel_mode = !user_mode && !supervisor_mode;
111#if defined(TARGET_MIPS64)
112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
115#endif
116 int ret = TLBRET_MATCH;
117
118#if 0
119 qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
120#endif
121
122 if (address <= (int32_t)0x7FFFFFFFUL) {
123
124 if (env->CP0_Status & (1 << CP0St_ERL)) {
125 *physical = address & 0xFFFFFFFF;
126 *prot = PAGE_READ | PAGE_WRITE;
127 } else {
128 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
129 }
130#if defined(TARGET_MIPS64)
131 } else if (address < 0x4000000000000000ULL) {
132
133 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
134 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
135 } else {
136 ret = TLBRET_BADADDR;
137 }
138 } else if (address < 0x8000000000000000ULL) {
139
140 if ((supervisor_mode || kernel_mode) &&
141 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
142 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
143 } else {
144 ret = TLBRET_BADADDR;
145 }
146 } else if (address < 0xC000000000000000ULL) {
147
148 if (kernel_mode && KX &&
149 (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
150 *physical = address & env->PAMask;
151 *prot = PAGE_READ | PAGE_WRITE;
152 } else {
153 ret = TLBRET_BADADDR;
154 }
155 } else if (address < 0xFFFFFFFF80000000ULL) {
156
157 if (kernel_mode && KX &&
158 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
159 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
160 } else {
161 ret = TLBRET_BADADDR;
162 }
163#endif
164 } else if (address < (int32_t)0xA0000000UL) {
165
166 if (kernel_mode) {
167 *physical = address - (int32_t)0x80000000UL;
168 *prot = PAGE_READ | PAGE_WRITE;
169 } else {
170 ret = TLBRET_BADADDR;
171 }
172 } else if (address < (int32_t)0xC0000000UL) {
173
174 if (kernel_mode) {
175 *physical = address - (int32_t)0xA0000000UL;
176 *prot = PAGE_READ | PAGE_WRITE;
177 } else {
178 ret = TLBRET_BADADDR;
179 }
180 } else if (address < (int32_t)0xE0000000UL) {
181
182 if (supervisor_mode || kernel_mode) {
183 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
184 } else {
185 ret = TLBRET_BADADDR;
186 }
187 } else {
188
189
190 if (kernel_mode) {
191 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
192 } else {
193 ret = TLBRET_BADADDR;
194 }
195 }
196#if 0
197 qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
198 address, rw, access_type, *physical, *prot, ret);
199#endif
200
201 return ret;
202}
203#endif
204
205static void raise_mmu_exception(CPUState *env, target_ulong address,
206 int rw, int tlb_error)
207{
208 int exception = 0, error_code = 0;
209
210 switch (tlb_error) {
211 default:
212 case TLBRET_BADADDR:
213
214
215 if (rw)
216 exception = EXCP_AdES;
217 else
218 exception = EXCP_AdEL;
219 break;
220 case TLBRET_NOMATCH:
221
222 if (rw)
223 exception = EXCP_TLBS;
224 else
225 exception = EXCP_TLBL;
226 error_code = 1;
227 break;
228 case TLBRET_INVALID:
229
230 if (rw)
231 exception = EXCP_TLBS;
232 else
233 exception = EXCP_TLBL;
234 break;
235 case TLBRET_DIRTY:
236
237 exception = EXCP_LTLBL;
238 break;
239
240 }
241
242 env->CP0_BadVAddr = address;
243 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
244 ((address >> 9) & 0x007ffff0);
245 env->CP0_EntryHi =
246 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
247#if defined(TARGET_MIPS64)
248 env->CP0_EntryHi &= env->SEGMask;
249 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
250 ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
251 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
252#endif
253 env->exception_index = exception;
254 env->error_code = error_code;
255}
256
257#if !defined(CONFIG_USER_ONLY)
258target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
259{
260 target_phys_addr_t phys_addr;
261 int prot;
262
263 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
264 return -1;
265 return phys_addr;
266}
267#endif
268
269int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
270 int mmu_idx, int is_softmmu)
271{
272#if !defined(CONFIG_USER_ONLY)
273 target_phys_addr_t physical;
274 int prot;
275#endif
276 int access_type;
277 int ret = 0;
278
279#if 0
280 log_cpu_state(env, 0);
281#endif
282 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
283 __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
284
285 rw &= 1;
286
287
288
289
290 access_type = ACCESS_INT;
291#if defined(CONFIG_USER_ONLY)
292 ret = TLBRET_NOMATCH;
293#else
294 ret = get_physical_address(env, &physical, &prot,
295 address, rw, access_type);
296 qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
297 __func__, address, ret, physical, prot);
298 if (ret == TLBRET_MATCH) {
299 tlb_set_page(env, address & TARGET_PAGE_MASK,
300 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
301 mmu_idx, TARGET_PAGE_SIZE);
302 ret = 0;
303 } else if (ret < 0)
304#endif
305 {
306 raise_mmu_exception(env, address, rw, ret);
307 ret = 1;
308 }
309
310 return ret;
311}
312
313#if !defined(CONFIG_USER_ONLY)
314target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
315{
316 target_phys_addr_t physical;
317 int prot;
318 int access_type;
319 int ret = 0;
320
321 rw &= 1;
322
323
324 access_type = ACCESS_INT;
325 ret = get_physical_address(env, &physical, &prot,
326 address, rw, access_type);
327 if (ret != TLBRET_MATCH) {
328 raise_mmu_exception(env, address, rw, ret);
329 return -1LL;
330 } else {
331 return physical;
332 }
333}
334#endif
335
336static const char * const excp_names[EXCP_LAST + 1] = {
337 [EXCP_RESET] = "reset",
338 [EXCP_SRESET] = "soft reset",
339 [EXCP_DSS] = "debug single step",
340 [EXCP_DINT] = "debug interrupt",
341 [EXCP_NMI] = "non-maskable interrupt",
342 [EXCP_MCHECK] = "machine check",
343 [EXCP_EXT_INTERRUPT] = "interrupt",
344 [EXCP_DFWATCH] = "deferred watchpoint",
345 [EXCP_DIB] = "debug instruction breakpoint",
346 [EXCP_IWATCH] = "instruction fetch watchpoint",
347 [EXCP_AdEL] = "address error load",
348 [EXCP_AdES] = "address error store",
349 [EXCP_TLBF] = "TLB refill",
350 [EXCP_IBE] = "instruction bus error",
351 [EXCP_DBp] = "debug breakpoint",
352 [EXCP_SYSCALL] = "syscall",
353 [EXCP_BREAK] = "break",
354 [EXCP_CpU] = "coprocessor unusable",
355 [EXCP_RI] = "reserved instruction",
356 [EXCP_OVERFLOW] = "arithmetic overflow",
357 [EXCP_TRAP] = "trap",
358 [EXCP_FPE] = "floating point",
359 [EXCP_DDBS] = "debug data break store",
360 [EXCP_DWATCH] = "data watchpoint",
361 [EXCP_LTLBL] = "TLB modify",
362 [EXCP_TLBL] = "TLB load",
363 [EXCP_TLBS] = "TLB store",
364 [EXCP_DBE] = "data bus error",
365 [EXCP_DDBL] = "debug data break load",
366 [EXCP_THREAD] = "thread",
367 [EXCP_MDMX] = "MDMX",
368 [EXCP_C2E] = "precise coprocessor 2",
369 [EXCP_CACHE] = "cache error",
370};
371
372#if !defined(CONFIG_USER_ONLY)
373static target_ulong exception_resume_pc (CPUState *env)
374{
375 target_ulong bad_pc;
376 target_ulong isa_mode;
377
378 isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
379 bad_pc = env->active_tc.PC | isa_mode;
380 if (env->hflags & MIPS_HFLAG_BMASK) {
381
382
383 bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
384 }
385
386 return bad_pc;
387}
388
389static void set_hflags_for_handler (CPUState *env)
390{
391
392 env->hflags &= ~(MIPS_HFLAG_M16);
393
394 if (env->insn_flags & ASE_MICROMIPS) {
395 env->hflags |= (!!(env->CP0_Config3
396 & (1 << CP0C3_ISA_ON_EXC))
397 << MIPS_HFLAG_M16_SHIFT);
398 }
399}
400#endif
401
402void do_interrupt (CPUState *env)
403{
404#if !defined(CONFIG_USER_ONLY)
405 target_ulong offset;
406 int cause = -1;
407 const char *name;
408
409 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
410 if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
411 name = "unknown";
412 else
413 name = excp_names[env->exception_index];
414
415 qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
416 __func__, env->active_tc.PC, env->CP0_EPC, name);
417 }
418 if (env->exception_index == EXCP_EXT_INTERRUPT &&
419 (env->hflags & MIPS_HFLAG_DM))
420 env->exception_index = EXCP_DINT;
421 offset = 0x180;
422 switch (env->exception_index) {
423 case EXCP_DSS:
424 env->CP0_Debug |= 1 << CP0DB_DSS;
425
426
427
428
429 env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
430 goto enter_debug_mode;
431 case EXCP_DINT:
432 env->CP0_Debug |= 1 << CP0DB_DINT;
433 goto set_DEPC;
434 case EXCP_DIB:
435 env->CP0_Debug |= 1 << CP0DB_DIB;
436 goto set_DEPC;
437 case EXCP_DBp:
438 env->CP0_Debug |= 1 << CP0DB_DBp;
439 goto set_DEPC;
440 case EXCP_DDBS:
441 env->CP0_Debug |= 1 << CP0DB_DDBS;
442 goto set_DEPC;
443 case EXCP_DDBL:
444 env->CP0_Debug |= 1 << CP0DB_DDBL;
445 set_DEPC:
446 env->CP0_DEPC = exception_resume_pc(env);
447 env->hflags &= ~MIPS_HFLAG_BMASK;
448 enter_debug_mode:
449 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
450 env->hflags &= ~(MIPS_HFLAG_KSU);
451
452 if (!(env->CP0_Status & (1 << CP0St_EXL)))
453 env->CP0_Cause &= ~(1 << CP0Ca_BD);
454 env->active_tc.PC = (int32_t)0xBFC00480;
455 set_hflags_for_handler(env);
456 break;
457 case EXCP_RESET:
458 cpu_reset(env);
459 break;
460 case EXCP_SRESET:
461 env->CP0_Status |= (1 << CP0St_SR);
462 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
463 goto set_error_EPC;
464 case EXCP_NMI:
465 env->CP0_Status |= (1 << CP0St_NMI);
466 set_error_EPC:
467 env->CP0_ErrorEPC = exception_resume_pc(env);
468 env->hflags &= ~MIPS_HFLAG_BMASK;
469 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
470 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
471 env->hflags &= ~(MIPS_HFLAG_KSU);
472 if (!(env->CP0_Status & (1 << CP0St_EXL)))
473 env->CP0_Cause &= ~(1 << CP0Ca_BD);
474 env->active_tc.PC = (int32_t)0xBFC00000;
475 set_hflags_for_handler(env);
476 break;
477 case EXCP_EXT_INTERRUPT:
478 cause = 0;
479 if (env->CP0_Cause & (1 << CP0Ca_IV))
480 offset = 0x200;
481 goto set_EPC;
482 case EXCP_LTLBL:
483 cause = 1;
484 goto set_EPC;
485 case EXCP_TLBL:
486 cause = 2;
487 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
488#if defined(TARGET_MIPS64)
489 int R = env->CP0_BadVAddr >> 62;
490 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
491 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
492 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
493
494 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
495 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
496 offset = 0x080;
497 else
498#endif
499 offset = 0x000;
500 }
501 goto set_EPC;
502 case EXCP_TLBS:
503 cause = 3;
504 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
505#if defined(TARGET_MIPS64)
506 int R = env->CP0_BadVAddr >> 62;
507 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
508 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
509 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
510
511 if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
512 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
513 offset = 0x080;
514 else
515#endif
516 offset = 0x000;
517 }
518 goto set_EPC;
519 case EXCP_AdEL:
520 cause = 4;
521 goto set_EPC;
522 case EXCP_AdES:
523 cause = 5;
524 goto set_EPC;
525 case EXCP_IBE:
526 cause = 6;
527 goto set_EPC;
528 case EXCP_DBE:
529 cause = 7;
530 goto set_EPC;
531 case EXCP_SYSCALL:
532 cause = 8;
533 goto set_EPC;
534 case EXCP_BREAK:
535 cause = 9;
536 goto set_EPC;
537 case EXCP_RI:
538 cause = 10;
539 goto set_EPC;
540 case EXCP_CpU:
541 cause = 11;
542 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
543 (env->error_code << CP0Ca_CE);
544 goto set_EPC;
545 case EXCP_OVERFLOW:
546 cause = 12;
547 goto set_EPC;
548 case EXCP_TRAP:
549 cause = 13;
550 goto set_EPC;
551 case EXCP_FPE:
552 cause = 15;
553 goto set_EPC;
554 case EXCP_C2E:
555 cause = 18;
556 goto set_EPC;
557 case EXCP_MDMX:
558 cause = 22;
559 goto set_EPC;
560 case EXCP_DWATCH:
561 cause = 23;
562
563 goto set_EPC;
564 case EXCP_MCHECK:
565 cause = 24;
566 goto set_EPC;
567 case EXCP_THREAD:
568 cause = 25;
569 goto set_EPC;
570 case EXCP_CACHE:
571 cause = 30;
572 if (env->CP0_Status & (1 << CP0St_BEV)) {
573 offset = 0x100;
574 } else {
575 offset = 0x20000100;
576 }
577 set_EPC:
578 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
579 env->CP0_EPC = exception_resume_pc(env);
580 if (env->hflags & MIPS_HFLAG_BMASK) {
581 env->CP0_Cause |= (1 << CP0Ca_BD);
582 } else {
583 env->CP0_Cause &= ~(1 << CP0Ca_BD);
584 }
585 env->CP0_Status |= (1 << CP0St_EXL);
586 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
587 env->hflags &= ~(MIPS_HFLAG_KSU);
588 }
589 env->hflags &= ~MIPS_HFLAG_BMASK;
590 if (env->CP0_Status & (1 << CP0St_BEV)) {
591 env->active_tc.PC = (int32_t)0xBFC00200;
592 } else {
593 env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
594 }
595 env->active_tc.PC += offset;
596 set_hflags_for_handler(env);
597 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
598 break;
599 default:
600 qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
601 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
602 exit(1);
603 }
604 if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
605 qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
606 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
607 __func__, env->active_tc.PC, env->CP0_EPC, cause,
608 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
609 env->CP0_DEPC);
610 }
611#endif
612 env->exception_index = EXCP_NONE;
613}
614
615#if !defined(CONFIG_USER_ONLY)
616void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
617{
618 r4k_tlb_t *tlb;
619 target_ulong addr;
620 target_ulong end;
621 uint8_t ASID = env->CP0_EntryHi & 0xFF;
622 target_ulong mask;
623
624 tlb = &env->tlb->mmu.r4k.tlb[idx];
625
626
627 if (tlb->G == 0 && tlb->ASID != ASID) {
628 return;
629 }
630
631 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
632
633
634
635 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
636 env->tlb->tlb_in_use++;
637 return;
638 }
639
640
641 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
642 if (tlb->V0) {
643 addr = tlb->VPN & ~mask;
644#if defined(TARGET_MIPS64)
645 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
646 addr |= 0x3FFFFF0000000000ULL;
647 }
648#endif
649 end = addr | (mask >> 1);
650 while (addr < end) {
651 tlb_flush_page (env, addr);
652 addr += TARGET_PAGE_SIZE;
653 }
654 }
655 if (tlb->V1) {
656 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
657#if defined(TARGET_MIPS64)
658 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
659 addr |= 0x3FFFFF0000000000ULL;
660 }
661#endif
662 end = addr | mask;
663 while (addr - 1 < end) {
664 tlb_flush_page (env, addr);
665 addr += TARGET_PAGE_SIZE;
666 }
667 }
668}
669#endif
670
