LXR qemu/hw/ide/mmio.c

   1/*
   2 * QEMU IDE Emulation: mmio support (for embedded).
   3 *
   4 * Copyright (c) 2003 Fabrice Bellard
   5 * Copyright (c) 2006 Openedhand Ltd.
   6 *
   7 * Permission is hereby granted, free of charge, to any person obtaining a copy
   8 * of this software and associated documentation files (the "Software"), to deal
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23 * THE SOFTWARE.
  24 */
  25#include <hw/hw.h>
  26#include "block.h"
  27#include "block_int.h"
  28#include "sysemu.h"
  29#include "dma.h"
  30
  31#include <hw/ide/internal.h>
  32
  33/***********************************************************/
  34/* MMIO based ide port
  35 * This emulates IDE device connected directly to the CPU bus without
  36 * dedicated ide controller, which is often seen on embedded boards.
  37 */
  38
  39typedef struct {
  40    IDEBus bus;
  41    int shift;
  42} MMIOState;
  43
  44static void mmio_ide_reset(void *opaque)
  45{
  46    MMIOState *s = opaque;
  47
  48    ide_bus_reset(&s->bus);
  49}
  50
  51static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
  52{
  53    MMIOState *s = opaque;
  54    addr >>= s->shift;
  55    if (addr & 7)
  56        return ide_ioport_read(&s->bus, addr);
  57    else
  58        return ide_data_readw(&s->bus, 0);
  59}
  60
  61static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
  62        uint32_t val)
  63{
  64    MMIOState *s = opaque;
  65    addr >>= s->shift;
  66    if (addr & 7)
  67        ide_ioport_write(&s->bus, addr, val);
  68    else
  69        ide_data_writew(&s->bus, 0, val);
  70}
  71
  72static CPUReadMemoryFunc * const mmio_ide_reads[] = {
  73    mmio_ide_read,
  74    mmio_ide_read,
  75    mmio_ide_read,
  76};
  77
  78static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
  79    mmio_ide_write,
  80    mmio_ide_write,
  81    mmio_ide_write,
  82};
  83
  84static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
  85{
  86    MMIOState *s= opaque;
  87    return ide_status_read(&s->bus, 0);
  88}
  89
  90static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
  91        uint32_t val)
  92{
  93    MMIOState *s = opaque;
  94    ide_cmd_write(&s->bus, 0, val);
  95}
  96
  97static CPUReadMemoryFunc * const mmio_ide_status[] = {
  98    mmio_ide_status_read,
  99    mmio_ide_status_read,
 100    mmio_ide_status_read,
 101};
 102
 103static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
 104    mmio_ide_cmd_write,
 105    mmio_ide_cmd_write,
 106    mmio_ide_cmd_write,
 107};
 108
 109static const VMStateDescription vmstate_ide_mmio = {
 110    .name = "mmio-ide",
 111    .version_id = 3,
 112    .minimum_version_id = 0,
 113    .minimum_version_id_old = 0,
 114    .fields      = (VMStateField []) {
 115        VMSTATE_IDE_BUS(bus, MMIOState),
 116        VMSTATE_IDE_DRIVES(bus.ifs, MMIOState),
 117        VMSTATE_END_OF_LIST()
 118    }
 119};
 120
 121void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
 122                    qemu_irq irq, int shift,
 123                    DriveInfo *hd0, DriveInfo *hd1)
 124{
 125    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
 126    int mem1, mem2;
 127
 128    ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq);
 129
 130    s->shift = shift;
 131
 132    mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s,
 133                                  DEVICE_NATIVE_ENDIAN);
 134    mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s,
 135                                  DEVICE_NATIVE_ENDIAN);
 136    cpu_register_physical_memory(membase, 16 << shift, mem1);
 137    cpu_register_physical_memory(membase2, 2 << shift, mem2);
 138    vmstate_register(NULL, 0, &vmstate_ide_mmio, s);
 139    qemu_register_reset(mmio_ide_reset, s);
 140}
 141
 142