LXR qemu/hw/isa

   1/*
   2 * Memory mapped access to ISA IO space.
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "hw.h"
  26#include "isa.h"
  27
  28static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
  29                                  uint32_t val)
  30{
  31    cpu_outb(addr & IOPORTS_MASK, val);
  32}
  33
  34static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
  35                               uint32_t val)
  36{
  37    cpu_outw(addr & IOPORTS_MASK, val);
  38}
  39
  40static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
  41                               uint32_t val)
  42{
  43    cpu_outl(addr & IOPORTS_MASK, val);
  44}
  45
  46static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
  47{
  48    return cpu_inb(addr & IOPORTS_MASK);
  49}
  50
  51static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
  52{
  53    return cpu_inw(addr & IOPORTS_MASK);
  54}
  55
  56static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
  57{
  58    return cpu_inl(addr & IOPORTS_MASK);
  59}
  60
  61static CPUWriteMemoryFunc * const isa_mmio_write[] = {
  62    &isa_mmio_writeb,
  63    &isa_mmio_writew,
  64    &isa_mmio_writel,
  65};
  66
  67static CPUReadMemoryFunc * const isa_mmio_read[] = {
  68    &isa_mmio_readb,
  69    &isa_mmio_readw,
  70    &isa_mmio_readl,
  71};
  72
  73void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
  74{
  75    int isa_mmio_iomemtype;
  76
  77    isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read,
  78                                                isa_mmio_write,
  79                                                NULL,
  80                                                DEVICE_LITTLE_ENDIAN);
  81    cpu_register_physical_memory(base, size, isa_mmio_iomemtype);
  82}
  83