LXR qemu/hw/pxa.h

   1/*
   2 * Intel XScale PXA255/270 processor support.
   3 *
   4 * Copyright (c) 2006 Openedhand Ltd.
   5 * Written by Andrzej Zaborowski <balrog@zabor.org>
   6 *
   7 * This code is licenced under the GNU GPL v2.
   8 */
   9#ifndef PXA_H
  10# define PXA_H                  "pxa.h"
  11
  12/* Interrupt numbers */
  13# define PXA2XX_PIC_SSP3        0
  14# define PXA2XX_PIC_USBH2       2
  15# define PXA2XX_PIC_USBH1       3
  16# define PXA2XX_PIC_KEYPAD      4
  17# define PXA2XX_PIC_PWRI2C      6
  18# define PXA25X_PIC_HWUART      7
  19# define PXA27X_PIC_OST_4_11    7
  20# define PXA2XX_PIC_GPIO_0      8
  21# define PXA2XX_PIC_GPIO_1      9
  22# define PXA2XX_PIC_GPIO_X      10
  23# define PXA2XX_PIC_I2S         13
  24# define PXA26X_PIC_ASSP        15
  25# define PXA25X_PIC_NSSP        16
  26# define PXA27X_PIC_SSP2        16
  27# define PXA2XX_PIC_LCD         17
  28# define PXA2XX_PIC_I2C         18
  29# define PXA2XX_PIC_ICP         19
  30# define PXA2XX_PIC_STUART      20
  31# define PXA2XX_PIC_BTUART      21
  32# define PXA2XX_PIC_FFUART      22
  33# define PXA2XX_PIC_MMC         23
  34# define PXA2XX_PIC_SSP         24
  35# define PXA2XX_PIC_DMA         25
  36# define PXA2XX_PIC_OST_0       26
  37# define PXA2XX_PIC_RTC1HZ      30
  38# define PXA2XX_PIC_RTCALARM    31
  39
  40/* DMA requests */
  41# define PXA2XX_RX_RQ_I2S       2
  42# define PXA2XX_TX_RQ_I2S       3
  43# define PXA2XX_RX_RQ_BTUART    4
  44# define PXA2XX_TX_RQ_BTUART    5
  45# define PXA2XX_RX_RQ_FFUART    6
  46# define PXA2XX_TX_RQ_FFUART    7
  47# define PXA2XX_RX_RQ_SSP1      13
  48# define PXA2XX_TX_RQ_SSP1      14
  49# define PXA2XX_RX_RQ_SSP2      15
  50# define PXA2XX_TX_RQ_SSP2      16
  51# define PXA2XX_RX_RQ_ICP       17
  52# define PXA2XX_TX_RQ_ICP       18
  53# define PXA2XX_RX_RQ_STUART    19
  54# define PXA2XX_TX_RQ_STUART    20
  55# define PXA2XX_RX_RQ_MMCI      21
  56# define PXA2XX_TX_RQ_MMCI      22
  57# define PXA2XX_USB_RQ(x)       ((x) + 24)
  58# define PXA2XX_RX_RQ_SSP3      66
  59# define PXA2XX_TX_RQ_SSP3      67
  60
  61# define PXA2XX_SDRAM_BASE      0xa0000000
  62# define PXA2XX_INTERNAL_BASE   0x5c000000
  63# define PXA2XX_INTERNAL_SIZE   0x40000
  64
  65/* pxa2xx_pic.c */
  66qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
  67
  68/* pxa2xx_timer.c */
  69void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
  70void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
  71
  72/* pxa2xx_gpio.c */
  73DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
  74                CPUState *env, qemu_irq *pic, int lines);
  75void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
  76
  77/* pxa2xx_dma.c */
  78typedef struct PXA2xxDMAState PXA2xxDMAState;
  79PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
  80                qemu_irq irq);
  81PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
  82                qemu_irq irq);
  83void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
  84
  85/* pxa2xx_lcd.c */
  86typedef struct PXA2xxLCDState PXA2xxLCDState;
  87PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
  88                qemu_irq irq);
  89void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
  90void pxa2xx_lcdc_oritentation(void *opaque, int angle);
  91
  92/* pxa2xx_mmci.c */
  93typedef struct PXA2xxMMCIState PXA2xxMMCIState;
  94PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
  95                BlockDriverState *bd, qemu_irq irq, void *dma);
  96void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
  97                qemu_irq coverswitch);
  98
  99/* pxa2xx_pcmcia.c */
 100typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
 101PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
 102int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
 103int pxa2xx_pcmcia_dettach(void *opaque);
 104void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
 105
 106/* pxa2xx_keypad.c */
 107struct  keymap {
 108    int column;
 109    int row;
 110};
 111typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
 112PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
 113                qemu_irq irq);
 114void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
 115                int size);
 116
 117/* pxa2xx.c */
 118typedef struct PXA2xxI2CState PXA2xxI2CState;
 119PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
 120                qemu_irq irq, uint32_t page_size);
 121i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
 122
 123typedef struct PXA2xxI2SState PXA2xxI2SState;
 124typedef struct PXA2xxFIrState PXA2xxFIrState;
 125
 126typedef struct {
 127    CPUState *env;
 128    qemu_irq *pic;
 129    qemu_irq reset;
 130    PXA2xxDMAState *dma;
 131    DeviceState *gpio;
 132    PXA2xxLCDState *lcd;
 133    SSIBus **ssp;
 134    PXA2xxI2CState *i2c[2];
 135    PXA2xxMMCIState *mmc;
 136    PXA2xxPCMCIAState *pcmcia[2];
 137    PXA2xxI2SState *i2s;
 138    PXA2xxFIrState *fir;
 139    PXA2xxKeyPadState *kp;
 140
 141    /* Power management */
 142    target_phys_addr_t pm_base;
 143    uint32_t pm_regs[0x40];
 144
 145    /* Clock management */
 146    target_phys_addr_t cm_base;
 147    uint32_t cm_regs[4];
 148    uint32_t clkcfg;
 149
 150    /* Memory management */
 151    target_phys_addr_t mm_base;
 152    uint32_t mm_regs[0x1a];
 153
 154    /* Performance monitoring */
 155    uint32_t pmnc;
 156
 157    /* Real-Time clock */
 158    target_phys_addr_t rtc_base;
 159    uint32_t rttr;
 160    uint32_t rtsr;
 161    uint32_t rtar;
 162    uint32_t rdar1;
 163    uint32_t rdar2;
 164    uint32_t ryar1;
 165    uint32_t ryar2;
 166    uint32_t swar1;
 167    uint32_t swar2;
 168    uint32_t piar;
 169    uint32_t last_rcnr;
 170    uint32_t last_rdcr;
 171    uint32_t last_rycr;
 172    uint32_t last_swcr;
 173    uint32_t last_rtcpicr;
 174    int64_t last_hz;
 175    int64_t last_sw;
 176    int64_t last_pi;
 177    QEMUTimer *rtc_hz;
 178    QEMUTimer *rtc_rdal1;
 179    QEMUTimer *rtc_rdal2;
 180    QEMUTimer *rtc_swal1;
 181    QEMUTimer *rtc_swal2;
 182    QEMUTimer *rtc_pi;
 183} PXA2xxState;
 184
 185struct PXA2xxI2SState {
 186    qemu_irq irq;
 187    PXA2xxDMAState *dma;
 188    void (*data_req)(void *, int, int);
 189
 190    uint32_t control[2];
 191    uint32_t status;
 192    uint32_t mask;
 193    uint32_t clk;
 194
 195    int enable;
 196    int rx_len;
 197    int tx_len;
 198    void (*codec_out)(void *, uint32_t);
 199    uint32_t (*codec_in)(void *);
 200    void *opaque;
 201
 202    int fifo_len;
 203    uint32_t fifo[16];
 204};
 205
 206# define PA_FMT                 "0x%08lx"
 207# define REG_FMT                "0x" TARGET_FMT_plx
 208
 209PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
 210PXA2xxState *pxa255_init(unsigned int sdram_size);
 211
 212#endif  /* PXA_H */
 213