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18#include "hw.h"
19#include "pxa.h"
20#include "sharpsl.h"
21#include "sysbus.h"
22
23#undef REG_FMT
24#define REG_FMT "0x%02lx"
25
26
27
28typedef struct ScoopInfo ScoopInfo;
29struct ScoopInfo {
30 SysBusDevice busdev;
31 qemu_irq handler[16];
32 uint16_t status;
33 uint16_t power;
34 uint32_t gpio_level;
35 uint32_t gpio_dir;
36 uint32_t prev_level;
37
38 uint16_t mcr;
39 uint16_t cdr;
40 uint16_t ccr;
41 uint16_t irr;
42 uint16_t imr;
43 uint16_t isr;
44};
45
46#define SCOOP_MCR 0x00
47#define SCOOP_CDR 0x04
48#define SCOOP_CSR 0x08
49#define SCOOP_CPR 0x0c
50#define SCOOP_CCR 0x10
51#define SCOOP_IRR_IRM 0x14
52#define SCOOP_IMR 0x18
53#define SCOOP_ISR 0x1c
54#define SCOOP_GPCR 0x20
55#define SCOOP_GPWR 0x24
56#define SCOOP_GPRR 0x28
57
58static inline void scoop_gpio_handler_update(ScoopInfo *s) {
59 uint32_t level, diff;
60 int bit;
61 level = s->gpio_level & s->gpio_dir;
62
63 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
64 bit = ffs(diff) - 1;
65 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
66 }
67
68 s->prev_level = level;
69}
70
71static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
72{
73 ScoopInfo *s = (ScoopInfo *) opaque;
74
75 switch (addr & 0x3f) {
76 case SCOOP_MCR:
77 return s->mcr;
78 case SCOOP_CDR:
79 return s->cdr;
80 case SCOOP_CSR:
81 return s->status;
82 case SCOOP_CPR:
83 return s->power;
84 case SCOOP_CCR:
85 return s->ccr;
86 case SCOOP_IRR_IRM:
87 return s->irr;
88 case SCOOP_IMR:
89 return s->imr;
90 case SCOOP_ISR:
91 return s->isr;
92 case SCOOP_GPCR:
93 return s->gpio_dir;
94 case SCOOP_GPWR:
95 case SCOOP_GPRR:
96 return s->gpio_level;
97 default:
98 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
99 }
100
101 return 0;
102}
103
104static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
105{
106 ScoopInfo *s = (ScoopInfo *) opaque;
107 value &= 0xffff;
108
109 switch (addr & 0x3f) {
110 case SCOOP_MCR:
111 s->mcr = value;
112 break;
113 case SCOOP_CDR:
114 s->cdr = value;
115 break;
116 case SCOOP_CPR:
117 s->power = value;
118 if (value & 0x80)
119 s->power |= 0x8040;
120 break;
121 case SCOOP_CCR:
122 s->ccr = value;
123 break;
124 case SCOOP_IRR_IRM:
125 s->irr = value;
126 break;
127 case SCOOP_IMR:
128 s->imr = value;
129 break;
130 case SCOOP_ISR:
131 s->isr = value;
132 break;
133 case SCOOP_GPCR:
134 s->gpio_dir = value;
135 scoop_gpio_handler_update(s);
136 break;
137 case SCOOP_GPWR:
138 case SCOOP_GPRR:
139 s->gpio_level = value & s->gpio_dir;
140 scoop_gpio_handler_update(s);
141 break;
142 default:
143 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
144 }
145}
146
147static CPUReadMemoryFunc * const scoop_readfn[] = {
148 scoop_readb,
149 scoop_readb,
150 scoop_readb,
151};
152static CPUWriteMemoryFunc * const scoop_writefn[] = {
153 scoop_writeb,
154 scoop_writeb,
155 scoop_writeb,
156};
157
158static void scoop_gpio_set(void *opaque, int line, int level)
159{
160 ScoopInfo *s = (ScoopInfo *) opaque;
161
162 if (level)
163 s->gpio_level |= (1 << line);
164 else
165 s->gpio_level &= ~(1 << line);
166}
167
168static int scoop_init(SysBusDevice *dev)
169{
170 ScoopInfo *s = FROM_SYSBUS(ScoopInfo, dev);
171 int iomemtype;
172
173 s->status = 0x02;
174 qdev_init_gpio_out(&s->busdev.qdev, s->handler, 16);
175 qdev_init_gpio_in(&s->busdev.qdev, scoop_gpio_set, 16);
176 iomemtype = cpu_register_io_memory(scoop_readfn,
177 scoop_writefn, s, DEVICE_NATIVE_ENDIAN);
178
179 sysbus_init_mmio(dev, 0x1000, iomemtype);
180
181 return 0;
182}
183
184static bool is_version_0 (void *opaque, int version_id)
185{
186 return version_id == 0;
187}
188
189
190static const VMStateDescription vmstate_scoop_regs = {
191 .name = "scoop",
192 .version_id = 1,
193 .minimum_version_id = 0,
194 .minimum_version_id_old = 0,
195 .fields = (VMStateField []) {
196 VMSTATE_UINT16(status, ScoopInfo),
197 VMSTATE_UINT16(power, ScoopInfo),
198 VMSTATE_UINT32(gpio_level, ScoopInfo),
199 VMSTATE_UINT32(gpio_dir, ScoopInfo),
200 VMSTATE_UINT32(prev_level, ScoopInfo),
201 VMSTATE_UINT16(mcr, ScoopInfo),
202 VMSTATE_UINT16(cdr, ScoopInfo),
203 VMSTATE_UINT16(ccr, ScoopInfo),
204 VMSTATE_UINT16(irr, ScoopInfo),
205 VMSTATE_UINT16(imr, ScoopInfo),
206 VMSTATE_UINT16(isr, ScoopInfo),
207 VMSTATE_UNUSED_TEST(is_version_0, 2),
208 VMSTATE_END_OF_LIST(),
209 },
210};
211
212static SysBusDeviceInfo scoop_sysbus_info = {
213 .init = scoop_init,
214 .qdev.name = "scoop",
215 .qdev.desc = "Scoop2 Sharp custom ASIC",
216 .qdev.size = sizeof(ScoopInfo),
217 .qdev.vmsd = &vmstate_scoop_regs,
218 .qdev.props = (Property[]) {
219 DEFINE_PROP_END_OF_LIST(),
220 }
221};
222
223static void scoop_register(void)
224{
225 sysbus_register_withprop(&scoop_sysbus_info);
226}
227device_init(scoop_register);
228
229
230
231#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
232
233static struct __attribute__ ((__packed__)) sl_param_info {
234 uint32_t comadj_keyword;
235 int32_t comadj;
236
237 uint32_t uuid_keyword;
238 char uuid[16];
239
240 uint32_t touch_keyword;
241 int32_t touch_xp;
242 int32_t touch_yp;
243 int32_t touch_xd;
244 int32_t touch_yd;
245
246 uint32_t adadj_keyword;
247 int32_t adadj;
248
249 uint32_t phad_keyword;
250 int32_t phadadj;
251} zaurus_bootparam = {
252 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
253 .comadj = 125,
254 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
255 .uuid = { -1 },
256 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
257 .touch_xp = -1,
258 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
259 .adadj = -1,
260 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
261 .phadadj = 0x01,
262};
263
264void sl_bootparam_write(target_phys_addr_t ptr)
265{
266 cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
267 sizeof(struct sl_param_info));
268}
269
