LXR qemu/tcg/hppa/tcg-target.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2008 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#define TCG_TARGET_HPPA 1
  26
  27#if defined(_PA_RISC1_1)
  28#define TCG_TARGET_REG_BITS 32
  29#else
  30#error unsupported
  31#endif
  32
  33#define TCG_TARGET_WORDS_BIGENDIAN
  34
  35#define TCG_TARGET_NB_REGS 32
  36
  37enum {
  38    TCG_REG_R0 = 0,
  39    TCG_REG_R1,
  40    TCG_REG_RP,
  41    TCG_REG_R3,
  42    TCG_REG_R4,
  43    TCG_REG_R5,
  44    TCG_REG_R6,
  45    TCG_REG_R7,
  46    TCG_REG_R8,
  47    TCG_REG_R9,
  48    TCG_REG_R10,
  49    TCG_REG_R11,
  50    TCG_REG_R12,
  51    TCG_REG_R13,
  52    TCG_REG_R14,
  53    TCG_REG_R15,
  54    TCG_REG_R16,
  55    TCG_REG_R17,
  56    TCG_REG_R18,
  57    TCG_REG_R19,
  58    TCG_REG_R20,
  59    TCG_REG_R21,
  60    TCG_REG_R22,
  61    TCG_REG_R23,
  62    TCG_REG_R24,
  63    TCG_REG_R25,
  64    TCG_REG_R26,
  65    TCG_REG_DP,
  66    TCG_REG_RET0,
  67    TCG_REG_RET1,
  68    TCG_REG_SP,
  69    TCG_REG_R31,
  70};
  71
  72#define TCG_CT_CONST_0    0x0100
  73#define TCG_CT_CONST_S5   0x0200
  74#define TCG_CT_CONST_S11  0x0400
  75#define TCG_CT_CONST_MS11 0x0800
  76#define TCG_CT_CONST_AND  0x1000
  77#define TCG_CT_CONST_OR   0x2000
  78
  79/* used for function call generation */
  80#define TCG_REG_CALL_STACK TCG_REG_SP
  81#define TCG_TARGET_STACK_ALIGN 64
  82#define TCG_TARGET_CALL_STACK_OFFSET -48
  83#define TCG_TARGET_STATIC_CALL_ARGS_SIZE 8*4
  84#define TCG_TARGET_CALL_ALIGN_ARGS 1
  85#define TCG_TARGET_STACK_GROWSUP
  86
  87/* optional instructions */
  88// #define TCG_TARGET_HAS_div_i32
  89#define TCG_TARGET_HAS_rot_i32
  90#define TCG_TARGET_HAS_ext8s_i32
  91#define TCG_TARGET_HAS_ext16s_i32
  92#define TCG_TARGET_HAS_bswap16_i32
  93#define TCG_TARGET_HAS_bswap32_i32
  94#define TCG_TARGET_HAS_not_i32
  95#define TCG_TARGET_HAS_andc_i32
  96// #define TCG_TARGET_HAS_orc_i32
  97
  98/* optional instructions automatically implemented */
  99#undef TCG_TARGET_HAS_neg_i32           /* sub rd, 0, rs */
 100#undef TCG_TARGET_HAS_ext8u_i32         /* and rd, rs, 0xff */
 101#undef TCG_TARGET_HAS_ext16u_i32        /* and rd, rs, 0xffff */
 102
 103#define TCG_TARGET_HAS_GUEST_BASE
 104
 105/* Note: must be synced with dyngen-exec.h */
 106#define TCG_AREG0 TCG_REG_R17
 107
 108static inline void flush_icache_range(unsigned long start, unsigned long stop)
 109{
 110    start &= ~31;
 111    while (start <= stop) {
 112        asm volatile ("fdc 0(%0)\n\t"
 113                      "sync\n\t"
 114                      "fic 0(%%sr4, %0)\n\t"
 115                      "sync"
 116                      : : "r"(start) : "memory");
 117        start += 32;
 118    }
 119}
 120