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24#define TCG_TARGET_S390 1
25
26#ifdef __s390x__
27#define TCG_TARGET_REG_BITS 64
28#else
29#define TCG_TARGET_REG_BITS 32
30#endif
31
32#define TCG_TARGET_WORDS_BIGENDIAN
33
34typedef enum TCGReg {
35 TCG_REG_R0 = 0,
36 TCG_REG_R1,
37 TCG_REG_R2,
38 TCG_REG_R3,
39 TCG_REG_R4,
40 TCG_REG_R5,
41 TCG_REG_R6,
42 TCG_REG_R7,
43 TCG_REG_R8,
44 TCG_REG_R9,
45 TCG_REG_R10,
46 TCG_REG_R11,
47 TCG_REG_R12,
48 TCG_REG_R13,
49 TCG_REG_R14,
50 TCG_REG_R15
51} TCGReg;
52
53#define TCG_TARGET_NB_REGS 16
54
55
56#define TCG_TARGET_HAS_div2_i32
57#define TCG_TARGET_HAS_rot_i32
58#define TCG_TARGET_HAS_ext8s_i32
59#define TCG_TARGET_HAS_ext16s_i32
60#define TCG_TARGET_HAS_ext8u_i32
61#define TCG_TARGET_HAS_ext16u_i32
62#define TCG_TARGET_HAS_bswap16_i32
63#define TCG_TARGET_HAS_bswap32_i32
64
65#define TCG_TARGET_HAS_neg_i32
66
67
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69
70
71
72#if TCG_TARGET_REG_BITS == 64
73#define TCG_TARGET_HAS_div2_i64
74#define TCG_TARGET_HAS_rot_i64
75#define TCG_TARGET_HAS_ext8s_i64
76#define TCG_TARGET_HAS_ext16s_i64
77#define TCG_TARGET_HAS_ext32s_i64
78#define TCG_TARGET_HAS_ext8u_i64
79#define TCG_TARGET_HAS_ext16u_i64
80#define TCG_TARGET_HAS_ext32u_i64
81#define TCG_TARGET_HAS_bswap16_i64
82#define TCG_TARGET_HAS_bswap32_i64
83#define TCG_TARGET_HAS_bswap64_i64
84
85#define TCG_TARGET_HAS_neg_i64
86
87
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89
90
91#endif
92
93#define TCG_TARGET_HAS_GUEST_BASE
94
95
96#define TCG_REG_CALL_STACK TCG_REG_R15
97#define TCG_TARGET_STACK_ALIGN 8
98#define TCG_TARGET_CALL_STACK_OFFSET 0
99
100#define TCG_TARGET_EXTEND_ARGS 1
101
102enum {
103
104 TCG_AREG0 = TCG_REG_R10,
105};
106
107static inline void flush_icache_range(unsigned long start, unsigned long stop)
108{
109}
110