1
2typedef struct pflash_t pflash_t;
3
4
5pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
6 BlockDriverState *bs,
7 uint32_t sector_len, int nb_blocs, int width,
8 uint16_t id0, uint16_t id1,
9 uint16_t id2, uint16_t id3, int be);
10
11
12pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
13 BlockDriverState *bs, uint32_t sector_len,
14 int nb_blocs, int nb_mappings, int width,
15 uint16_t id0, uint16_t id1,
16 uint16_t id2, uint16_t id3,
17 uint16_t unlock_addr0, uint16_t unlock_addr1,
18 int be);
19
20
21typedef struct NANDFlashState NANDFlashState;
22NANDFlashState *nand_init(int manf_id, int chip_id);
23void nand_done(NANDFlashState *s);
24void nand_setpins(NANDFlashState *s, uint8_t cle, uint8_t ale,
25 uint8_t ce, uint8_t wp, uint8_t gnd);
26void nand_getpins(NANDFlashState *s, int *rb);
27void nand_setio(NANDFlashState *s, uint8_t value);
28uint8_t nand_getio(NANDFlashState *s);
29
30#define NAND_MFR_TOSHIBA 0x98
31#define NAND_MFR_SAMSUNG 0xec
32#define NAND_MFR_FUJITSU 0x04
33#define NAND_MFR_NATIONAL 0x8f
34#define NAND_MFR_RENESAS 0x07
35#define NAND_MFR_STMICRO 0x20
36#define NAND_MFR_HYNIX 0xad
37#define NAND_MFR_MICRON 0x2c
38
39
40void onenand_base_update(void *opaque, target_phys_addr_t new);
41void onenand_base_unmap(void *opaque);
42void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
43void *onenand_raw_otp(void *opaque);
44
45
46typedef struct {
47 uint8_t cp;
48 uint16_t lp[2];
49 uint16_t count;
50} ECCState;
51
52uint8_t ecc_digest(ECCState *s, uint8_t sample);
53void ecc_reset(ECCState *s);
54extern VMStateDescription vmstate_ecc_state;
55