LXR qemu/hw/pci.h

   1#ifndef QEMU_PCI_H
   2#define QEMU_PCI_H
   3
   4#include "qemu-common.h"
   5#include "qobject.h"
   6
   7#include "qdev.h"
   8
   9/* PCI includes legacy ISA access.  */
  10#include "isa.h"
  11
  12#include "pcie.h"
  13
  14/* PCI bus */
  15
  16#define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17#define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18#define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19#define PCI_SLOT_MAX            32
  20#define PCI_FUNC_MAX            8
  21
  22/* Class, Vendor and Device IDs from Linux's pci_ids.h */
  23#include "pci_ids.h"
  24
  25/* QEMU-specific Vendor and Device ID definitions */
  26
  27/* IBM (0x1014) */
  28#define PCI_DEVICE_ID_IBM_440GX          0x027f
  29#define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  30
  31/* Hitachi (0x1054) */
  32#define PCI_VENDOR_ID_HITACHI            0x1054
  33#define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  34
  35/* Apple (0x106b) */
  36#define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  37#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  38#define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  39#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  40#define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  41
  42/* Realtek (0x10ec) */
  43#define PCI_DEVICE_ID_REALTEK_8029       0x8029
  44
  45/* Xilinx (0x10ee) */
  46#define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  47
  48/* Marvell (0x11ab) */
  49#define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  50
  51/* QEMU/Bochs VGA (0x1234) */
  52#define PCI_VENDOR_ID_QEMU               0x1234
  53#define PCI_DEVICE_ID_QEMU_VGA           0x1111
  54
  55/* VMWare (0x15ad) */
  56#define PCI_VENDOR_ID_VMWARE             0x15ad
  57#define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  58#define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  59#define PCI_DEVICE_ID_VMWARE_NET         0x0720
  60#define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  61#define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62
  63/* Intel (0x8086) */
  64#define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  65#define PCI_DEVICE_ID_INTEL_82557        0x1229
  66#define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  67
  68/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69#define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71#define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73#define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74#define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75#define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76#define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78#define FMT_PCIBUS                      PRIx64
  79
  80typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  81                                uint32_t address, uint32_t data, int len);
  82typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  83                                   uint32_t address, int len);
  84typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  85                                pcibus_t addr, pcibus_t size, int type);
  86typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  87
  88typedef struct PCIIORegion {
  89    pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  90#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  91    pcibus_t size;
  92    pcibus_t filtered_size;
  93    uint8_t type;
  94    PCIMapIORegionFunc *map_func;
  95    ram_addr_t ram_addr;
  96} PCIIORegion;
  97
  98#define PCI_ROM_SLOT 6
  99#define PCI_NUM_REGIONS 7
 100
 101#include "pci_regs.h"
 102
 103/* PCI HEADER_TYPE */
 104#define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 105
 106/* Size of the standard PCI config header */
 107#define PCI_CONFIG_HEADER_SIZE 0x40
 108/* Size of the standard PCI config space */
 109#define PCI_CONFIG_SPACE_SIZE 0x100
 110/* Size of the standart PCIe config space: 4KB */
 111#define PCIE_CONFIG_SPACE_SIZE  0x1000
 112
 113#define PCI_NUM_PINS 4 /* A-D */
 114
 115/* Bits in cap_present field. */
 116enum {
 117    QEMU_PCI_CAP_MSI = 0x1,
 118    QEMU_PCI_CAP_MSIX = 0x2,
 119    QEMU_PCI_CAP_EXPRESS = 0x4,
 120
 121    /* multifunction capable device */
 122#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 123    QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 124
 125    /* command register SERR bit enabled */
 126#define QEMU_PCI_CAP_SERR_BITNR 4
 127    QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 128};
 129
 130struct PCIDevice {
 131    DeviceState qdev;
 132    /* PCI config space */
 133    uint8_t *config;
 134
 135    /* Used to enable config checks on load. Note that writable bits are
 136     * never checked even if set in cmask. */
 137    uint8_t *cmask;
 138
 139    /* Used to implement R/W bytes */
 140    uint8_t *wmask;
 141
 142    /* Used to implement RW1C(Write 1 to Clear) bytes */
 143    uint8_t *w1cmask;
 144
 145    /* Used to allocate config space for capabilities. */
 146    uint8_t *used;
 147
 148    /* the following fields are read only */
 149    PCIBus *bus;
 150    uint32_t devfn;
 151    char name[64];
 152    PCIIORegion io_regions[PCI_NUM_REGIONS];
 153
 154    /* do not access the following fields */
 155    PCIConfigReadFunc *config_read;
 156    PCIConfigWriteFunc *config_write;
 157
 158    /* IRQ objects for the INTA-INTD pins.  */
 159    qemu_irq *irq;
 160
 161    /* Current IRQ levels.  Used internally by the generic PCI code.  */
 162    uint8_t irq_state;
 163
 164    /* Capability bits */
 165    uint32_t cap_present;
 166
 167    /* Offset of MSI-X capability in config space */
 168    uint8_t msix_cap;
 169
 170    /* MSI-X entries */
 171    int msix_entries_nr;
 172
 173    /* Space to store MSIX table */
 174    uint8_t *msix_table_page;
 175    /* MMIO index used to map MSIX table and pending bit entries. */
 176    int msix_mmio_index;
 177    /* Reference-count for entries actually in use by driver. */
 178    unsigned *msix_entry_used;
 179    /* Region including the MSI-X table */
 180    uint32_t msix_bar_size;
 181    /* Version id needed for VMState */
 182    int32_t version_id;
 183
 184    /* Offset of MSI capability in config space */
 185    uint8_t msi_cap;
 186
 187    /* PCI Express */
 188    PCIExpressDevice exp;
 189
 190    /* Location of option rom */
 191    char *romfile;
 192    ram_addr_t rom_offset;
 193    uint32_t rom_bar;
 194};
 195
 196PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 197                               int instance_size, int devfn,
 198                               PCIConfigReadFunc *config_read,
 199                               PCIConfigWriteFunc *config_write);
 200
 201void pci_register_bar(PCIDevice *pci_dev, int region_num,
 202                            pcibus_t size, uint8_t type,
 203                            PCIMapIORegionFunc *map_func);
 204void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
 205                             pcibus_t size, uint8_t attr, ram_addr_t ram_addr);
 206
 207int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 208                       uint8_t offset, uint8_t size);
 209
 210void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 211
 212void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 213
 214uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 215
 216
 217uint32_t pci_default_read_config(PCIDevice *d,
 218                                 uint32_t address, int len);
 219void pci_default_write_config(PCIDevice *d,
 220                              uint32_t address, uint32_t val, int len);
 221void pci_device_save(PCIDevice *s, QEMUFile *f);
 222int pci_device_load(PCIDevice *s, QEMUFile *f);
 223
 224typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 225typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 226
 227typedef enum {
 228    PCI_HOTPLUG_DISABLED,
 229    PCI_HOTPLUG_ENABLED,
 230    PCI_COLDPLUG_ENABLED,
 231} PCIHotplugState;
 232
 233typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 234                              PCIHotplugState state);
 235void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 236                         const char *name, uint8_t devfn_min);
 237PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min);
 238void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 239                  void *irq_opaque, int nirq);
 240int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 241void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 242PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 243                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 244                         void *irq_opaque, uint8_t devfn_min, int nirq);
 245void pci_device_reset(PCIDevice *dev);
 246void pci_bus_reset(PCIBus *bus);
 247
 248void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 249
 250PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 251                        const char *default_devaddr);
 252PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 253                               const char *default_devaddr);
 254int pci_bus_num(PCIBus *s);
 255void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 256PCIBus *pci_find_root_bus(int domain);
 257int pci_find_domain(const PCIBus *bus);
 258PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 259PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 260int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 261PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 262
 263int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 264                      unsigned int *slotp, unsigned int *funcp);
 265int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 266                     unsigned *slotp);
 267
 268void do_pci_info_print(Monitor *mon, const QObject *data);
 269void do_pci_info(Monitor *mon, QObject **ret_data);
 270void pci_bridge_update_mappings(PCIBus *b);
 271
 272void pci_device_deassert_intx(PCIDevice *dev);
 273
 274static inline void
 275pci_set_byte(uint8_t *config, uint8_t val)
 276{
 277    *config = val;
 278}
 279
 280static inline uint8_t
 281pci_get_byte(const uint8_t *config)
 282{
 283    return *config;
 284}
 285
 286static inline void
 287pci_set_word(uint8_t *config, uint16_t val)
 288{
 289    cpu_to_le16wu((uint16_t *)config, val);
 290}
 291
 292static inline uint16_t
 293pci_get_word(const uint8_t *config)
 294{
 295    return le16_to_cpupu((const uint16_t *)config);
 296}
 297
 298static inline void
 299pci_set_long(uint8_t *config, uint32_t val)
 300{
 301    cpu_to_le32wu((uint32_t *)config, val);
 302}
 303
 304static inline uint32_t
 305pci_get_long(const uint8_t *config)
 306{
 307    return le32_to_cpupu((const uint32_t *)config);
 308}
 309
 310static inline void
 311pci_set_quad(uint8_t *config, uint64_t val)
 312{
 313    cpu_to_le64w((uint64_t *)config, val);
 314}
 315
 316static inline uint64_t
 317pci_get_quad(const uint8_t *config)
 318{
 319    return le64_to_cpup((const uint64_t *)config);
 320}
 321
 322static inline void
 323pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 324{
 325    pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 326}
 327
 328static inline void
 329pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 330{
 331    pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 332}
 333
 334static inline void
 335pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 336{
 337    pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 338}
 339
 340static inline void
 341pci_config_set_class(uint8_t *pci_config, uint16_t val)
 342{
 343    pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 344}
 345
 346static inline void
 347pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 348{
 349    pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 350}
 351
 352static inline void
 353pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 354{
 355    pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 356}
 357
 358/*
 359 * helper functions to do bit mask operation on configuration space.
 360 * Just to set bit, use test-and-set and discard returned value.
 361 * Just to clear bit, use test-and-clear and discard returned value.
 362 * NOTE: They aren't atomic.
 363 */
 364static inline uint8_t
 365pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 366{
 367    uint8_t val = pci_get_byte(config);
 368    pci_set_byte(config, val & ~mask);
 369    return val & mask;
 370}
 371
 372static inline uint8_t
 373pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 374{
 375    uint8_t val = pci_get_byte(config);
 376    pci_set_byte(config, val | mask);
 377    return val & mask;
 378}
 379
 380static inline uint16_t
 381pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 382{
 383    uint16_t val = pci_get_word(config);
 384    pci_set_word(config, val & ~mask);
 385    return val & mask;
 386}
 387
 388static inline uint16_t
 389pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 390{
 391    uint16_t val = pci_get_word(config);
 392    pci_set_word(config, val | mask);
 393    return val & mask;
 394}
 395
 396static inline uint32_t
 397pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 398{
 399    uint32_t val = pci_get_long(config);
 400    pci_set_long(config, val & ~mask);
 401    return val & mask;
 402}
 403
 404static inline uint32_t
 405pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 406{
 407    uint32_t val = pci_get_long(config);
 408    pci_set_long(config, val | mask);
 409    return val & mask;
 410}
 411
 412static inline uint64_t
 413pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 414{
 415    uint64_t val = pci_get_quad(config);
 416    pci_set_quad(config, val & ~mask);
 417    return val & mask;
 418}
 419
 420static inline uint64_t
 421pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 422{
 423    uint64_t val = pci_get_quad(config);
 424    pci_set_quad(config, val | mask);
 425    return val & mask;
 426}
 427
 428typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 429typedef struct {
 430    DeviceInfo qdev;
 431    pci_qdev_initfn init;
 432    PCIUnregisterFunc *exit;
 433    PCIConfigReadFunc *config_read;
 434    PCIConfigWriteFunc *config_write;
 435
 436    uint16_t vendor_id;
 437    uint16_t device_id;
 438    uint8_t revision;
 439    uint16_t class_id;
 440    uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 441    uint16_t subsystem_id;              /* only for header type = 0 */
 442
 443    /*
 444     * pci-to-pci bridge or normal device.
 445     * This doesn't mean pci host switch.
 446     * When card bus bridge is supported, this would be enhanced.
 447     */
 448    int is_bridge;
 449
 450    /* pcie stuff */
 451    int is_express;   /* is this device pci express? */
 452
 453    /* device isn't hot-pluggable */
 454    int no_hotplug;
 455
 456    /* rom bar */
 457    const char *romfile;
 458} PCIDeviceInfo;
 459
 460void pci_qdev_register(PCIDeviceInfo *info);
 461void pci_qdev_register_many(PCIDeviceInfo *info);
 462
 463PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 464                                    const char *name);
 465PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 466                                           bool multifunction,
 467                                           const char *name);
 468PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 469                                        bool multifunction,
 470                                        const char *name);
 471PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 472PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 473PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 474
 475static inline int pci_is_express(const PCIDevice *d)
 476{
 477    return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 478}
 479
 480static inline uint32_t pci_config_size(const PCIDevice *d)
 481{
 482    return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 483}
 484
 485#endif
 486