1
2
3
4
5
6
7
8
9
10#include "hw.h"
11#include "pxa.h"
12#include "arm-misc.h"
13#include "sysemu.h"
14#include "pcmcia.h"
15#include "i2c.h"
16#include "ssi.h"
17#include "flash.h"
18#include "qemu-timer.h"
19#include "devices.h"
20#include "sharpsl.h"
21#include "console.h"
22#include "block.h"
23#include "audio/audio.h"
24#include "boards.h"
25#include "blockdev.h"
26#include "sysbus.h"
27
28#undef REG_FMT
29#define REG_FMT "0x%02lx"
30
31
32#define FLASH_BASE 0x0c000000
33#define FLASH_ECCLPLB 0x00
34#define FLASH_ECCLPUB 0x04
35#define FLASH_ECCCP 0x08
36#define FLASH_ECCCNTR 0x0c
37#define FLASH_ECCCLRR 0x10
38#define FLASH_FLASHIO 0x14
39#define FLASH_FLASHCTL 0x18
40
41#define FLASHCTL_CE0 (1 << 0)
42#define FLASHCTL_CLE (1 << 1)
43#define FLASHCTL_ALE (1 << 2)
44#define FLASHCTL_WP (1 << 3)
45#define FLASHCTL_CE1 (1 << 4)
46#define FLASHCTL_RYBY (1 << 5)
47#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
48
49typedef struct {
50 SysBusDevice busdev;
51 NANDFlashState *nand;
52 uint8_t ctl;
53 uint8_t manf_id;
54 uint8_t chip_id;
55 ECCState ecc;
56} SLNANDState;
57
58static uint32_t sl_readb(void *opaque, target_phys_addr_t addr)
59{
60 SLNANDState *s = (SLNANDState *) opaque;
61 int ryby;
62
63 switch (addr) {
64#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
65 case FLASH_ECCLPLB:
66 return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
67 BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
68
69#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
70 case FLASH_ECCLPUB:
71 return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
72 BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
73
74 case FLASH_ECCCP:
75 return s->ecc.cp;
76
77 case FLASH_ECCCNTR:
78 return s->ecc.count & 0xff;
79
80 case FLASH_FLASHCTL:
81 nand_getpins(s->nand, &ryby);
82 if (ryby)
83 return s->ctl | FLASHCTL_RYBY;
84 else
85 return s->ctl;
86
87 case FLASH_FLASHIO:
88 return ecc_digest(&s->ecc, nand_getio(s->nand));
89
90 default:
91 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
92 }
93 return 0;
94}
95
96static uint32_t sl_readl(void *opaque, target_phys_addr_t addr)
97{
98 SLNANDState *s = (SLNANDState *) opaque;
99
100 if (addr == FLASH_FLASHIO)
101 return ecc_digest(&s->ecc, nand_getio(s->nand)) |
102 (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16);
103
104 return sl_readb(opaque, addr);
105}
106
107static void sl_writeb(void *opaque, target_phys_addr_t addr,
108 uint32_t value)
109{
110 SLNANDState *s = (SLNANDState *) opaque;
111
112 switch (addr) {
113 case FLASH_ECCCLRR:
114
115 ecc_reset(&s->ecc);
116 break;
117
118 case FLASH_FLASHCTL:
119 s->ctl = value & 0xff & ~FLASHCTL_RYBY;
120 nand_setpins(s->nand,
121 s->ctl & FLASHCTL_CLE,
122 s->ctl & FLASHCTL_ALE,
123 s->ctl & FLASHCTL_NCE,
124 s->ctl & FLASHCTL_WP,
125 0);
126 break;
127
128 case FLASH_FLASHIO:
129 nand_setio(s->nand, ecc_digest(&s->ecc, value & 0xff));
130 break;
131
132 default:
133 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
134 }
135}
136
137enum {
138 FLASH_128M,
139 FLASH_1024M,
140};
141
142static CPUReadMemoryFunc * const sl_readfn[] = {
143 sl_readb,
144 sl_readb,
145 sl_readl,
146};
147static CPUWriteMemoryFunc * const sl_writefn[] = {
148 sl_writeb,
149 sl_writeb,
150 sl_writeb,
151};
152
153static void sl_flash_register(PXA2xxState *cpu, int size)
154{
155 DeviceState *dev;
156
157 dev = qdev_create(NULL, "sl-nand");
158
159 qdev_prop_set_uint8(dev, "manf_id", NAND_MFR_SAMSUNG);
160 if (size == FLASH_128M)
161 qdev_prop_set_uint8(dev, "chip_id", 0x73);
162 else if (size == FLASH_1024M)
163 qdev_prop_set_uint8(dev, "chip_id", 0xf1);
164
165 qdev_init_nofail(dev);
166 sysbus_mmio_map(sysbus_from_qdev(dev), 0, FLASH_BASE);
167}
168
169static int sl_nand_init(SysBusDevice *dev) {
170 int iomemtype;
171 SLNANDState *s;
172
173 s = FROM_SYSBUS(SLNANDState, dev);
174
175 s->ctl = 0;
176 s->nand = nand_init(s->manf_id, s->chip_id);
177
178 iomemtype = cpu_register_io_memory(sl_readfn,
179 sl_writefn, s, DEVICE_NATIVE_ENDIAN);
180
181 sysbus_init_mmio(dev, 0x40, iomemtype);
182
183 return 0;
184}
185
186
187
188#define SPITZ_KEY_STROBE_NUM 11
189#define SPITZ_KEY_SENSE_NUM 7
190
191static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
192 12, 17, 91, 34, 36, 38, 39
193};
194
195static const int spitz_gpio_key_strobe[SPITZ_KEY_STROBE_NUM] = {
196 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114
197};
198
199
200static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
201 { 0x1d, 0x02, 0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0e, 0x3f, 0x40 },
202 { -1 , 0x03, 0x05, 0x13, 0x15, 0x09, 0x17, 0x18, 0x19, 0x41, 0x42 },
203 { 0x0f, 0x10, 0x12, 0x14, 0x22, 0x16, 0x24, 0x25, -1 , -1 , -1 },
204 { 0x3c, 0x11, 0x1f, 0x21, 0x2f, 0x23, 0x32, 0x26, -1 , 0x36, -1 },
205 { 0x3b, 0x1e, 0x20, 0x2e, 0x30, 0x31, 0x34, -1 , 0x1c, 0x2a, -1 },
206 { 0x44, 0x2c, 0x2d, 0x0c, 0x39, 0x33, -1 , 0x48, -1 , -1 , 0x38 },
207 { 0x37, 0x3d, -1 , 0x45, 0x57, 0x58, 0x4b, 0x50, 0x4d, -1 , -1 },
208 { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
209};
210
211#define SPITZ_GPIO_AK_INT 13
212#define SPITZ_GPIO_SYNC 16
213#define SPITZ_GPIO_ON_KEY 95
214#define SPITZ_GPIO_SWA 97
215#define SPITZ_GPIO_SWB 96
216
217
218static const int spitz_gpiomap[5] = {
219 SPITZ_GPIO_AK_INT, SPITZ_GPIO_SYNC, SPITZ_GPIO_ON_KEY,
220 SPITZ_GPIO_SWA, SPITZ_GPIO_SWB,
221};
222
223typedef struct {
224 SysBusDevice busdev;
225 qemu_irq sense[SPITZ_KEY_SENSE_NUM];
226 qemu_irq gpiomap[5];
227 int keymap[0x80];
228 uint16_t keyrow[SPITZ_KEY_SENSE_NUM];
229 uint16_t strobe_state;
230 uint16_t sense_state;
231
232 uint16_t pre_map[0x100];
233 uint16_t modifiers;
234 uint16_t imodifiers;
235 uint8_t fifo[16];
236 int fifopos, fifolen;
237 QEMUTimer *kbdtimer;
238} SpitzKeyboardState;
239
240static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
241{
242 int i;
243 uint16_t strobe, sense = 0;
244 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++) {
245 strobe = s->keyrow[i] & s->strobe_state;
246 if (strobe) {
247 sense |= 1 << i;
248 if (!(s->sense_state & (1 << i)))
249 qemu_irq_raise(s->sense[i]);
250 } else if (s->sense_state & (1 << i))
251 qemu_irq_lower(s->sense[i]);
252 }
253
254 s->sense_state = sense;
255}
256
257static void spitz_keyboard_strobe(void *opaque, int line, int level)
258{
259 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
260
261 if (level)
262 s->strobe_state |= 1 << line;
263 else
264 s->strobe_state &= ~(1 << line);
265 spitz_keyboard_sense_update(s);
266}
267
268static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
269{
270 int spitz_keycode = s->keymap[keycode & 0x7f];
271 if (spitz_keycode == -1)
272 return;
273
274
275 if ((spitz_keycode >> 4) == SPITZ_KEY_SENSE_NUM) {
276 qemu_set_irq(s->gpiomap[spitz_keycode & 0xf], (keycode < 0x80));
277 return;
278 }
279
280 if (keycode & 0x80)
281 s->keyrow[spitz_keycode >> 4] &= ~(1 << (spitz_keycode & 0xf));
282 else
283 s->keyrow[spitz_keycode >> 4] |= 1 << (spitz_keycode & 0xf);
284
285 spitz_keyboard_sense_update(s);
286}
287
288#define SHIFT (1 << 7)
289#define CTRL (1 << 8)
290#define FN (1 << 9)
291
292#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
293
294static void spitz_keyboard_handler(void *opaque, int keycode)
295{
296 SpitzKeyboardState *s = opaque;
297 uint16_t code;
298 int mapcode;
299 switch (keycode) {
300 case 0x2a:
301 s->modifiers |= 1;
302 break;
303 case 0xaa:
304 s->modifiers &= ~1;
305 break;
306 case 0x36:
307 s->modifiers |= 2;
308 break;
309 case 0xb6:
310 s->modifiers &= ~2;
311 break;
312 case 0x1d:
313 s->modifiers |= 4;
314 break;
315 case 0x9d:
316 s->modifiers &= ~4;
317 break;
318 case 0x38:
319 s->modifiers |= 8;
320 break;
321 case 0xb8:
322 s->modifiers &= ~8;
323 break;
324 }
325
326 code = s->pre_map[mapcode = ((s->modifiers & 3) ?
327 (keycode | SHIFT) :
328 (keycode & ~SHIFT))];
329
330 if (code != mapcode) {
331#if 0
332 if ((code & SHIFT) && !(s->modifiers & 1))
333 QUEUE_KEY(0x2a | (keycode & 0x80));
334 if ((code & CTRL ) && !(s->modifiers & 4))
335 QUEUE_KEY(0x1d | (keycode & 0x80));
336 if ((code & FN ) && !(s->modifiers & 8))
337 QUEUE_KEY(0x38 | (keycode & 0x80));
338 if ((code & FN ) && (s->modifiers & 1))
339 QUEUE_KEY(0x2a | (~keycode & 0x80));
340 if ((code & FN ) && (s->modifiers & 2))
341 QUEUE_KEY(0x36 | (~keycode & 0x80));
342#else
343 if (keycode & 0x80) {
344 if ((s->imodifiers & 1 ) && !(s->modifiers & 1))
345 QUEUE_KEY(0x2a | 0x80);
346 if ((s->imodifiers & 4 ) && !(s->modifiers & 4))
347 QUEUE_KEY(0x1d | 0x80);
348 if ((s->imodifiers & 8 ) && !(s->modifiers & 8))
349 QUEUE_KEY(0x38 | 0x80);
350 if ((s->imodifiers & 0x10) && (s->modifiers & 1))
351 QUEUE_KEY(0x2a);
352 if ((s->imodifiers & 0x20) && (s->modifiers & 2))
353 QUEUE_KEY(0x36);
354 s->imodifiers = 0;
355 } else {
356 if ((code & SHIFT) && !((s->modifiers | s->imodifiers) & 1)) {
357 QUEUE_KEY(0x2a);
358 s->imodifiers |= 1;
359 }
360 if ((code & CTRL ) && !((s->modifiers | s->imodifiers) & 4)) {
361 QUEUE_KEY(0x1d);
362 s->imodifiers |= 4;
363 }
364 if ((code & FN ) && !((s->modifiers | s->imodifiers) & 8)) {
365 QUEUE_KEY(0x38);
366 s->imodifiers |= 8;
367 }
368 if ((code & FN ) && (s->modifiers & 1) &&
369 !(s->imodifiers & 0x10)) {
370 QUEUE_KEY(0x2a | 0x80);
371 s->imodifiers |= 0x10;
372 }
373 if ((code & FN ) && (s->modifiers & 2) &&
374 !(s->imodifiers & 0x20)) {
375 QUEUE_KEY(0x36 | 0x80);
376 s->imodifiers |= 0x20;
377 }
378 }
379#endif
380 }
381
382 QUEUE_KEY((code & 0x7f) | (keycode & 0x80));
383}
384
385static void spitz_keyboard_tick(void *opaque)
386{
387 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
388
389 if (s->fifolen) {
390 spitz_keyboard_keydown(s, s->fifo[s->fifopos ++]);
391 s->fifolen --;
392 if (s->fifopos >= 16)
393 s->fifopos = 0;
394 }
395
396 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock) +
397 get_ticks_per_sec() / 32);
398}
399
400static void spitz_keyboard_pre_map(SpitzKeyboardState *s)
401{
402 int i;
403 for (i = 0; i < 0x100; i ++)
404 s->pre_map[i] = i;
405 s->pre_map[0x02 | SHIFT ] = 0x02 | SHIFT;
406 s->pre_map[0x28 | SHIFT ] = 0x03 | SHIFT;
407 s->pre_map[0x04 | SHIFT ] = 0x04 | SHIFT;
408 s->pre_map[0x05 | SHIFT ] = 0x05 | SHIFT;
409 s->pre_map[0x06 | SHIFT ] = 0x06 | SHIFT;
410 s->pre_map[0x08 | SHIFT ] = 0x07 | SHIFT;
411 s->pre_map[0x28 ] = 0x08 | SHIFT;
412 s->pre_map[0x0a | SHIFT ] = 0x09 | SHIFT;
413 s->pre_map[0x0b | SHIFT ] = 0x0a | SHIFT;
414 s->pre_map[0x29 | SHIFT ] = 0x0b | SHIFT;
415 s->pre_map[0x03 | SHIFT ] = 0x0c | SHIFT;
416 s->pre_map[0xd3 ] = 0x0e | FN;
417 s->pre_map[0x3a ] = 0x0f | FN;
418 s->pre_map[0x07 | SHIFT ] = 0x11 | FN;
419 s->pre_map[0x0d ] = 0x12 | FN;
420 s->pre_map[0x0d | SHIFT ] = 0x13 | FN;
421 s->pre_map[0x1a ] = 0x14 | FN;
422 s->pre_map[0x1b ] = 0x15 | FN;
423 s->pre_map[0x1a | SHIFT ] = 0x16 | FN;
424 s->pre_map[0x1b | SHIFT ] = 0x17 | FN;
425 s->pre_map[0x27 ] = 0x22 | FN;
426 s->pre_map[0x27 | SHIFT ] = 0x23 | FN;
427 s->pre_map[0x09 | SHIFT ] = 0x24 | FN;
428 s->pre_map[0x2b ] = 0x25 | FN;
429 s->pre_map[0x2b | SHIFT ] = 0x26 | FN;
430 s->pre_map[0x0c | SHIFT ] = 0x30 | FN;
431 s->pre_map[0x33 | SHIFT ] = 0x33 | FN;
432 s->pre_map[0x35 ] = 0x33 | SHIFT;
433 s->pre_map[0x34 | SHIFT ] = 0x34 | FN;
434 s->pre_map[0x35 | SHIFT ] = 0x34 | SHIFT;
435 s->pre_map[0x49 ] = 0x48 | FN;
436 s->pre_map[0x51 ] = 0x50 | FN;
437
438 s->modifiers = 0;
439 s->imodifiers = 0;
440 s->fifopos = 0;
441 s->fifolen = 0;
442}
443
444#undef SHIFT
445#undef CTRL
446#undef FN
447
448static int spitz_keyboard_post_load(void *opaque, int version_id)
449{
450 SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
451
452
453 memset(s->keyrow, 0, sizeof(s->keyrow));
454 spitz_keyboard_sense_update(s);
455 s->modifiers = 0;
456 s->imodifiers = 0;
457 s->fifopos = 0;
458 s->fifolen = 0;
459
460 return 0;
461}
462
463static void spitz_keyboard_register(PXA2xxState *cpu)
464{
465 int i;
466 DeviceState *dev;
467 SpitzKeyboardState *s;
468
469 dev = sysbus_create_simple("spitz-keyboard", -1, NULL);
470 s = FROM_SYSBUS(SpitzKeyboardState, sysbus_from_qdev(dev));
471
472 for (i = 0; i < SPITZ_KEY_SENSE_NUM; i ++)
473 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(cpu->gpio, spitz_gpio_key_sense[i]));
474
475 for (i = 0; i < 5; i ++)
476 s->gpiomap[i] = qdev_get_gpio_in(cpu->gpio, spitz_gpiomap[i]);
477
478 if (!graphic_rotate)
479 s->gpiomap[4] = qemu_irq_invert(s->gpiomap[4]);
480
481 for (i = 0; i < 5; i++)
482 qemu_set_irq(s->gpiomap[i], 0);
483
484 for (i = 0; i < SPITZ_KEY_STROBE_NUM; i ++)
485 qdev_connect_gpio_out(cpu->gpio, spitz_gpio_key_strobe[i],
486 qdev_get_gpio_in(dev, i));
487
488 qemu_mod_timer(s->kbdtimer, qemu_get_clock_ns(vm_clock));
489
490 qemu_add_kbd_event_handler(spitz_keyboard_handler, s);
491}
492
493static int spitz_keyboard_init(SysBusDevice *dev)
494{
495 SpitzKeyboardState *s;
496 int i, j;
497
498 s = FROM_SYSBUS(SpitzKeyboardState, dev);
499
500 for (i = 0; i < 0x80; i ++)
501 s->keymap[i] = -1;
502 for (i = 0; i < SPITZ_KEY_SENSE_NUM + 1; i ++)
503 for (j = 0; j < SPITZ_KEY_STROBE_NUM; j ++)
504 if (spitz_keymap[i][j] != -1)
505 s->keymap[spitz_keymap[i][j]] = (i << 4) | j;
506
507 spitz_keyboard_pre_map(s);
508
509 s->kbdtimer = qemu_new_timer_ns(vm_clock, spitz_keyboard_tick, s);
510 qdev_init_gpio_in(&dev->qdev, spitz_keyboard_strobe, SPITZ_KEY_STROBE_NUM);
511 qdev_init_gpio_out(&dev->qdev, s->sense, SPITZ_KEY_SENSE_NUM);
512
513 return 0;
514}
515
516
517
518#define LCDTG_RESCTL 0x00
519#define LCDTG_PHACTRL 0x01
520#define LCDTG_DUTYCTRL 0x02
521#define LCDTG_POWERREG0 0x03
522#define LCDTG_POWERREG1 0x04
523#define LCDTG_GPOR3 0x05
524#define LCDTG_PICTRL 0x06
525#define LCDTG_POLCTRL 0x07
526
527typedef struct {
528 SSISlave ssidev;
529 uint32_t bl_intensity;
530 uint32_t bl_power;
531} SpitzLCDTG;
532
533static void spitz_bl_update(SpitzLCDTG *s)
534{
535 if (s->bl_power && s->bl_intensity)
536 zaurus_printf("LCD Backlight now at %i/63\n", s->bl_intensity);
537 else
538 zaurus_printf("LCD Backlight now off\n");
539}
540
541
542static SpitzLCDTG *spitz_lcdtg;
543
544static inline void spitz_bl_bit5(void *opaque, int line, int level)
545{
546 SpitzLCDTG *s = spitz_lcdtg;
547 int prev = s->bl_intensity;
548
549 if (level)
550 s->bl_intensity &= ~0x20;
551 else
552 s->bl_intensity |= 0x20;
553
554 if (s->bl_power && prev != s->bl_intensity)
555 spitz_bl_update(s);
556}
557
558static inline void spitz_bl_power(void *opaque, int line, int level)
559{
560 SpitzLCDTG *s = spitz_lcdtg;
561 s->bl_power = !!level;
562 spitz_bl_update(s);
563}
564
565static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
566{
567 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
568 int addr;
569 addr = value >> 5;
570 value &= 0x1f;
571
572 switch (addr) {
573 case LCDTG_RESCTL:
574 if (value)
575 zaurus_printf("LCD in QVGA mode\n");
576 else
577 zaurus_printf("LCD in VGA mode\n");
578 break;
579
580 case LCDTG_DUTYCTRL:
581 s->bl_intensity &= ~0x1f;
582 s->bl_intensity |= value;
583 if (s->bl_power)
584 spitz_bl_update(s);
585 break;
586
587 case LCDTG_POWERREG0:
588
589 break;
590 }
591 return 0;
592}
593
594static int spitz_lcdtg_init(SSISlave *dev)
595{
596 SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
597
598 spitz_lcdtg = s;
599 s->bl_power = 0;
600 s->bl_intensity = 0x20;
601
602 return 0;
603}
604
605
606
607#define CORGI_SSP_PORT 2
608
609#define SPITZ_GPIO_LCDCON_CS 53
610#define SPITZ_GPIO_ADS7846_CS 14
611#define SPITZ_GPIO_MAX1111_CS 20
612#define SPITZ_GPIO_TP_INT 11
613
614static DeviceState *max1111;
615
616
617typedef struct {
618 SSISlave ssidev;
619 SSIBus *bus[3];
620 uint32_t enable[3];
621} CorgiSSPState;
622
623static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
624{
625 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
626 int i;
627
628 for (i = 0; i < 3; i++) {
629 if (s->enable[i]) {
630 return ssi_transfer(s->bus[i], value);
631 }
632 }
633 return 0;
634}
635
636static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
637{
638 CorgiSSPState *s = (CorgiSSPState *)opaque;
639 assert(line >= 0 && line < 3);
640 s->enable[line] = !level;
641}
642
643#define MAX1111_BATT_VOLT 1
644#define MAX1111_BATT_TEMP 2
645#define MAX1111_ACIN_VOLT 3
646
647#define SPITZ_BATTERY_TEMP 0xe0
648#define SPITZ_BATTERY_VOLT 0xd0
649#define SPITZ_CHARGEON_ACIN 0x80
650
651static void spitz_adc_temp_on(void *opaque, int line, int level)
652{
653 if (!max1111)
654 return;
655
656 if (level)
657 max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
658 else
659 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
660}
661
662static int corgi_ssp_init(SSISlave *dev)
663{
664 CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
665
666 qdev_init_gpio_in(&dev->qdev, corgi_ssp_gpio_cs, 3);
667 s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
668 s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
669 s->bus[2] = ssi_create_bus(&dev->qdev, "ssi2");
670
671 return 0;
672}
673
674static void spitz_ssp_attach(PXA2xxState *cpu)
675{
676 DeviceState *mux;
677 DeviceState *dev;
678 void *bus;
679
680 mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
681
682 bus = qdev_get_child_bus(mux, "ssi0");
683 ssi_create_slave(bus, "spitz-lcdtg");
684
685 bus = qdev_get_child_bus(mux, "ssi1");
686 dev = ssi_create_slave(bus, "ads7846");
687 qdev_connect_gpio_out(dev, 0,
688 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
689
690 bus = qdev_get_child_bus(mux, "ssi2");
691 max1111 = ssi_create_slave(bus, "max1111");
692 max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
693 max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
694 max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
695
696 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
697 qdev_get_gpio_in(mux, 0));
698 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
699 qdev_get_gpio_in(mux, 1));
700 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
701 qdev_get_gpio_in(mux, 2));
702}
703
704
705
706static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
707{
708 PCMCIACardState *md;
709 BlockDriverState *bs;
710 DriveInfo *dinfo;
711
712 dinfo = drive_get(IF_IDE, 0, 0);
713 if (!dinfo)
714 return;
715 bs = dinfo->bdrv;
716 if (bdrv_is_inserted(bs) && !bdrv_is_removable(bs)) {
717 md = dscm1xxxx_init(dinfo);
718 pxa2xx_pcmcia_attach(cpu->pcmcia[slot], md);
719 }
720}
721
722
723
724#define AKITA_MAX_ADDR 0x18
725#define SPITZ_WM_ADDRL 0x1b
726#define SPITZ_WM_ADDRH 0x1a
727
728#define SPITZ_GPIO_WM 5
729
730static void spitz_wm8750_addr(void *opaque, int line, int level)
731{
732 i2c_slave *wm = (i2c_slave *) opaque;
733 if (level)
734 i2c_set_slave_address(wm, SPITZ_WM_ADDRH);
735 else
736 i2c_set_slave_address(wm, SPITZ_WM_ADDRL);
737}
738
739static void spitz_i2c_setup(PXA2xxState *cpu)
740{
741
742 i2c_bus *bus = pxa2xx_i2c_bus(cpu->i2c[0]);
743
744 DeviceState *wm;
745
746
747 wm = i2c_create_slave(bus, "wm8750", 0);
748
749 spitz_wm8750_addr(wm, 0, 0);
750 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_WM,
751 qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
752
753 cpu->i2s->opaque = wm;
754 cpu->i2s->codec_out = wm8750_dac_dat;
755 cpu->i2s->codec_in = wm8750_adc_dat;
756 wm8750_data_req_set(wm, cpu->i2s->data_req, cpu->i2s);
757}
758
759static void spitz_akita_i2c_setup(PXA2xxState *cpu)
760{
761
762 i2c_create_slave(pxa2xx_i2c_bus(cpu->i2c[0]), "max7310",
763 AKITA_MAX_ADDR);
764}
765
766
767
768static void spitz_out_switch(void *opaque, int line, int level)
769{
770 switch (line) {
771 case 0:
772 zaurus_printf("Charging %s.\n", level ? "off" : "on");
773 break;
774 case 1:
775 zaurus_printf("Discharging %s.\n", level ? "on" : "off");
776 break;
777 case 2:
778 zaurus_printf("Green LED %s.\n", level ? "on" : "off");
779 break;
780 case 3:
781 zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
782 break;
783 case 4:
784 spitz_bl_bit5(opaque, line, level);
785 break;
786 case 5:
787 spitz_bl_power(opaque, line, level);
788 break;
789 case 6:
790 spitz_adc_temp_on(opaque, line, level);
791 break;
792 }
793}
794
795#define SPITZ_SCP_LED_GREEN 1
796#define SPITZ_SCP_JK_B 2
797#define SPITZ_SCP_CHRG_ON 3
798#define SPITZ_SCP_MUTE_L 4
799#define SPITZ_SCP_MUTE_R 5
800#define SPITZ_SCP_CF_POWER 6
801#define SPITZ_SCP_LED_ORANGE 7
802#define SPITZ_SCP_JK_A 8
803#define SPITZ_SCP_ADC_TEMP_ON 9
804#define SPITZ_SCP2_IR_ON 1
805#define SPITZ_SCP2_AKIN_PULLUP 2
806#define SPITZ_SCP2_BACKLIGHT_CONT 7
807#define SPITZ_SCP2_BACKLIGHT_ON 8
808#define SPITZ_SCP2_MIC_BIAS 9
809
810static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
811 DeviceState *scp0, DeviceState *scp1)
812{
813 qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
814
815 qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
816 qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
817 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
818 qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
819
820 if (scp1) {
821 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
822 qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
823 }
824
825 qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
826}
827
828#define SPITZ_GPIO_HSYNC 22
829#define SPITZ_GPIO_SD_DETECT 9
830#define SPITZ_GPIO_SD_WP 81
831#define SPITZ_GPIO_ON_RESET 89
832#define SPITZ_GPIO_BAT_COVER 90
833#define SPITZ_GPIO_CF1_IRQ 105
834#define SPITZ_GPIO_CF1_CD 94
835#define SPITZ_GPIO_CF2_IRQ 106
836#define SPITZ_GPIO_CF2_CD 93
837
838static int spitz_hsync;
839
840static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
841{
842 PXA2xxState *cpu = (PXA2xxState *) opaque;
843 qemu_set_irq(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_HSYNC), spitz_hsync);
844 spitz_hsync ^= 1;
845}
846
847static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
848{
849 qemu_irq lcd_hsync;
850
851
852
853
854
855
856 spitz_hsync = 0;
857 lcd_hsync = qemu_allocate_irqs(spitz_lcd_hsync_handler, cpu, 1)[0];
858 pxa2xx_gpio_read_notifier(cpu->gpio, lcd_hsync);
859 pxa2xx_lcd_vsync_notifier(cpu->lcd, lcd_hsync);
860
861
862 pxa2xx_mmci_handlers(cpu->mmc,
863 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_WP),
864 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_SD_DETECT));
865
866
867 qemu_irq_raise(qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_BAT_COVER));
868
869
870 qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ON_RESET, cpu->reset);
871
872
873 if (slots >= 1)
874 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[0],
875 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_IRQ),
876 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF1_CD));
877 if (slots >= 2)
878 pxa2xx_pcmcia_set_irq_cb(cpu->pcmcia[1],
879 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_IRQ),
880 qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_CF2_CD));
881}
882
883
884enum spitz_model_e { spitz, akita, borzoi, terrier };
885
886#define SPITZ_RAM 0x04000000
887#define SPITZ_ROM 0x00800000
888
889static struct arm_boot_info spitz_binfo = {
890 .loader_start = PXA2XX_SDRAM_BASE,
891 .ram_size = 0x04000000,
892};
893
894static void spitz_common_init(ram_addr_t ram_size,
895 const char *kernel_filename,
896 const char *kernel_cmdline, const char *initrd_filename,
897 const char *cpu_model, enum spitz_model_e model, int arm_id)
898{
899 PXA2xxState *cpu;
900 DeviceState *scp0, *scp1 = NULL;
901
902 if (!cpu_model)
903 cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
904
905
906 cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
907
908 sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
909
910 cpu_register_physical_memory(0, SPITZ_ROM,
911 qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM);
912
913
914 spitz_keyboard_register(cpu);
915
916 spitz_ssp_attach(cpu);
917
918 scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
919 if (model != akita) {
920 scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
921 }
922
923 spitz_scoop_gpio_setup(cpu, scp0, scp1);
924
925 spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);
926
927 spitz_i2c_setup(cpu);
928
929 if (model == akita)
930 spitz_akita_i2c_setup(cpu);
931
932 if (model == terrier)
933
934 spitz_microdrive_attach(cpu, 1);
935 else if (model != akita)
936
937 spitz_microdrive_attach(cpu, 0);
938
939 spitz_binfo.kernel_filename = kernel_filename;
940 spitz_binfo.kernel_cmdline = kernel_cmdline;
941 spitz_binfo.initrd_filename = initrd_filename;
942 spitz_binfo.board_id = arm_id;
943 arm_load_kernel(cpu->env, &spitz_binfo);
944 sl_bootparam_write(SL_PXA_PARAM_BASE);
945}
946
947static void spitz_init(ram_addr_t ram_size,
948 const char *boot_device,
949 const char *kernel_filename, const char *kernel_cmdline,
950 const char *initrd_filename, const char *cpu_model)
951{
952 spitz_common_init(ram_size, kernel_filename,
953 kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
954}
955
956static void borzoi_init(ram_addr_t ram_size,
957 const char *boot_device,
958 const char *kernel_filename, const char *kernel_cmdline,
959 const char *initrd_filename, const char *cpu_model)
960{
961 spitz_common_init(ram_size, kernel_filename,
962 kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
963}
964
965static void akita_init(ram_addr_t ram_size,
966 const char *boot_device,
967 const char *kernel_filename, const char *kernel_cmdline,
968 const char *initrd_filename, const char *cpu_model)
969{
970 spitz_common_init(ram_size, kernel_filename,
971 kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
972}
973
974static void terrier_init(ram_addr_t ram_size,
975 const char *boot_device,
976 const char *kernel_filename, const char *kernel_cmdline,
977 const char *initrd_filename, const char *cpu_model)
978{
979 spitz_common_init(ram_size, kernel_filename,
980 kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
981}
982
983static QEMUMachine akitapda_machine = {
984 .name = "akita",
985 .desc = "Akita PDA (PXA270)",
986 .init = akita_init,
987};
988
989static QEMUMachine spitzpda_machine = {
990 .name = "spitz",
991 .desc = "Spitz PDA (PXA270)",
992 .init = spitz_init,
993};
994
995static QEMUMachine borzoipda_machine = {
996 .name = "borzoi",
997 .desc = "Borzoi PDA (PXA270)",
998 .init = borzoi_init,
999};
1000
1001static QEMUMachine terrierpda_machine = {
1002 .name = "terrier",
1003 .desc = "Terrier PDA (PXA270)",
1004 .init = terrier_init,
1005};
1006
1007static void spitz_machine_init(void)
1008{
1009 qemu_register_machine(&akitapda_machine);
1010 qemu_register_machine(&spitzpda_machine);
1011 qemu_register_machine(&borzoipda_machine);
1012 qemu_register_machine(&terrierpda_machine);
1013}
1014
1015machine_init(spitz_machine_init);
1016
1017static bool is_version_0(void *opaque, int version_id)
1018{
1019 return version_id == 0;
1020}
1021
1022static VMStateDescription vmstate_sl_nand_info = {
1023 .name = "sl-nand",
1024 .version_id = 0,
1025 .minimum_version_id = 0,
1026 .minimum_version_id_old = 0,
1027 .fields = (VMStateField []) {
1028 VMSTATE_UINT8(ctl, SLNANDState),
1029 VMSTATE_STRUCT(ecc, SLNANDState, 0, vmstate_ecc_state, ECCState),
1030 VMSTATE_END_OF_LIST(),
1031 },
1032};
1033
1034static SysBusDeviceInfo sl_nand_info = {
1035 .init = sl_nand_init,
1036 .qdev.name = "sl-nand",
1037 .qdev.size = sizeof(SLNANDState),
1038 .qdev.vmsd = &vmstate_sl_nand_info,
1039 .qdev.props = (Property []) {
1040 DEFINE_PROP_UINT8("manf_id", SLNANDState, manf_id, NAND_MFR_SAMSUNG),
1041 DEFINE_PROP_UINT8("chip_id", SLNANDState, chip_id, 0xf1),
1042 DEFINE_PROP_END_OF_LIST(),
1043 },
1044};
1045
1046static VMStateDescription vmstate_spitz_kbd = {
1047 .name = "spitz-keyboard",
1048 .version_id = 1,
1049 .minimum_version_id = 0,
1050 .minimum_version_id_old = 0,
1051 .post_load = spitz_keyboard_post_load,
1052 .fields = (VMStateField []) {
1053 VMSTATE_UINT16(sense_state, SpitzKeyboardState),
1054 VMSTATE_UINT16(strobe_state, SpitzKeyboardState),
1055 VMSTATE_UNUSED_TEST(is_version_0, 5),
1056 VMSTATE_END_OF_LIST(),
1057 },
1058};
1059
1060static SysBusDeviceInfo spitz_keyboard_info = {
1061 .init = spitz_keyboard_init,
1062 .qdev.name = "spitz-keyboard",
1063 .qdev.size = sizeof(SpitzKeyboardState),
1064 .qdev.vmsd = &vmstate_spitz_kbd,
1065 .qdev.props = (Property []) {
1066 DEFINE_PROP_END_OF_LIST(),
1067 },
1068};
1069
1070static const VMStateDescription vmstate_corgi_ssp_regs = {
1071 .name = "corgi-ssp",
1072 .version_id = 1,
1073 .minimum_version_id = 1,
1074 .minimum_version_id_old = 1,
1075 .fields = (VMStateField []) {
1076 VMSTATE_UINT32_ARRAY(enable, CorgiSSPState, 3),
1077 VMSTATE_END_OF_LIST(),
1078 }
1079};
1080
1081static SSISlaveInfo corgi_ssp_info = {
1082 .qdev.name = "corgi-ssp",
1083 .qdev.size = sizeof(CorgiSSPState),
1084 .qdev.vmsd = &vmstate_corgi_ssp_regs,
1085 .init = corgi_ssp_init,
1086 .transfer = corgi_ssp_transfer
1087};
1088
1089static const VMStateDescription vmstate_spitz_lcdtg_regs = {
1090 .name = "spitz-lcdtg",
1091 .version_id = 1,
1092 .minimum_version_id = 1,
1093 .minimum_version_id_old = 1,
1094 .fields = (VMStateField []) {
1095 VMSTATE_UINT32(bl_intensity, SpitzLCDTG),
1096 VMSTATE_UINT32(bl_power, SpitzLCDTG),
1097 VMSTATE_END_OF_LIST(),
1098 }
1099};
1100
1101static SSISlaveInfo spitz_lcdtg_info = {
1102 .qdev.name = "spitz-lcdtg",
1103 .qdev.size = sizeof(SpitzLCDTG),
1104 .qdev.vmsd = &vmstate_spitz_lcdtg_regs,
1105 .init = spitz_lcdtg_init,
1106 .transfer = spitz_lcdtg_transfer
1107};
1108
1109static void spitz_register_devices(void)
1110{
1111 ssi_register_slave(&corgi_ssp_info);
1112 ssi_register_slave(&spitz_lcdtg_info);
1113 sysbus_register_withprop(&spitz_keyboard_info);
1114 sysbus_register_withprop(&sl_nand_info);
1115}
1116
1117device_init(spitz_register_devices)
1118
