/*
 *  S/390 translation
 *
 *  Copyright (c) 2009 Ulrich Hecht
 *  Copyright (c) 2010 Alexander Graf
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>

/* #define DEBUG_ILLEGAL_INSTRUCTIONS */
/* #define DEBUG_INLINE_BRANCHES */
#define S390X_DEBUG_DISAS
/* #define S390X_DEBUG_DISAS_VERBOSE */

#ifdef S390X_DEBUG_DISAS_VERBOSE
#  define LOG_DISAS(...) qemu_log(__VA_ARGS__)
#else
#  define LOG_DISAS(...) do { } while (0)
#endif

#include "cpu.h"
#include "disas.h"
#include "tcg-op.h"
#include "qemu-log.h"

/* global register indexes */
static TCGv_ptr cpu_env;

#include "gen-icount.h"
#include "helpers.h"
#define GEN_HELPER 1
#include "helpers.h"

typedef struct DisasContext DisasContext;
struct DisasContext {
    uint64_t pc;
    int is_jmp;
    enum cc_op cc_op;
    struct TranslationBlock *tb;
};

#define DISAS_EXCP 4

static void gen_op_calc_cc(DisasContext *s);

#ifdef DEBUG_INLINE_BRANCHES
static uint64_t inline_branch_hit[CC_OP_MAX];
static uint64_t inline_branch_miss[CC_OP_MAX];
#endif

static inline void debug_insn(uint64_t insn)
{
    LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
}

static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
{
    if (!(s->tb->flags & FLAG_MASK_64)) {
        if (s->tb->flags & FLAG_MASK_32) {
            return pc | 0x80000000;
        }
    }
    return pc;
}

void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
                    int flags)
{
    int i;

    for (i = 0; i < 16; i++) {
        cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
        if ((i % 4) == 3) {
            cpu_fprintf(f, "\n");
        } else {
            cpu_fprintf(f, " ");
        }
    }

    for (i = 0; i < 16; i++) {
        cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]);
        if ((i % 4) == 3) {
            cpu_fprintf(f, "\n");
        } else {
            cpu_fprintf(f, " ");
        }
    }

    cpu_fprintf(f, "\n");

#ifndef CONFIG_USER_ONLY
    for (i = 0; i < 16; i++) {
        cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
        if ((i % 4) == 3) {
            cpu_fprintf(f, "\n");
        } else {
            cpu_fprintf(f, " ");
        }
    }
#endif

    cpu_fprintf(f, "\n");

    if (env->cc_op > 3) {
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
                    env->psw.mask, env->psw.addr, cc_name(env->cc_op));
    } else {
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
                    env->psw.mask, env->psw.addr, env->cc_op);
    }

#ifdef DEBUG_INLINE_BRANCHES
    for (i = 0; i < CC_OP_MAX; i++) {
        cpu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
                    inline_branch_miss[i], inline_branch_hit[i]);
    }
#endif
}

static TCGv_i64 psw_addr;
static TCGv_i64 psw_mask;

static TCGv_i32 cc_op;
static TCGv_i64 cc_src;
static TCGv_i64 cc_dst;
static TCGv_i64 cc_vr;

static char cpu_reg_names[10*3 + 6*4];
static TCGv_i64 regs[16];

static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];

void s390x_translate_init(void)
{
    int i;
    size_t cpu_reg_names_size = sizeof(cpu_reg_names);
    char *p;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
    psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr),
                                      "psw_addr");
    psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask),
                                      "psw_mask");

    cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
                                   "cc_op");
    cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src),
                                    "cc_src");
    cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst),
                                    "cc_dst");
    cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr),
                                   "cc_vr");

    p = cpu_reg_names;
    for (i = 0; i < 16; i++) {
        snprintf(p, cpu_reg_names_size, "r%d", i);
        regs[i] = tcg_global_mem_new(TCG_AREG0,
                                     offsetof(CPUState, regs[i]), p);
        p += (i < 10) ? 3 : 4;
        cpu_reg_names_size -= (i < 10) ? 3 : 4;
    }
}

static inline TCGv_i64 load_reg(int reg)
{
    TCGv_i64 r = tcg_temp_new_i64();
    tcg_gen_mov_i64(r, regs[reg]);
    return r;
}

static inline TCGv_i64 load_freg(int reg)
{
    TCGv_i64 r = tcg_temp_new_i64();
    tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d));
    return r;
}

static inline TCGv_i32 load_freg32(int reg)
{
    TCGv_i32 r = tcg_temp_new_i32();
    tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
    return r;
}

static inline TCGv_i32 load_reg32(int reg)
{
    TCGv_i32 r = tcg_temp_new_i32();
    tcg_gen_trunc_i64_i32(r, regs[reg]);
    return r;
}

static inline TCGv_i64 load_reg32_i64(int reg)
{
    TCGv_i64 r = tcg_temp_new_i64();
    tcg_gen_ext32s_i64(r, regs[reg]);
    return r;
}

static inline void store_reg(int reg, TCGv_i64 v)
{
    tcg_gen_mov_i64(regs[reg], v);
}

static inline void store_freg(int reg, TCGv_i64 v)
{
    tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d));
}

static inline void store_reg32(int reg, TCGv_i32 v)
{
#if HOST_LONG_BITS == 32
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
#else
    TCGv_i64 tmp = tcg_temp_new_i64();
    tcg_gen_extu_i32_i64(tmp, v);
    /* 32 bit register writes keep the upper half */
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
    tcg_temp_free_i64(tmp);
#endif
}

static inline void store_reg32_i64(int reg, TCGv_i64 v)
{
    /* 32 bit register writes keep the upper half */
#if HOST_LONG_BITS == 32
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v));
#else
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
#endif
}

static inline void store_reg16(int reg, TCGv_i32 v)
{
    TCGv_i64 tmp = tcg_temp_new_i64();
    tcg_gen_extu_i32_i64(tmp, v);
    /* 16 bit register writes keep the upper bytes */
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16);
    tcg_temp_free_i64(tmp);
}

static inline void store_reg8(int reg, TCGv_i64 v)
{
    /* 8 bit register writes keep the upper bytes */
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8);
}

static inline void store_freg32(int reg, TCGv_i32 v)
{
    tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
}

static inline void update_psw_addr(DisasContext *s)
{
    /* psw.addr */
    tcg_gen_movi_i64(psw_addr, s->pc);
}

static inline void potential_page_fault(DisasContext *s)
{
#ifndef CONFIG_USER_ONLY
    update_psw_addr(s);
    gen_op_calc_cc(s);
#endif
}

static inline uint64_t ld_code2(uint64_t pc)
{
    return (uint64_t)lduw_code(pc);
}

static inline uint64_t ld_code4(uint64_t pc)
{
    return (uint64_t)ldl_code(pc);
}

static inline uint64_t ld_code6(uint64_t pc)
{
    uint64_t opc;
    opc = (uint64_t)lduw_code(pc) << 32;
    opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
    return opc;
}

static inline int get_mem_index(DisasContext *s)
{
    switch (s->tb->flags & FLAG_MASK_ASC) {
    case PSW_ASC_PRIMARY >> 32:
        return 0;
    case PSW_ASC_SECONDARY >> 32:
        return 1;
    case PSW_ASC_HOME >> 32:
        return 2;
    default:
        tcg_abort();
        break;
    }
}

static inline void gen_debug(DisasContext *s)
{
    TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
    update_psw_addr(s);
    gen_op_calc_cc(s);
    gen_helper_exception(tmp);
    tcg_temp_free_i32(tmp);
    s->is_jmp = DISAS_EXCP;
}

#ifdef CONFIG_USER_ONLY

static void gen_illegal_opcode(DisasContext *s, int ilc)
{
    TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
    update_psw_addr(s);
    gen_op_calc_cc(s);
    gen_helper_exception(tmp);
    tcg_temp_free_i32(tmp);
    s->is_jmp = DISAS_EXCP;
}

#else /* CONFIG_USER_ONLY */

static void debug_print_inst(DisasContext *s, int ilc)
{
#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
    uint64_t inst = 0;

    switch (ilc & 3) {
    case 1:
        inst = ld_code2(s->pc);
        break;
    case 2:
        inst = ld_code4(s->pc);
        break;
    case 3:
        inst = ld_code6(s->pc);
        break;
    }

    fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016"
            PRIx64 "\n", ilc, s->pc, inst);
#endif
}

static void gen_program_exception(DisasContext *s, int ilc, int code)
{
    TCGv_i32 tmp;

    debug_print_inst(s, ilc);

    /* remember what pgm exeption this was */
    tmp = tcg_const_i32(code);
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code));
    tcg_temp_free_i32(tmp);

    tmp = tcg_const_i32(ilc);
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc));
    tcg_temp_free_i32(tmp);

    /* advance past instruction */
    s->pc += (ilc * 2);
    update_psw_addr(s);

    /* save off cc */
    gen_op_calc_cc(s);

    /* trigger exception */
    tmp = tcg_const_i32(EXCP_PGM);
    gen_helper_exception(tmp);
    tcg_temp_free_i32(tmp);

    /* end TB here */
    s->is_jmp = DISAS_EXCP;
}


static void gen_illegal_opcode(DisasContext *s, int ilc)
{
    gen_program_exception(s, ilc, PGM_SPECIFICATION);
}

static void gen_privileged_exception(DisasContext *s, int ilc)
{
    gen_program_exception(s, ilc, PGM_PRIVILEGED);
}

static void check_privileged(DisasContext *s, int ilc)
{
    if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
        gen_privileged_exception(s, ilc);
    }
}

#endif /* CONFIG_USER_ONLY */

static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
{
    TCGv_i64 tmp;

    /* 31-bitify the immediate part; register contents are dealt with below */
    if (!(s->tb->flags & FLAG_MASK_64)) {
        d2 &= 0x7fffffffUL;
    }

    if (x2) {
        if (d2) {
            tmp = tcg_const_i64(d2);
            tcg_gen_add_i64(tmp, tmp, regs[x2]);
        } else {
            tmp = load_reg(x2);
        }
        if (b2) {
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
        }
    } else if (b2) {
        if (d2) {
            tmp = tcg_const_i64(d2);
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
        } else {
            tmp = load_reg(b2);
        }
    } else {
        tmp = tcg_const_i64(d2);
    }

    /* 31-bit mode mask if there are values loaded from registers */
    if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
        tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
    }

    return tmp;
}

static void gen_op_movi_cc(DisasContext *s, uint32_t val)
{
    s->cc_op = CC_OP_CONST0 + val;
}

static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
{
    tcg_gen_discard_i64(cc_src);
    tcg_gen_mov_i64(cc_dst, dst);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = op;
}

static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
{
    tcg_gen_discard_i64(cc_src);
    tcg_gen_extu_i32_i64(cc_dst, dst);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = op;
}

static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
                                  TCGv_i64 dst)
{
    tcg_gen_mov_i64(cc_src, src);
    tcg_gen_mov_i64(cc_dst, dst);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = op;
}

static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
                                  TCGv_i32 dst)
{
    tcg_gen_extu_i32_i64(cc_src, src);
    tcg_gen_extu_i32_i64(cc_dst, dst);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = op;
}

static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
                                  TCGv_i64 dst, TCGv_i64 vr)
{
    tcg_gen_mov_i64(cc_src, src);
    tcg_gen_mov_i64(cc_dst, dst);
    tcg_gen_mov_i64(cc_vr, vr);
    s->cc_op = op;
}

static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
                                  TCGv_i32 dst, TCGv_i32 vr)
{
    tcg_gen_extu_i32_i64(cc_src, src);
    tcg_gen_extu_i32_i64(cc_dst, dst);
    tcg_gen_extu_i32_i64(cc_vr, vr);
    s->cc_op = op;
}

static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
{
    gen_op_update1_cc_i32(s, CC_OP_NZ, val);
}

static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
{
    gen_op_update1_cc_i64(s, CC_OP_NZ, val);
}

static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
                          enum cc_op cond)
{
    gen_op_update2_cc_i32(s, cond, v1, v2);
}

static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
                          enum cc_op cond)
{
    gen_op_update2_cc_i64(s, cond, v1, v2);
}

static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
    cmp_32(s, v1, v2, CC_OP_LTGT_32);
}

static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
    cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
}

static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
{
    /* XXX optimize for the constant? put it in s? */
    TCGv_i32 tmp = tcg_const_i32(v2);
    cmp_32(s, v1, tmp, CC_OP_LTGT_32);
    tcg_temp_free_i32(tmp);
}

static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
{
    TCGv_i32 tmp = tcg_const_i32(v2);
    cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
    tcg_temp_free_i32(tmp);
}

static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
{
    cmp_64(s, v1, v2, CC_OP_LTGT_64);
}

static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
{
    cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
}

static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
{
    TCGv_i64 tmp = tcg_const_i64(v2);
    cmp_s64(s, v1, tmp);
    tcg_temp_free_i64(tmp);
}

static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
{
    TCGv_i64 tmp = tcg_const_i64(v2);
    cmp_u64(s, v1, tmp);
    tcg_temp_free_i64(tmp);
}

static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
{
    gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
}

static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
{
    gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
}

static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
{
    gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
}

static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
                          TCGv_i64 vr)
{
    gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr);
}

static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
{
    gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr);
}

static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
                          TCGv_i64 vr)
{
    gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr);
}

static void set_cc_abs64(DisasContext *s, TCGv_i64 v1)
{
    gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1);
}

static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
{
    gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
}

static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
{
    gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
}

static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
                          TCGv_i32 vr)
{
    gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
}

static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
{
    gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
}

static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
                          TCGv_i32 vr)
{
    gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr);
}

static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
{
    gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
}

static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1)
{
    gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1);
}

static void set_cc_comp32(DisasContext *s, TCGv_i32 v1)
{
    gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1);
}

static void set_cc_comp64(DisasContext *s, TCGv_i64 v1)
{
    gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1);
}

static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
{
    gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
}

static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
{
    tcg_gen_extu_i32_i64(cc_src, v1);
    tcg_gen_mov_i64(cc_dst, v2);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = CC_OP_LTGT_F32;
}

static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
{
    gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
}

static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
{
    gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
}

/* CC value is in env->cc_op */
static inline void set_cc_static(DisasContext *s)
{
    tcg_gen_discard_i64(cc_src);
    tcg_gen_discard_i64(cc_dst);
    tcg_gen_discard_i64(cc_vr);
    s->cc_op = CC_OP_STATIC;
}

static inline void gen_op_set_cc_op(DisasContext *s)
{
    if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
        tcg_gen_movi_i32(cc_op, s->cc_op);
    }
}

static inline void gen_update_cc_op(DisasContext *s)
{
    gen_op_set_cc_op(s);
}

/* calculates cc into cc_op */
static void gen_op_calc_cc(DisasContext *s)
{
    TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
    TCGv_i64 dummy = tcg_const_i64(0);

    switch (s->cc_op) {
    case CC_OP_CONST0:
    case CC_OP_CONST1:
    case CC_OP_CONST2:
    case CC_OP_CONST3:
        /* s->cc_op is the cc value */
        tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
        break;
    case CC_OP_STATIC:
        /* env->cc_op already is the cc value */
        break;
    case CC_OP_NZ:
    case CC_OP_ABS_64:
    case CC_OP_NABS_64:
    case CC_OP_ABS_32:
    case CC_OP_NABS_32:
    case CC_OP_LTGT0_32:
    case CC_OP_LTGT0_64:
    case CC_OP_COMP_32:
    case CC_OP_COMP_64:
    case CC_OP_NZ_F32:
    case CC_OP_NZ_F64:
        /* 1 argument */
        gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
        break;
    case CC_OP_ICM:
    case CC_OP_LTGT_32:
    case CC_OP_LTGT_64:
    case CC_OP_LTUGTU_32:
    case CC_OP_LTUGTU_64:
    case CC_OP_TM_32:
    case CC_OP_TM_64:
    case CC_OP_LTGT_F32:
    case CC_OP_LTGT_F64:
    case CC_OP_SLAG:
        /* 2 arguments */
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
        break;
    case CC_OP_ADD_64:
    case CC_OP_ADDU_64:
    case CC_OP_SUB_64:
    case CC_OP_SUBU_64:
    case CC_OP_ADD_32:
    case CC_OP_ADDU_32:
    case CC_OP_SUB_32:
    case CC_OP_SUBU_32:
        /* 3 arguments */
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
        break;
    case CC_OP_DYNAMIC:
        /* unknown operation - assume 3 arguments and cc_op in env */
        gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
        break;
    default:
        tcg_abort();
    }

    tcg_temp_free_i32(local_cc_op);

    /* We now have cc in cc_op as constant */
    set_cc_static(s);
}

static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
{
    debug_insn(insn);

    *r1 = (insn >> 4) & 0xf;
    *r2 = insn & 0xf;
}

static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
                                 int *x2, int *b2, int *d2)
{
    debug_insn(insn);

    *r1 = (insn >> 20) & 0xf;
    *x2 = (insn >> 16) & 0xf;
    *b2 = (insn >> 12) & 0xf;
    *d2 = insn & 0xfff;

    return get_address(s, *x2, *b2, *d2);
}

static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
                             int *b2, int *d2)
{
    debug_insn(insn);

    *r1 = (insn >> 20) & 0xf;
    /* aka m3 */
    *r3 = (insn >> 16) & 0xf;
    *b2 = (insn >> 12) & 0xf;
    *d2 = insn & 0xfff;
}

static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
                                 int *b1, int *d1)
{
    debug_insn(insn);

    *i2 = (insn >> 16) & 0xff;
    *b1 = (insn >> 12) & 0xf;
    *d1 = insn & 0xfff;

    return get_address(s, 0, *b1, *d1);
}

static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
{
    TranslationBlock *tb;

    gen_update_cc_op(s);

    tb = s->tb;
    /* NOTE: we handle the case where the TB spans two pages here */
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
        (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))  {
        /* jump to same page: we can use a direct jump */
        tcg_gen_goto_tb(tb_num);
        tcg_gen_movi_i64(psw_addr, pc);
        tcg_gen_exit_tb((long)tb + tb_num);
    } else {
        /* jump to another page: currently not optimized */
        tcg_gen_movi_i64(psw_addr, pc);
        tcg_gen_exit_tb(0);
    }
}

static inline void account_noninline_branch(DisasContext *s, int cc_op)
{
#ifdef DEBUG_INLINE_BRANCHES
    inline_branch_miss[cc_op]++;
#endif
}

static inline void account_inline_branch(DisasContext *s)
{
#ifdef DEBUG_INLINE_BRANCHES
    inline_branch_hit[s->cc_op]++;
#endif
}

static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
{
    TCGv_i32 tmp, tmp2, r;
    TCGv_i64 tmp64;
    int old_cc_op;

    switch (s->cc_op) {
    case CC_OP_LTGT0_32:
        tmp = tcg_temp_new_i32();
        tcg_gen_trunc_i64_i32(tmp, cc_dst);
        switch (mask) {
        case 0x8 | 0x4: /* dst <= 0 */
            tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
            break;
        case 0x8 | 0x2: /* dst >= 0 */
            tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
            break;
        case 0x8: /* dst == 0 */
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
            break;
        case 0x7: /* dst != 0 */
        case 0x6: /* dst != 0 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
            break;
        case 0x4: /* dst < 0 */
            tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
            break;
        case 0x2: /* dst > 0 */
            tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
            break;
        default:
            tcg_temp_free_i32(tmp);
            goto do_dynamic;
        }
        account_inline_branch(s);
        tcg_temp_free_i32(tmp);
        break;
    case CC_OP_LTGT0_64:
        switch (mask) {
        case 0x8 | 0x4: /* dst <= 0 */
            tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
            break;
        case 0x8 | 0x2: /* dst >= 0 */
            tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
            break;
        case 0x8: /* dst == 0 */
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
            break;
        case 0x7: /* dst != 0 */
        case 0x6: /* dst != 0 */
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
            break;
        case 0x4: /* dst < 0 */
            tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
            break;
        case 0x2: /* dst > 0 */
            tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
            break;
        default:
            goto do_dynamic;
        }
        account_inline_branch(s);
        break;
    case CC_OP_LTGT_32:
        tmp = tcg_temp_new_i32();
        tmp2 = tcg_temp_new_i32();
        tcg_gen_trunc_i64_i32(tmp, cc_src);
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
        switch (mask) {
        case 0x8 | 0x4: /* src <= dst */
            tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
            break;
        case 0x8 | 0x2: /* src >= dst */
            tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
            break;
        case 0x8: /* src == dst */
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
            break;
        case 0x7: /* src != dst */
        case 0x6: /* src != dst */
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
            break;
        case 0x4: /* src < dst */
            tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
            break;
        case 0x2: /* src > dst */
            tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
            break;
        default:
            tcg_temp_free_i32(tmp);
            tcg_temp_free_i32(tmp2);
            goto do_dynamic;
        }
        account_inline_branch(s);
        tcg_temp_free_i32(tmp);
        tcg_temp_free_i32(tmp2);
        break;
    case CC_OP_LTGT_64:
        switch (mask) {
        case 0x8 | 0x4: /* src <= dst */
            tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
            break;
        case 0x8 | 0x2: /* src >= dst */
            tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
            break;
        case 0x8: /* src == dst */
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
            break;
        case 0x7: /* src != dst */
        case 0x6: /* src != dst */
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
            break;
        case 0x4: /* src < dst */
            tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
            break;
        case 0x2: /* src > dst */
            tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
            break;
        default:
            goto do_dynamic;
        }
        account_inline_branch(s);
        break;
    case CC_OP_LTUGTU_32:
        tmp = tcg_temp_new_i32();
        tmp2 = tcg_temp_new_i32();
        tcg_gen_trunc_i64_i32(tmp, cc_src);
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
        switch (mask) {
        case 0x8 | 0x4: /* src <= dst */
            tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
            break;
        case 0x8 | 0x2: /* src >= dst */
            tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
            break;
        case 0x8: /* src == dst */
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
            break;
        case 0x7: /* src != dst */
        case 0x6: /* src != dst */
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
            break;
        case 0x4: /* src < dst */
            tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
            break;
        case 0x2: /* src > dst */

            tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
            break;
        default:
            tcg_temp_free_i32(tmp);
            tcg_temp_free_i32(tmp2);
            goto do_dynamic;
        }
        account_inline_branch(s);
        tcg_temp_free_i32(tmp);
        tcg_temp_free_i32(tmp2);
        break;
    case CC_OP_LTUGTU_64:
        switch (mask) {
        case 0x8 | 0x4: /* src <= dst */
            tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip);
            break;
        case 0x8 | 0x2: /* src >= dst */
            tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip);
            break;
        case 0x8: /* src == dst */
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
            break;
        case 0x7: /* src != dst */
        case 0x6: /* src != dst */
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
            break;
        case 0x4: /* src < dst */
            tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip);
            break;
        case 0x2: /* src > dst */
            tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip);
            break;
        default:
            goto do_dynamic;
        }
        account_inline_branch(s);
        break;
    case CC_OP_NZ:
        switch (mask) {
        /* dst == 0 || dst != 0 */
        case 0x8 | 0x4:
        case 0x8 | 0x4 | 0x2:
        case 0x8 | 0x4 | 0x2 | 0x1:
        case 0x8 | 0x4 | 0x1:
            break;
        /* dst == 0 */
        case 0x8:
        case 0x8 | 0x2:
        case 0x8 | 0x2 | 0x1:
        case 0x8 | 0x1:
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
            break;
        /* dst != 0 */
        case 0x4:
        case 0x4 | 0x2:
        case 0x4 | 0x2 | 0x1:
        case 0x4 | 0x1:
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
            break;
        default:
            goto do_dynamic;
        }
        account_inline_branch(s);
        break;
    case CC_OP_TM_32:
        tmp = tcg_temp_new_i32();
        tmp2 = tcg_temp_new_i32();

        tcg_gen_trunc_i64_i32(tmp, cc_src);
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
        tcg_gen_and_i32(tmp, tmp, tmp2);
        switch (mask) {
        case 0x8: /* val & mask == 0 */
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
            break;
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
            break;
        default:
            tcg_temp_free_i32(tmp);
            tcg_temp_free_i32(tmp2);
            goto do_dynamic;
        }
        tcg_temp_free_i32(tmp);
        tcg_temp_free_i32(tmp2);
        account_inline_branch(s);
        break;
    case CC_OP_TM_64:
        tmp64 = tcg_temp_new_i64();

        tcg_gen_and_i64(tmp64, cc_src, cc_dst);
        switch (mask) {
        case 0x8: /* val & mask == 0 */
            tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip);
            break;
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
            tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip);
            break;
        default:
            tcg_temp_free_i64(tmp64);
            goto do_dynamic;
        }
        tcg_temp_free_i64(tmp64);
        account_inline_branch(s);
        break;
    case CC_OP_ICM:
        switch (mask) {
        case 0x8: /* val == 0 */
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
            break;
        case 0x4 | 0x2 | 0x1: /* val != 0 */
        case 0x4 | 0x2: /* val != 0 */
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
            break;
        default:
            goto do_dynamic;
        }
        account_inline_branch(s);
        break;
    case CC_OP_STATIC:
        old_cc_op = s->cc_op;
        goto do_dynamic_nocccalc;
    case CC_OP_DYNAMIC:
    default:
do_dynamic:
        old_cc_op = s->cc_op;
        /* calculate cc value */
        gen_op_calc_cc(s);

do_dynamic_nocccalc:
        /* jump based on cc */
        account_noninline_branch(s, old_cc_op);

        switch (mask) {
        case 0x8 | 0x4 | 0x2 | 0x1:
            /* always true */
            break;
        case 0x8 | 0x4 | 0x2: /* cc != 3 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip);
            break;
        case 0x8 | 0x4 | 0x1: /* cc != 2 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip);
            break;
        case 0x8 | 0x2 | 0x1: /* cc != 1 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip);
            break;
        case 0x8 | 0x2: /* cc == 0 || cc == 2 */
            tmp = tcg_temp_new_i32();
            tcg_gen_andi_i32(tmp, cc_op, 1);
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
            tcg_temp_free_i32(tmp);
            break;
        case 0x8 | 0x4: /* cc < 2 */
            tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip);
            break;
        case 0x8: /* cc == 0 */
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip);
            break;
        case 0x4 | 0x2 | 0x1: /* cc != 0 */
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip);
            break;
        case 0x4 | 0x1: /* cc == 1 || cc == 3 */
            tmp = tcg_temp_new_i32();
            tcg_gen_andi_i32(tmp, cc_op, 1);
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
            tcg_temp_free_i32(tmp);
            break;
        case 0x4: /* cc == 1 */
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip);
            break;
        case 0x2 | 0x1: /* cc > 1 */
            tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip);
            break;
        case 0x2: /* cc == 2 */
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip);
            break;
        case 0x1: /* cc == 3 */
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip);
            break;
        default: /* cc is masked by something else */
            tmp = tcg_const_i32(3);
            /* 3 - cc */
            tcg_gen_sub_i32(tmp, tmp, cc_op);
            tmp2 = tcg_const_i32(1);
            /* 1 << (3 - cc) */
            tcg_gen_shl_i32(tmp2, tmp2, tmp);
            r = tcg_const_i32(mask);
            /* mask & (1 << (3 - cc)) */
            tcg_gen_and_i32(r, r, tmp2);
            tcg_temp_free_i32(tmp);
            tcg_temp_free_i32(tmp2);

            tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip);
            tcg_temp_free_i32(r);
            break;
        }
        break;
    }
}

static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
                    uint64_t offset)
{
    int skip;

    if (mask == 0xf) {
        /* unconditional */
        tcg_gen_mov_i64(psw_addr, target);
        tcg_gen_exit_tb(0);
    } else if (mask == 0) {
        /* ignore cc and never match */
        gen_goto_tb(s, 0, offset + 2);
    } else {
        TCGv_i64 new_addr = tcg_temp_local_new_i64();

        tcg_gen_mov_i64(new_addr, target);
        skip = gen_new_label();
        gen_jcc(s, mask, skip);
        tcg_gen_mov_i64(psw_addr, new_addr);
        tcg_temp_free_i64(new_addr);
        tcg_gen_exit_tb(0);
        gen_set_label(skip);
        tcg_temp_free_i64(new_addr);
        gen_goto_tb(s, 1, offset + 2);
    }
}

static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset)
{
    int skip;

    if (mask == 0xf) {
        /* unconditional */
        gen_goto_tb(s, 0, s->pc + offset);
    } else if (mask == 0) {
        /* ignore cc and never match */
        gen_goto_tb(s, 0, s->pc + 4);
    } else {
        skip = gen_new_label();
        gen_jcc(s, mask, skip);
        gen_goto_tb(s, 0, s->pc + offset);
        gen_set_label(skip);
        gen_goto_tb(s, 1, s->pc + 4);
    }
    s->is_jmp = DISAS_TB_JUMP;
}

static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
{
    TCGv_i64 tmp, tmp2;
    int i;
    int l_memset = gen_new_label();
    int l_out = gen_new_label();
    TCGv_i64 dest = tcg_temp_local_new_i64();
    TCGv_i64 src = tcg_temp_local_new_i64();
    TCGv_i32 vl;

    /* Find out if we should use the inline version of mvc */
    switch (l) {
    case 0:
    case 1:
    case 2:
    case 3:
    case 4:
    case 5:
    case 6:
    case 7:
    case 11:
    case 15:
        /* use inline */
        break;
    default:
        /* Fall back to helper */
        vl = tcg_const_i32(l);
        potential_page_fault(s);
        gen_helper_mvc(vl, s1, s2);
        tcg_temp_free_i32(vl);
        return;
    }

    tcg_gen_mov_i64(dest, s1);
    tcg_gen_mov_i64(src, s2);

    if (!(s->tb->flags & FLAG_MASK_64)) {
        /* XXX what if we overflow while moving? */
        tcg_gen_andi_i64(dest, dest, 0x7fffffffUL);
        tcg_gen_andi_i64(src, src, 0x7fffffffUL);
    }

    tmp = tcg_temp_new_i64();
    tcg_gen_addi_i64(tmp, src, 1);
    tcg_gen_brcond_i64(TCG_COND_EQ, dest, tmp, l_memset);
    tcg_temp_free_i64(tmp);

    switch (l) {
    case 0:
        tmp = tcg_temp_new_i64();

        tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));

        tcg_temp_free_i64(tmp);
        break;
    case 1:
        tmp = tcg_temp_new_i64();

        tcg_gen_qemu_ld16u(tmp, src, get_mem_index(s));
        tcg_gen_qemu_st16(tmp, dest, get_mem_index(s));

        tcg_temp_free_i64(tmp);
        break;
    case 3:
        tmp = tcg_temp_new_i64();

        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));

        tcg_temp_free_i64(tmp);
        break;
    case 4:
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_temp_new_i64();

        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
        tcg_gen_addi_i64(src, src, 4);
        tcg_gen_qemu_ld8u(tmp2, src, get_mem_index(s));
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
        tcg_gen_addi_i64(dest, dest, 4);
        tcg_gen_qemu_st8(tmp2, dest, get_mem_index(s));

        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 7:
        tmp = tcg_temp_new_i64();

        tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));

        tcg_temp_free_i64(tmp);
        break;
    default:
        /* The inline version can become too big for too uneven numbers, only
           use it on known good lengths */
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_const_i64(8);
        for (i = 0; (i + 7) <= l; i += 8) {
            tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
            tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));

            tcg_gen_add_i64(src, src, tmp2);
            tcg_gen_add_i64(dest, dest, tmp2);
        }

        tcg_temp_free_i64(tmp2);
        tmp2 = tcg_const_i64(1);

        for (; i <= l; i++) {
            tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
            tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));

            tcg_gen_add_i64(src, src, tmp2);
            tcg_gen_add_i64(dest, dest, tmp2);
        }

        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp);
        break;
    }

    tcg_gen_br(l_out);

    gen_set_label(l_memset);
    /* memset case (dest == (src + 1)) */

    tmp = tcg_temp_new_i64();
    tmp2 = tcg_temp_new_i64();
    /* fill tmp with the byte */
    tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
    tcg_gen_shli_i64(tmp2, tmp, 8);
    tcg_gen_or_i64(tmp, tmp, tmp2);
    tcg_gen_shli_i64(tmp2, tmp, 16);
    tcg_gen_or_i64(tmp, tmp, tmp2);
    tcg_gen_shli_i64(tmp2, tmp, 32);
    tcg_gen_or_i64(tmp, tmp, tmp2);
    tcg_temp_free_i64(tmp2);

    tmp2 = tcg_const_i64(8);

    for (i = 0; (i + 7) <= l; i += 8) {
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
        tcg_gen_addi_i64(dest, dest, 8);
    }

    tcg_temp_free_i64(tmp2);
    tmp2 = tcg_const_i64(1);

    for (; i <= l; i++) {
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
        tcg_gen_addi_i64(dest, dest, 1);
    }

    tcg_temp_free_i64(tmp2);
    tcg_temp_free_i64(tmp);

    gen_set_label(l_out);

    tcg_temp_free(dest);
    tcg_temp_free(src);
}

static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
{
    TCGv_i64 tmp;
    TCGv_i64 tmp2;
    TCGv_i32 vl;

    /* check for simple 32bit or 64bit match */
    switch (l) {
    case 0:
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_temp_new_i64();

        tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s));
        tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s));
        cmp_u64(s, tmp, tmp2);

        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        return;
    case 1:
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_temp_new_i64();

        tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s));
        tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s));
        cmp_u64(s, tmp, tmp2);

        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        return;
    case 3:
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_temp_new_i64();

        tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s));
        tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s));
        cmp_u64(s, tmp, tmp2);

        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        return;
    case 7:
        tmp = tcg_temp_new_i64();
        tmp2 = tcg_temp_new_i64();

        tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s));
        tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s));
        cmp_u64(s, tmp, tmp2);

        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        return;
    }

    potential_page_fault(s);
    vl = tcg_const_i32(l);
    gen_helper_clc(cc_op, vl, s1, s2);
    tcg_temp_free_i32(vl);
    set_cc_static(s);
}

static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
{
    TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;

    LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
              op, r1, x2, b2, d2);
    addr = get_address(s, x2, b2, d2);
    switch (op) {
    case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
    case 0x4: /* lg r1,d2(x2,b2) */
        tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s));
        if (op == 0x2) {
            set_cc_s64(s, regs[r1]);
        }
        break;
    case 0x12: /* LT R1,D2(X2,B2) [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
        store_reg32(r1, tmp32_1);
        set_cc_s32(s, tmp32_1);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0xc: /* MSG      R1,D2(X2,B2)     [RXY] */
    case 0x1c: /* MSGF     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        if (op == 0xc) {
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        } else {
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        }
        tcg_gen_mul_i64(regs[r1], regs[r1], tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0xd: /* DSG      R1,D2(X2,B2)     [RXY] */
    case 0x1d: /* DSGF      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        if (op == 0x1d) {
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        } else {
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        }
        tmp4 = load_reg(r1 + 1);
        tmp3 = tcg_temp_new_i64();
        tcg_gen_div_i64(tmp3, tmp4, tmp2);
        store_reg(r1 + 1, tmp3);
        tcg_gen_rem_i64(tmp3, tmp4, tmp2);
        store_reg(r1, tmp3);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        tcg_temp_free_i64(tmp4);
        break;
    case 0x8: /* AG      R1,D2(X2,B2)     [RXY] */
    case 0xa: /* ALG      R1,D2(X2,B2)     [RXY] */
    case 0x18: /* AGF       R1,D2(X2,B2)     [RXY] */
    case 0x1a: /* ALGF      R1,D2(X2,B2)     [RXY] */
        if (op == 0x1a) {
            tmp2 = tcg_temp_new_i64();
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        } else if (op == 0x18) {
            tmp2 = tcg_temp_new_i64();
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        } else {
            tmp2 = tcg_temp_new_i64();
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        }
        tmp4 = load_reg(r1);
        tmp3 = tcg_temp_new_i64();
        tcg_gen_add_i64(tmp3, tmp4, tmp2);
        store_reg(r1, tmp3);
        switch (op) {
        case 0x8:
        case 0x18:
            set_cc_add64(s, tmp4, tmp2, tmp3);
            break;
        case 0xa:
        case 0x1a:
            set_cc_addu64(s, tmp4, tmp2, tmp3);
            break;
        default:
            tcg_abort();
        }
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        tcg_temp_free_i64(tmp4);
        break;
    case 0x9: /* SG      R1,D2(X2,B2)     [RXY] */
    case 0xb: /* SLG      R1,D2(X2,B2)     [RXY] */
    case 0x19: /* SGF      R1,D2(X2,B2)     [RXY] */
    case 0x1b: /* SLGF     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        if (op == 0x19) {
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        } else if (op == 0x1b) {
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        } else {
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        }
        tmp4 = load_reg(r1);
        tmp3 = tcg_temp_new_i64();
        tcg_gen_sub_i64(tmp3, tmp4, tmp2);
        store_reg(r1, tmp3);
        switch (op) {
        case 0x9:
        case 0x19:
            set_cc_sub64(s, tmp4, tmp2, tmp3);
            break;
        case 0xb:
        case 0x1b:
            set_cc_subu64(s, tmp4, tmp2, tmp3);
            break;
        default:
            tcg_abort();
        }
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        tcg_temp_free_i64(tmp4);
        break;
    case 0xf: /* LRVG     R1,D2(X2,B2)     [RXE] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        tcg_gen_bswap64_i64(tmp2, tmp2);
        store_reg(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x14: /* LGF      R1,D2(X2,B2)     [RXY] */
    case 0x16: /* LLGF      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        if (op == 0x14) {
            tcg_gen_ext32s_i64(tmp2, tmp2);
        }
        store_reg(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x15: /* LGH     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
        store_reg(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x17: /* LLGT      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL);
        store_reg(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
        store_reg16(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x20: /* CG      R1,D2(X2,B2)     [RXY] */
    case 0x21: /* CLG      R1,D2(X2,B2) */
    case 0x30: /* CGF       R1,D2(X2,B2)     [RXY] */
    case 0x31: /* CLGF      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        switch (op) {
        case 0x20:
        case 0x21:
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
            break;
        case 0x30:
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
            break;
        case 0x31:
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
            break;
        default:
            tcg_abort();
        }
        switch (op) {
        case 0x20:
        case 0x30:
            cmp_s64(s, regs[r1], tmp2);
            break;
        case 0x21:
        case 0x31:
            cmp_u64(s, regs[r1], tmp2);
            break;
        default:
            tcg_abort();
        }
        tcg_temp_free_i64(tmp2);
        break;
    case 0x24: /* stg r1, d2(x2,b2) */
        tcg_gen_qemu_st64(regs[r1], addr, get_mem_index(s));
        break;
    case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
        tmp32_1 = load_reg32(r1);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
        tcg_temp_free_i64(tmp2);
        break;
    case 0x50: /* STY  R1,D2(X2,B2) [RXY] */
        tmp32_1 = load_reg32(r1);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
        tcg_temp_free_i64(tmp2);
        break;
    case 0x57: /* XY R1,D2(X2,B2) [RXY] */
        tmp32_1 = load_reg32(r1);
        tmp32_2 = tcg_temp_new_i32();
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_gen_xor_i32(tmp32_2, tmp32_1, tmp32_2);
        store_reg32(r1, tmp32_2);
        set_cc_nz_u32(s, tmp32_2);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x58: /* LY R1,D2(X2,B2) [RXY] */
        tmp3 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32u(tmp3, addr, get_mem_index(s));
        store_reg32_i64(r1, tmp3);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x5a: /* AY R1,D2(X2,B2) [RXY] */
    case 0x5b: /* SY R1,D2(X2,B2) [RXY] */
        tmp32_1 = load_reg32(r1);
        tmp32_2 = tcg_temp_new_i32();
        tmp32_3 = tcg_temp_new_i32();
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
        tcg_temp_free_i64(tmp2);
        switch (op) {
        case 0x5a:
            tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
            break;
        case 0x5b:
            tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
            break;
        default:
            tcg_abort();
        }
        store_reg32(r1, tmp32_3);
        switch (op) {
        case 0x5a:
            set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
            break;
        case 0x5b:
            set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
            break;
        default:
            tcg_abort();
        }
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        break;
    case 0x71: /* LAY R1,D2(X2,B2) [RXY] */
        store_reg(r1, addr);
        break;
    case 0x72: /* STCY R1,D2(X2,B2) [RXY] */
        tmp32_1 = load_reg32(r1);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_ext_i32_i64(tmp2, tmp32_1);
        tcg_gen_qemu_st8(tmp2, addr, get_mem_index(s));
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x73: /* ICY R1,D2(X2,B2) [RXY] */
        tmp3 = tcg_temp_new_i64();
        tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s));
        store_reg8(r1, tmp3);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x76: /* LB R1,D2(X2,B2) [RXY] */
    case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld8s(tmp2, addr, get_mem_index(s));
        switch (op) {
        case 0x76:
            tcg_gen_ext8s_i64(tmp2, tmp2);
            store_reg32_i64(r1, tmp2);
            break;
        case 0x77:
            tcg_gen_ext8s_i64(tmp2, tmp2);
            store_reg(r1, tmp2);
            break;
        default:
            tcg_abort();
        }
        tcg_temp_free_i64(tmp2);
        break;
    case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
        store_reg32_i64(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x80: /* NG      R1,D2(X2,B2)     [RXY] */
    case 0x81: /* OG      R1,D2(X2,B2)     [RXY] */
    case 0x82: /* XG      R1,D2(X2,B2)     [RXY] */
        tmp3 = tcg_temp_new_i64();
        tcg_gen_qemu_ld64(tmp3, addr, get_mem_index(s));
        switch (op) {
        case 0x80:
            tcg_gen_and_i64(regs[r1], regs[r1], tmp3);
            break;
        case 0x81:
            tcg_gen_or_i64(regs[r1], regs[r1], tmp3);
            break;
        case 0x82:
            tcg_gen_xor_i64(regs[r1], regs[r1], tmp3);
            break;
        default:
            tcg_abort();
        }
        set_cc_nz_u64(s, regs[r1]);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x86: /* MLG      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_const_i32(r1);
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        gen_helper_mlg(tmp32_1, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x87: /* DLG      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_const_i32(r1);
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        gen_helper_dlg(tmp32_1, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x88: /* ALCG      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp3 = tcg_temp_new_i64();
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        /* XXX possible optimization point */
        gen_op_calc_cc(s);
        tcg_gen_extu_i32_i64(tmp3, cc_op);
        tcg_gen_shri_i64(tmp3, tmp3, 1);
        tcg_gen_andi_i64(tmp3, tmp3, 1);
        tcg_gen_add_i64(tmp3, tmp2, tmp3);
        tcg_gen_add_i64(tmp3, regs[r1], tmp3);
        store_reg(r1, tmp3);
        set_cc_addu64(s, regs[r1], tmp2, tmp3);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x89: /* SLBG      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_const_i32(r1);
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
        /* XXX possible optimization point */
        gen_op_calc_cc(s);
        gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x90: /* LLGC      R1,D2(X2,B2)     [RXY] */
        tcg_gen_qemu_ld8u(regs[r1], addr, get_mem_index(s));
        break;
    case 0x91: /* LLGH      R1,D2(X2,B2)     [RXY] */
        tcg_gen_qemu_ld16u(regs[r1], addr, get_mem_index(s));
        break;
    case 0x94: /* LLC     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld8u(tmp2, addr, get_mem_index(s));
        store_reg32_i64(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x95: /* LLH     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
        store_reg32_i64(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x96: /* ML      R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp3 = load_reg((r1 + 1) & 15);
        tcg_gen_ext32u_i64(tmp3, tmp3);
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_mul_i64(tmp2, tmp2, tmp3);
        store_reg32_i64((r1 + 1) & 15, tmp2);
        tcg_gen_shri_i64(tmp2, tmp2, 32);
        store_reg32_i64(r1, tmp2);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x97: /* DL     R1,D2(X2,B2)     [RXY] */
        /* reg(r1) = reg(r1, r1+1) % ld32(addr) */
        /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
        tmp = load_reg(r1);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tmp3 = load_reg((r1 + 1) & 15);
        tcg_gen_ext32u_i64(tmp2, tmp2);
        tcg_gen_ext32u_i64(tmp3, tmp3);
        tcg_gen_shli_i64(tmp, tmp, 32);
        tcg_gen_or_i64(tmp, tmp, tmp3);

        tcg_gen_rem_i64(tmp3, tmp, tmp2);
        tcg_gen_div_i64(tmp, tmp, tmp2);
        store_reg32_i64((r1 + 1) & 15, tmp);
        store_reg32_i64(r1, tmp3);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x98: /* ALC     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = load_reg32(r1);
        tmp32_2 = tcg_temp_new_i32();
        tmp32_3 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
        /* XXX possible optimization point */
        gen_op_calc_cc(s);
        gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2);
        set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
        store_reg32(r1, tmp32_3);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        break;
    case 0x99: /* SLB     R1,D2(X2,B2)     [RXY] */
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
        /* XXX possible optimization point */
        gen_op_calc_cc(s);
        gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    default:
        LOG_DISAS("illegal e3 operation 0x%x\n", op);
        gen_illegal_opcode(s, 3);
        break;
    }
    tcg_temp_free_i64(addr);
}

#ifndef CONFIG_USER_ONLY
static void disas_e5(DisasContext* s, uint64_t insn)
{
    TCGv_i64 tmp, tmp2;
    int op = (insn >> 32) & 0xff;

    tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff);
    tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff);

    LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn);
    switch (op) {
    case 0x01: /* TPROT    D1(B1),D2(B2)  [SSE] */
        /* Test Protection */
        potential_page_fault(s);
        gen_helper_tprot(cc_op, tmp, tmp2);
        set_cc_static(s);
        break;
    default:
        LOG_DISAS("illegal e5 operation 0x%x\n", op);
        gen_illegal_opcode(s, 3);
        break;
    }

    tcg_temp_free_i64(tmp);
    tcg_temp_free_i64(tmp2);
}
#endif

static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2)
{
    TCGv_i64 tmp, tmp2, tmp3, tmp4;
    TCGv_i32 tmp32_1, tmp32_2;
    int i, stm_len;
    int ilc = 3;

    LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
              op, r1, r3, b2, d2);
    switch (op) {
    case 0xc: /* SRLG     R1,R3,D2(B2)     [RSY] */
    case 0xd: /* SLLG     R1,R3,D2(B2)     [RSY] */
    case 0xa: /* SRAG     R1,R3,D2(B2)     [RSY] */
    case 0xb: /* SLAG     R1,R3,D2(B2)     [RSY] */
    case 0x1c: /* RLLG     R1,R3,D2(B2)     [RSY] */
        if (b2) {
            tmp = get_address(s, 0, b2, d2);
            tcg_gen_andi_i64(tmp, tmp, 0x3f);
        } else {
            tmp = tcg_const_i64(d2 & 0x3f);
        }
        switch (op) {
        case 0xc:
            tcg_gen_shr_i64(regs[r1], regs[r3], tmp);
            break;
        case 0xd:
            tcg_gen_shl_i64(regs[r1], regs[r3], tmp);
            break;
        case 0xa:

            tcg_gen_sar_i64(regs[r1], regs[r3], tmp);
            break;
        case 0xb:
            tmp2 = tcg_temp_new_i64();
            tmp3 = tcg_temp_new_i64();
            gen_op_update2_cc_i64(s, CC_OP_SLAG, regs[r3], tmp);
            tcg_gen_shl_i64(tmp2, regs[r3], tmp);
            /* override sign bit with source sign */
            tcg_gen_andi_i64(tmp2, tmp2, ~0x8000000000000000ULL);
            tcg_gen_andi_i64(tmp3, regs[r3], 0x8000000000000000ULL);
            tcg_gen_or_i64(regs[r1], tmp2, tmp3);
            tcg_temp_free_i64(tmp2);
            tcg_temp_free_i64(tmp3);
            break;
        case 0x1c:
            tcg_gen_rotl_i64(regs[r1], regs[r3], tmp);
            break;
        default:
            tcg_abort();
            break;
        }
        if (op == 0xa) {
            set_cc_s64(s, regs[r1]);
        }
        tcg_temp_free_i64(tmp);
        break;
    case 0x1d: /* RLL    R1,R3,D2(B2)        [RSY] */
        if (b2) {
            tmp = get_address(s, 0, b2, d2);
            tcg_gen_andi_i64(tmp, tmp, 0x3f);
        } else {
            tmp = tcg_const_i64(d2 & 0x3f);
        }
        tmp32_1 = tcg_temp_new_i32();
        tmp32_2 = load_reg32(r3);
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
        switch (op) {
        case 0x1d:
            tcg_gen_rotl_i32(tmp32_1, tmp32_2, tmp32_1);
            break;
        default:
            tcg_abort();
            break;
        }
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x4:  /* LMG      R1,R3,D2(B2)     [RSE] */
    case 0x24: /* STMG     R1,R3,D2(B2)     [RSE] */
        stm_len = 8;
        goto do_mh;
    case 0x26: /* STMH     R1,R3,D2(B2)     [RSE] */
    case 0x96: /* LMH      R1,R3,D2(B2)     [RSE] */
        stm_len = 4;
do_mh:
        /* Apparently, unrolling lmg/stmg of any size gains performance -
           even for very long ones... */
        tmp = get_address(s, 0, b2, d2);
        tmp3 = tcg_const_i64(stm_len);
        tmp4 = tcg_const_i64(op == 0x26 ? 32 : 4);
        for (i = r1;; i = (i + 1) % 16) {
            switch (op) {
            case 0x4:
                tcg_gen_qemu_ld64(regs[i], tmp, get_mem_index(s));
                break;
            case 0x96:
                tmp2 = tcg_temp_new_i64();
#if HOST_LONG_BITS == 32
                tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
                tcg_gen_trunc_i64_i32(TCGV_HIGH(regs[i]), tmp2);
#else
                tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
                tcg_gen_shl_i64(tmp2, tmp2, tmp4);
                tcg_gen_ext32u_i64(regs[i], regs[i]);
                tcg_gen_or_i64(regs[i], regs[i], tmp2);
#endif
                tcg_temp_free_i64(tmp2);
                break;
            case 0x24:
                tcg_gen_qemu_st64(regs[i], tmp, get_mem_index(s));
                break;
            case 0x26:
                tmp2 = tcg_temp_new_i64();
                tcg_gen_shr_i64(tmp2, regs[i], tmp4);
                tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
                tcg_temp_free_i64(tmp2);
                break;
            default:
                tcg_abort();
            }
            if (i == r3) {
                break;
            }
            tcg_gen_add_i64(tmp, tmp, tmp3);
        }
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp3);
        tcg_temp_free_i64(tmp4);
        break;
    case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        gen_helper_stcmh(tmp32_1, tmp, tmp32_2);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
#ifndef CONFIG_USER_ONLY
    case 0x2f: /* LCTLG     R1,R3,D2(B2)     [RSE] */
        /* Load Control */
        check_privileged(s, ilc);
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        gen_helper_lctlg(tmp32_1, tmp, tmp32_2);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x25: /* STCTG     R1,R3,D2(B2)     [RSE] */
        /* Store Control */
        check_privileged(s, ilc);
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        gen_helper_stctg(tmp32_1, tmp, tmp32_2);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
#endif
    case 0x30: /* CSG     R1,R3,D2(B2)     [RSY] */
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        /* XXX rewrite in tcg */
        gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        /* XXX rewrite in tcg */
        gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x51: /* TMY D1(B1),I2 [SIY] */
        tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
        tmp2 = tcg_const_i64((r1 << 4) | r3);
        tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
        /* yes, this is a 32 bit operation with 64 bit tcg registers, because
           that incurs less conversions */
        cmp_64(s, tmp, tmp2, CC_OP_TM_32);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x52: /* MVIY D1(B1),I2 [SIY] */
        tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
        tmp2 = tcg_const_i64((r1 << 4) | r3);
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x55: /* CLIY D1(B1),I2 [SIY] */
        tmp3 = get_address(s, 0, b2, d2); /* SIY -> this is the 1st operand */
        tmp = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_qemu_ld8u(tmp, tmp3, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
        cmp_u32c(s, tmp32_1, (r1 << 4) | r3);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp3);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x80: /* ICMH      R1,M3,D2(B2)     [RSY] */
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r3);
        potential_page_fault(s);
        /* XXX split CC calculation out */
        gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    default:
        LOG_DISAS("illegal eb operation 0x%x\n", op);
        gen_illegal_opcode(s, ilc);
        break;
    }
}

static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
                     int r1b)
{
    TCGv_i32 tmp_r1, tmp32;
    TCGv_i64 addr, tmp;
    addr = get_address(s, x2, b2, d2);
    tmp_r1 = tcg_const_i32(r1);
    switch (op) {
    case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
        potential_page_fault(s);
        gen_helper_lxdb(tmp_r1, addr);
        break;
    case 0x9: /* CEB    R1,D2(X2,B2)       [RXE] */
        tmp = tcg_temp_new_i64();
        tmp32 = load_freg32(r1);
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
        set_cc_cmp_f32_i64(s, tmp32, tmp);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32);
        break;
    case 0xa: /* AEB    R1,D2(X2,B2)       [RXE] */
        tmp = tcg_temp_new_i64();
        tmp32 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        gen_helper_aeb(tmp_r1, tmp32);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32);

        tmp32 = load_freg32(r1);
        set_cc_nz_f32(s, tmp32);
        tcg_temp_free_i32(tmp32);
        break;
    case 0xb: /* SEB    R1,D2(X2,B2)       [RXE] */
        tmp = tcg_temp_new_i64();
        tmp32 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        gen_helper_seb(tmp_r1, tmp32);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32);

        tmp32 = load_freg32(r1);
        set_cc_nz_f32(s, tmp32);
        tcg_temp_free_i32(tmp32);
        break;
    case 0xd: /* DEB    R1,D2(X2,B2)       [RXE] */
        tmp = tcg_temp_new_i64();
        tmp32 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        gen_helper_deb(tmp_r1, tmp32);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32);
        break;
    case 0x10: /* TCEB   R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_tceb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x11: /* TCDB   R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_tcdb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x12: /* TCXB   R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_tcxb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x17: /* MEEB   R1,D2(X2,B2)       [RXE] */
        tmp = tcg_temp_new_i64();
        tmp32 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        gen_helper_meeb(tmp_r1, tmp32);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32);
        break;
    case 0x19: /* CDB    R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_cdb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x1a: /* ADB    R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_adb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x1b: /* SDB    R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_sdb(cc_op, tmp_r1, addr);
        set_cc_static(s);
        break;
    case 0x1c: /* MDB    R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_mdb(tmp_r1, addr);
        break;
    case 0x1d: /* DDB    R1,D2(X2,B2)       [RXE] */
        potential_page_fault(s);
        gen_helper_ddb(tmp_r1, addr);
        break;
    case 0x1e: /* MADB  R1,R3,D2(X2,B2) [RXF] */
        /* for RXF insns, r1 is R3 and r1b is R1 */
        tmp32 = tcg_const_i32(r1b);
        potential_page_fault(s);
        gen_helper_madb(tmp32, addr, tmp_r1);
        tcg_temp_free_i32(tmp32);
        break;
    default:
        LOG_DISAS("illegal ed operation 0x%x\n", op);
        gen_illegal_opcode(s, 3);
        return;
    }
    tcg_temp_free_i32(tmp_r1);
    tcg_temp_free_i64(addr);
}

static void disas_a5(DisasContext *s, int op, int r1, int i2)
{
    TCGv_i64 tmp, tmp2;
    TCGv_i32 tmp32;
    LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
    switch (op) {
    case 0x0: /* IIHH     R1,I2     [RI] */
        tmp = tcg_const_i64(i2);
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16);
        tcg_temp_free_i64(tmp);
        break;
    case 0x1: /* IIHL     R1,I2     [RI] */
        tmp = tcg_const_i64(i2);
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16);
        tcg_temp_free_i64(tmp);
        break;
    case 0x2: /* IILH     R1,I2     [RI] */
        tmp = tcg_const_i64(i2);
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16);
        tcg_temp_free_i64(tmp);
        break;
    case 0x3: /* IILL     R1,I2     [RI] */
        tmp = tcg_const_i64(i2);
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16);
        tcg_temp_free_i64(tmp);
        break;
    case 0x4: /* NIHH     R1,I2     [RI] */
    case 0x8: /* OIHH     R1,I2     [RI] */
        tmp = load_reg(r1);
        tmp32 = tcg_temp_new_i32();
        switch (op) {
        case 0x4:
            tmp2 = tcg_const_i64((((uint64_t)i2) << 48)
                               | 0x0000ffffffffffffULL);
            tcg_gen_and_i64(tmp, tmp, tmp2);
            break;
        case 0x8:
            tmp2 = tcg_const_i64(((uint64_t)i2) << 48);
            tcg_gen_or_i64(tmp, tmp, tmp2);
            break;
        default:
            tcg_abort();
        }
        store_reg(r1, tmp);
        tcg_gen_shri_i64(tmp2, tmp, 48);
        tcg_gen_trunc_i64_i32(tmp32, tmp2);
        set_cc_nz_u32(s, tmp32);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32);
        tcg_temp_free_i64(tmp);
        break;
    case 0x5: /* NIHL     R1,I2     [RI] */
    case 0x9: /* OIHL     R1,I2     [RI] */
        tmp = load_reg(r1);
        tmp32 = tcg_temp_new_i32();
        switch (op) {
        case 0x5:
            tmp2 = tcg_const_i64((((uint64_t)i2) << 32)
                               | 0xffff0000ffffffffULL);
            tcg_gen_and_i64(tmp, tmp, tmp2);
            break;
        case 0x9:
            tmp2 = tcg_const_i64(((uint64_t)i2) << 32);
            tcg_gen_or_i64(tmp, tmp, tmp2);
            break;
        default:
            tcg_abort();
        }
        store_reg(r1, tmp);
        tcg_gen_shri_i64(tmp2, tmp, 32);
        tcg_gen_trunc_i64_i32(tmp32, tmp2);
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
        set_cc_nz_u32(s, tmp32);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32);
        tcg_temp_free_i64(tmp);
        break;
    case 0x6: /* NILH     R1,I2     [RI] */
    case 0xa: /* OILH     R1,I2     [RI] */
        tmp = load_reg(r1);
        tmp32 = tcg_temp_new_i32();
        switch (op) {
        case 0x6:
            tmp2 = tcg_const_i64((((uint64_t)i2) << 16)
                               | 0xffffffff0000ffffULL);
            tcg_gen_and_i64(tmp, tmp, tmp2);
            break;
        case 0xa:
            tmp2 = tcg_const_i64(((uint64_t)i2) << 16);
            tcg_gen_or_i64(tmp, tmp, tmp2);
            break;
        default:
            tcg_abort();
        }
        store_reg(r1, tmp);
        tcg_gen_shri_i64(tmp, tmp, 16);
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
        set_cc_nz_u32(s, tmp32);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32);
        tcg_temp_free_i64(tmp);
        break;
    case 0x7: /* NILL     R1,I2     [RI] */
    case 0xb: /* OILL     R1,I2     [RI] */
        tmp = load_reg(r1);
        tmp32 = tcg_temp_new_i32();
        switch (op) {
        case 0x7:
            tmp2 = tcg_const_i64(i2 | 0xffffffffffff0000ULL);
            tcg_gen_and_i64(tmp, tmp, tmp2);
            break;
        case 0xb:
            tmp2 = tcg_const_i64(i2);
            tcg_gen_or_i64(tmp, tmp, tmp2);
            break;
        default:
            tcg_abort();
        }
        store_reg(r1, tmp);
        tcg_gen_trunc_i64_i32(tmp32, tmp);
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
        set_cc_nz_u32(s, tmp32);        /* signedness should not matter here */
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32);
        tcg_temp_free_i64(tmp);
        break;
    case 0xc: /* LLIHH     R1,I2     [RI] */
        tmp = tcg_const_i64( ((uint64_t)i2) << 48 );
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0xd: /* LLIHL     R1,I2     [RI] */
        tmp = tcg_const_i64( ((uint64_t)i2) << 32 );
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0xe: /* LLILH     R1,I2     [RI] */
        tmp = tcg_const_i64( ((uint64_t)i2) << 16 );
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0xf: /* LLILL     R1,I2     [RI] */
        tmp = tcg_const_i64(i2);
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    default:
        LOG_DISAS("illegal a5 operation 0x%x\n", op);
        gen_illegal_opcode(s, 2);
        return;
    }
}

static void disas_a7(DisasContext *s, int op, int r1, int i2)
{
    TCGv_i64 tmp, tmp2;
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
    int l1;

    LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
    switch (op) {
    case 0x0: /* TMLH or TMH     R1,I2     [RI] */
    case 0x1: /* TMLL or TML     R1,I2     [RI] */
    case 0x2: /* TMHH     R1,I2     [RI] */
    case 0x3: /* TMHL     R1,I2     [RI] */
        tmp = load_reg(r1);
        tmp2 = tcg_const_i64((uint16_t)i2);
        switch (op) {
        case 0x0:
            tcg_gen_shri_i64(tmp, tmp, 16);
            break;
        case 0x1:
            break;
        case 0x2:
            tcg_gen_shri_i64(tmp, tmp, 48);
            break;
        case 0x3:
            tcg_gen_shri_i64(tmp, tmp, 32);
            break;
        }
        tcg_gen_andi_i64(tmp, tmp, 0xffff);
        cmp_64(s, tmp, tmp2, CC_OP_TM_64);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x4: /* brc m1, i2 */
        gen_brc(r1, s, i2 * 2LL);
        return;
    case 0x5: /* BRAS     R1,I2     [RI] */
        tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        gen_goto_tb(s, 0, s->pc + i2 * 2LL);
        s->is_jmp = DISAS_TB_JUMP;
        break;
    case 0x6: /* BRCT     R1,I2     [RI] */
        tmp32_1 = load_reg32(r1);
        tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
        store_reg32(r1, tmp32_1);
        gen_update_cc_op(s);
        l1 = gen_new_label();
        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
        gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
        gen_set_label(l1);
        gen_goto_tb(s, 1, s->pc + 4);
        s->is_jmp = DISAS_TB_JUMP;
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x7: /* BRCTG     R1,I2     [RI] */
        tmp = load_reg(r1);
        tcg_gen_subi_i64(tmp, tmp, 1);
        store_reg(r1, tmp);
        gen_update_cc_op(s);
        l1 = gen_new_label();
        tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
        gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
        gen_set_label(l1);
        gen_goto_tb(s, 1, s->pc + 4);
        s->is_jmp = DISAS_TB_JUMP;
        tcg_temp_free_i64(tmp);
        break;
    case 0x8: /* lhi r1, i2 */
        tmp32_1 = tcg_const_i32(i2);
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x9: /* lghi r1, i2 */
        tmp = tcg_const_i64(i2);
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0xa: /* AHI     R1,I2     [RI] */
        tmp32_1 = load_reg32(r1);
        tmp32_2 = tcg_temp_new_i32();
        tmp32_3 = tcg_const_i32(i2);

        if (i2 < 0) {
            tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2);
        } else {
            tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3);
        }

        store_reg32(r1, tmp32_2);
        set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        break;
    case 0xb: /* aghi r1, i2 */
        tmp = load_reg(r1);
        tmp2 = tcg_const_i64(i2);

        if (i2 < 0) {
            tcg_gen_subi_i64(regs[r1], tmp, -i2);
        } else {
            tcg_gen_add_i64(regs[r1], tmp, tmp2);
        }
        set_cc_add64(s, tmp, tmp2, regs[r1]);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0xc: /* MHI     R1,I2     [RI] */
        tmp32_1 = load_reg32(r1);
        tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0xd: /* MGHI     R1,I2     [RI] */
        tmp = load_reg(r1);
        tcg_gen_muli_i64(tmp, tmp, i2);
        store_reg(r1, tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0xe: /* CHI     R1,I2     [RI] */
        tmp32_1 = load_reg32(r1);
        cmp_s32c(s, tmp32_1, i2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0xf: /* CGHI     R1,I2     [RI] */
        tmp = load_reg(r1);
        cmp_s64c(s, tmp, i2);
        tcg_temp_free_i64(tmp);
        break;
    default:
        LOG_DISAS("illegal a7 operation 0x%x\n", op);
        gen_illegal_opcode(s, 2);
        return;
    }
}

static void disas_b2(DisasContext *s, int op, uint32_t insn)
{
    TCGv_i64 tmp, tmp2, tmp3;
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
    int r1, r2;
    int ilc = 2;
#ifndef CONFIG_USER_ONLY
    int r3, d2, b2;
#endif

    r1 = (insn >> 4) & 0xf;
    r2 = insn & 0xf;

    LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);

    switch (op) {
    case 0x22: /* IPM    R1               [RRE] */
        tmp32_1 = tcg_const_i32(r1);
        gen_op_calc_cc(s);
        gen_helper_ipm(cc_op, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x41: /* CKSM    R1,R2     [RRE] */
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r2);
        potential_page_fault(s);
        gen_helper_cksm(tmp32_1, tmp32_2);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        gen_op_movi_cc(s, 0);
        break;
    case 0x4e: /* SAR     R1,R2     [RRE] */
        tmp32_1 = load_reg32(r2);
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1]));
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x4f: /* EAR     R1,R2     [RRE] */
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2]));
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x52: /* MSR     R1,R2     [RRE] */
        tmp32_1 = load_reg32(r1);
        tmp32_2 = load_reg32(r2);
        tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
        store_reg32(r1, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x54: /* MVPG     R1,R2     [RRE] */
        tmp = load_reg(0);
        tmp2 = load_reg(r1);
        tmp3 = load_reg(r2);
        potential_page_fault(s);
        gen_helper_mvpg(tmp, tmp2, tmp3);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        /* XXX check CCO bit and set CC accordingly */
        gen_op_movi_cc(s, 0);
        break;
    case 0x55: /* MVST     R1,R2     [RRE] */
        tmp32_1 = load_reg32(0);
        tmp32_2 = tcg_const_i32(r1);
        tmp32_3 = tcg_const_i32(r2);
        potential_page_fault(s);
        gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        gen_op_movi_cc(s, 1);
        break;
    case 0x5d: /* CLST     R1,R2     [RRE] */
        tmp32_1 = load_reg32(0);
        tmp32_2 = tcg_const_i32(r1);
        tmp32_3 = tcg_const_i32(r2);
        potential_page_fault(s);
        gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3);
        set_cc_static(s);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        break;
    case 0x5e: /* SRST     R1,R2     [RRE] */
        tmp32_1 = load_reg32(0);
        tmp32_2 = tcg_const_i32(r1);
        tmp32_3 = tcg_const_i32(r2);
        potential_page_fault(s);
        gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3);
        set_cc_static(s);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        tcg_temp_free_i32(tmp32_3);
        break;

#ifndef CONFIG_USER_ONLY
    case 0x02: /* STIDP     D2(B2)     [S] */
        /* Store CPU ID */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_stidp(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x04: /* SCK       D2(B2)     [S] */
        /* Set Clock */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_sck(cc_op, tmp);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        break;
    case 0x05: /* STCK     D2(B2)     [S] */
        /* Store Clock */
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_stck(cc_op, tmp);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        break;
    case 0x06: /* SCKC     D2(B2)     [S] */
        /* Set Clock Comparator */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_sckc(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x07: /* STCKC    D2(B2)     [S] */
        /* Store Clock Comparator */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_stckc(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x08: /* SPT      D2(B2)     [S] */
        /* Set CPU Timer */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_spt(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x09: /* STPT     D2(B2)     [S] */
        /* Store CPU Timer */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_stpt(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x0a: /* SPKA     D2(B2)     [S] */
        /* Set PSW Key from Address */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
        tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
        tcg_gen_or_i64(psw_mask, tmp2, tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp);
        break;
    case 0x0d: /* PTLB                [S] */
        /* Purge TLB */
        check_privileged(s, ilc);
        gen_helper_ptlb();
        break;
    case 0x10: /* SPX      D2(B2)     [S] */
        /* Set Prefix Register */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_spx(tmp);
        tcg_temp_free_i64(tmp);
        break;
    case 0x11: /* STPX     D2(B2)     [S] */
        /* Store Prefix */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp2 = tcg_temp_new_i64();
        tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa));
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x12: /* STAP     D2(B2)     [S] */
        /* Store CPU Address */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num));
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0x21: /* IPTE     R1,R2      [RRE] */
        /* Invalidate PTE */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp = load_reg(r1);
        tmp2 = load_reg(r2);
        gen_helper_ipte(tmp, tmp2);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x29: /* ISKE     R1,R2      [RRE] */
        /* Insert Storage Key Extended */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp = load_reg(r2);
        tmp2 = tcg_temp_new_i64();
        gen_helper_iske(tmp2, tmp);
        store_reg(r1, tmp2);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        break;
    case 0x2a: /* RRBE     R1,R2      [RRE] */
        /* Set Storage Key Extended */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp32_1 = load_reg32(r1);
        tmp = load_reg(r2);
        gen_helper_rrbe(cc_op, tmp32_1, tmp);
        set_cc_static(s);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i64(tmp);
        break;
    case 0x2b: /* SSKE     R1,R2      [RRE] */
        /* Set Storage Key Extended */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp32_1 = load_reg32(r1);
        tmp = load_reg(r2);
        gen_helper_sske(tmp32_1, tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i64(tmp);
        break;
    case 0x34: /* STCH ? */
        /* Store Subchannel */
        check_privileged(s, ilc);
        gen_op_movi_cc(s, 3);
        break;
    case 0x46: /* STURA    R1,R2      [RRE] */
        /* Store Using Real Address */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp32_1 = load_reg32(r1);
        tmp = load_reg(r2);
        potential_page_fault(s);
        gen_helper_stura(tmp, tmp32_1);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i64(tmp);
        break;
    case 0x50: /* CSP      R1,R2      [RRE] */
        /* Compare And Swap And Purge */
        check_privileged(s, ilc);
        r1 = (insn >> 4) & 0xf;
        r2 = insn & 0xf;
        tmp32_1 = tcg_const_i32(r1);
        tmp32_2 = tcg_const_i32(r2);
        gen_helper_csp(cc_op, tmp32_1, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x5f: /* CHSC ? */
        /* Channel Subsystem Call */
        check_privileged(s, ilc);
        gen_op_movi_cc(s, 3);
        break;
    case 0x78: /* STCKE    D2(B2)     [S] */
        /* Store Clock Extended */
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_stcke(cc_op, tmp);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        break;
    case 0x79: /* SACF    D2(B2)     [S] */
        /* Store Clock Extended */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        potential_page_fault(s);
        gen_helper_sacf(tmp);
        tcg_temp_free_i64(tmp);
        /* addressing mode has changed, so end the block */
        s->pc += ilc * 2;
        update_psw_addr(s);
        s->is_jmp = DISAS_EXCP;
        break;
    case 0x7d: /* STSI     D2,(B2)     [S] */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp32_1 = load_reg32(0);
        tmp32_2 = load_reg32(1);
        potential_page_fault(s);
        gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2);
        set_cc_static(s);
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i32(tmp32_2);
        break;
    case 0x9d: /* LFPC      D2(B2)   [S] */
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp2 = tcg_temp_new_i64();
        tmp32_1 = tcg_temp_new_i32();
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i32(tmp32_1);
        break;
    case 0xb1: /* STFL     D2(B2)     [S] */
        /* Store Facility List (CPU features) at 200 */
        check_privileged(s, ilc);
        tmp2 = tcg_const_i64(0xc0000000);
        tmp = tcg_const_i64(200);
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp);
        break;
    case 0xb2: /* LPSWE    D2(B2)     [S] */
        /* Load PSW Extended */
        check_privileged(s, ilc);
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
        tmp = get_address(s, 0, b2, d2);
        tmp2 = tcg_temp_new_i64();
        tmp3 = tcg_temp_new_i64();
        tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
        tcg_gen_addi_i64(tmp, tmp, 8);
        tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
        gen_helper_load_psw(tmp2, tmp3);
        /* we need to keep cc_op intact */
        s->is_jmp = DISAS_JUMP;
        tcg_temp_free_i64(tmp);
        tcg_temp_free_i64(tmp2);
        tcg_temp_free_i64(tmp3);
        break;
    case 0x20: /* SERVC     R1,R2     [RRE] */
        /* SCLP Service call (PV hypercall) */
        check_privileged(s, ilc);
        potential_page_fault(s);
        tmp32_1 = load_reg32(r2);
        tmp = load_reg(r1);
        gen_helper_servc(cc_op, tmp32_1, tmp);
        set_cc_static(s);
        tcg_temp_free_i32(tmp32_1);
        tcg_temp_free_i64(tmp);
        break;
#endif
    default:
        LOG_DISAS("illegal b2 operation 0x%x\n", op);
        gen_illegal_opcode(s, ilc);
        break;
    }
}