LXR qemu/hw/axis

   1/*
   2 * QEMU model for the AXIS devboard 88.
   3 *
   4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "sysbus.h"
  26#include "net.h"
  27#include "flash.h"
  28#include "boards.h"
  29#include "etraxfs.h"
  30#include "loader.h"
  31#include "elf.h"
  32#include "cris-boot.h"
  33#include "blockdev.h"
  34#include "exec-memory.h"
  35
  36#define D(x)
  37#define DNAND(x)
  38
  39struct nand_state_t
  40{
  41    DeviceState *nand;
  42    unsigned int rdy:1;
  43    unsigned int ale:1;
  44    unsigned int cle:1;
  45    unsigned int ce:1;
  46};
  47
  48static struct nand_state_t nand_state;
  49static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
  50{
  51    struct nand_state_t *s = opaque;
  52    uint32_t r;
  53    int rdy;
  54
  55    r = nand_getio(s->nand);
  56    nand_getpins(s->nand, &rdy);
  57    s->rdy = rdy;
  58
  59    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
  60    return r;
  61}
  62
  63static void
  64nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  65{
  66    struct nand_state_t *s = opaque;
  67    int rdy;
  68
  69    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
  70    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
  71    nand_setio(s->nand, value);
  72    nand_getpins(s->nand, &rdy);
  73    s->rdy = rdy;
  74}
  75
  76static CPUReadMemoryFunc * const nand_read[] = {
  77    &nand_readl,
  78    &nand_readl,
  79    &nand_readl,
  80};
  81
  82static CPUWriteMemoryFunc * const nand_write[] = {
  83    &nand_writel,
  84    &nand_writel,
  85    &nand_writel,
  86};
  87
  88
  89struct tempsensor_t
  90{
  91    unsigned int shiftreg;
  92    unsigned int count;
  93    enum {
  94        ST_OUT, ST_IN, ST_Z
  95    } state;
  96
  97    uint16_t regs[3];
  98};
  99
 100static void tempsensor_clkedge(struct tempsensor_t *s,
 101                               unsigned int clk, unsigned int data_in)
 102{
 103    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
 104             clk, s->state, s->shiftreg));
 105    if (s->count == 0) {
 106        s->count = 16;
 107        s->state = ST_OUT;
 108    }
 109    switch (s->state) {
 110        case ST_OUT:
 111            /* Output reg is clocked at negedge.  */
 112            if (!clk) {
 113                s->count--;
 114                s->shiftreg <<= 1;
 115                if (s->count == 0) {
 116                    s->shiftreg = 0;
 117                    s->state = ST_IN;
 118                    s->count = 16;
 119                }
 120            }
 121            break;
 122        case ST_Z:
 123            if (clk) {
 124                s->count--;
 125                if (s->count == 0) {
 126                    s->shiftreg = 0;
 127                    s->state = ST_OUT;
 128                    s->count = 16;
 129                }
 130            }
 131            break;
 132        case ST_IN:
 133            /* Indata is sampled at posedge.  */
 134            if (clk) {
 135                s->count--;
 136                s->shiftreg <<= 1;
 137                s->shiftreg |= data_in & 1;
 138                if (s->count == 0) {
 139                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
 140                    s->regs[0] = s->shiftreg;
 141                    s->state = ST_OUT;
 142                    s->count = 16;
 143
 144                    if ((s->regs[0] & 0xff) == 0) {
 145                        /* 25 degrees celcius.  */
 146                        s->shiftreg = 0x0b9f;
 147                    } else if ((s->regs[0] & 0xff) == 0xff) {
 148                        /* Sensor ID, 0x8100 LM70.  */
 149                        s->shiftreg = 0x8100;
 150                    } else
 151                        printf("Invalid tempsens state %x\n", s->regs[0]);
 152                }
 153            }
 154            break;
 155    }
 156}
 157
 158
 159#define RW_PA_DOUT    0x00
 160#define R_PA_DIN      0x01
 161#define RW_PA_OE      0x02
 162#define RW_PD_DOUT    0x10
 163#define R_PD_DIN      0x11
 164#define RW_PD_OE      0x12
 165
 166static struct gpio_state_t
 167{
 168    struct nand_state_t *nand;
 169    struct tempsensor_t tempsensor;
 170    uint32_t regs[0x5c / 4];
 171} gpio_state;
 172
 173static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
 174{
 175    struct gpio_state_t *s = opaque;
 176    uint32_t r = 0;
 177
 178    addr >>= 2;
 179    switch (addr)
 180    {
 181        case R_PA_DIN:
 182            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
 183
 184            /* Encode pins from the nand.  */
 185            r |= s->nand->rdy << 7;
 186            break;
 187        case R_PD_DIN:
 188            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
 189
 190            /* Encode temp sensor pins.  */
 191            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
 192            break;
 193
 194        default:
 195            r = s->regs[addr];
 196            break;
 197    }
 198    return r;
 199    D(printf("%s %x=%x\n", __func__, addr, r));
 200}
 201
 202static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 203{
 204    struct gpio_state_t *s = opaque;
 205    D(printf("%s %x=%x\n", __func__, addr, value));
 206
 207    addr >>= 2;
 208    switch (addr)
 209    {
 210        case RW_PA_DOUT:
 211            /* Decode nand pins.  */
 212            s->nand->ale = !!(value & (1 << 6));
 213            s->nand->cle = !!(value & (1 << 5));
 214            s->nand->ce  = !!(value & (1 << 4));
 215
 216            s->regs[addr] = value;
 217            break;
 218
 219        case RW_PD_DOUT:
 220            /* Temp sensor clk.  */
 221            if ((s->regs[addr] ^ value) & 2)
 222                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
 223                                   !!(value & 16));
 224            s->regs[addr] = value;
 225            break;
 226
 227        default:
 228            s->regs[addr] = value;
 229            break;
 230    }
 231}
 232
 233static CPUReadMemoryFunc * const gpio_read[] = {
 234    NULL, NULL,
 235    &gpio_readl,
 236};
 237
 238static CPUWriteMemoryFunc * const gpio_write[] = {
 239    NULL, NULL,
 240    &gpio_writel,
 241};
 242
 243#define INTMEM_SIZE (128 * 1024)
 244
 245static struct cris_load_info li;
 246
 247static
 248void axisdev88_init (ram_addr_t ram_size,
 249                     const char *boot_device,
 250                     const char *kernel_filename, const char *kernel_cmdline,
 251                     const char *initrd_filename, const char *cpu_model)
 252{
 253    CPUState *env;
 254    DeviceState *dev;
 255    SysBusDevice *s;
 256    DriveInfo *nand;
 257    qemu_irq irq[30], nmi[2], *cpu_irq;
 258    void *etraxfs_dmac;
 259    struct etraxfs_dma_client *dma_eth;
 260    int i;
 261    int nand_regs;
 262    int gpio_regs;
 263    MemoryRegion *address_space_mem = get_system_memory();
 264    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 265    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
 266
 267    /* init CPUs */
 268    if (cpu_model == NULL) {
 269        cpu_model = "crisv32";
 270    }
 271    env = cpu_init(cpu_model);
 272
 273    /* allocate RAM */
 274    memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
 275    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
 276
 277    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
 278       internal memory.  */
 279    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
 280    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
 281
 282      /* Attach a NAND flash to CS1.  */
 283    nand = drive_get(IF_MTD, 0, 0);
 284    nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
 285                                NAND_MFR_STMICRO, 0x39);
 286    nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state,
 287                                       DEVICE_NATIVE_ENDIAN);
 288    cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
 289
 290    gpio_state.nand = &nand_state;
 291    gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state,
 292                                       DEVICE_NATIVE_ENDIAN);
 293    cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
 294
 295
 296    cpu_irq = cris_pic_init_cpu(env);
 297    dev = qdev_create(NULL, "etraxfs,pic");
 298    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
 299    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
 300    qdev_init_nofail(dev);
 301    s = sysbus_from_qdev(dev);
 302    sysbus_mmio_map(s, 0, 0x3001c000);
 303    sysbus_connect_irq(s, 0, cpu_irq[0]);
 304    sysbus_connect_irq(s, 1, cpu_irq[1]);
 305    for (i = 0; i < 30; i++) {
 306        irq[i] = qdev_get_gpio_in(dev, i);
 307    }
 308    nmi[0] = qdev_get_gpio_in(dev, 30);
 309    nmi[1] = qdev_get_gpio_in(dev, 31);
 310
 311    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
 312    for (i = 0; i < 10; i++) {
 313        /* On ETRAX, odd numbered channels are inputs.  */
 314        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
 315    }
 316
 317    /* Add the two ethernet blocks.  */
 318    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
 319    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
 320    if (nb_nics > 1) {
 321        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
 322    }
 323
 324    /* The DMA Connector block is missing, hardwire things for now.  */
 325    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
 326    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
 327    if (nb_nics > 1) {
 328        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
 329        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
 330    }
 331
 332    /* 2 timers.  */
 333    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
 334    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
 335
 336    for (i = 0; i < 4; i++) {
 337        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
 338                             irq[0x14 + i]);
 339    }
 340
 341    if (!kernel_filename) {
 342        fprintf(stderr, "Kernel image must be specified\n");
 343        exit(1);
 344    }
 345
 346    li.image_filename = kernel_filename;
 347    li.cmdline = kernel_cmdline;
 348    cris_load_image(env, &li);
 349}
 350
 351static QEMUMachine axisdev88_machine = {
 352    .name = "axis-dev88",
 353    .desc = "AXIS devboard 88",
 354    .init = axisdev88_init,
 355    .is_default = 1,
 356};
 357
 358static void axisdev88_machine_init(void)
 359{
 360    qemu_register_machine(&axisdev88_machine);
 361}
 362
 363machine_init(axisdev88_machine_init);
 364