1#define PCNET_IOPORT_SIZE 0x20
2#define PCNET_PNPMMIO_SIZE 0x20
3
4#define PCNET_LOOPTEST_CRC 1
5#define PCNET_LOOPTEST_NOCRC 2
6
7#include "memory.h"
8
9
10#define BCR_MSRDA 0
11#define BCR_MSWRA 1
12#define BCR_MC 2
13#define BCR_LNKST 4
14#define BCR_LED1 5
15#define BCR_LED2 6
16#define BCR_LED3 7
17#define BCR_FDC 9
18#define BCR_BSBC 18
19#define BCR_EECAS 19
20#define BCR_SWS 20
21#define BCR_PLAT 22
22
23#define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
24#define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
25#define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
26#define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
27
28typedef struct PCNetState_st PCNetState;
29
30struct PCNetState_st {
31 NICState *nic;
32 NICConf conf;
33 QEMUTimer *poll_timer;
34 int rap, isr, lnkst;
35 uint32_t rdra, tdra;
36 uint8_t prom[16];
37 uint16_t csr[128];
38 uint16_t bcr[32];
39 int xmit_pos;
40 uint64_t timer;
41 MemoryRegion mmio;
42 uint8_t buffer[4096];
43 qemu_irq irq;
44 void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
45 uint8_t *buf, int len, int do_bswap);
46 void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
47 uint8_t *buf, int len, int do_bswap);
48 void *dma_opaque;
49 int tx_busy;
50 int looptest;
51};
52
53void pcnet_h_reset(void *opaque);
54void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
55uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr);
56void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
57uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr);
58uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
59int pcnet_can_receive(VLANClientState *nc);
60ssize_t pcnet_receive(VLANClientState *nc, const uint8_t *buf, size_t size_);
61void pcnet_set_link_status(VLANClientState *nc);
62void pcnet_common_cleanup(PCNetState *d);
63int pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
64extern const VMStateDescription vmstate_pcnet;
65
