LXR qemu/hw/exynos4210.c

   1/*
   2 *  Samsung exynos4210 SoC emulation
   3 *
   4 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5 *    Maksim Kozlov <m.kozlov@samsung.com>
   6 *    Evgeny Voevodin <e.voevodin@samsung.com>
   7 *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8 *
   9 *  This program is free software; you can redistribute it and/or modify it
  10 *  under the terms of the GNU General Public License as published by the
  11 *  Free Software Foundation; either version 2 of the License, or
  12 *  (at your option) any later version.
  13 *
  14 *  This program is distributed in the hope that it will be useful, but WITHOUT
  15 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17 *  for more details.
  18 *
  19 *  You should have received a copy of the GNU General Public License along
  20 *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21 *
  22 */
  23
  24#include "boards.h"
  25#include "sysemu.h"
  26#include "sysbus.h"
  27#include "arm-misc.h"
  28#include "loader.h"
  29#include "exynos4210.h"
  30
  31#define EXYNOS4210_CHIPID_ADDR         0x10000000
  32
  33/* PWM */
  34#define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  35
  36/* MCT */
  37#define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  38
  39/* UART's definitions */
  40#define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  41#define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  42#define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  43#define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  44#define EXYNOS4210_UART0_FIFO_SIZE     256
  45#define EXYNOS4210_UART1_FIFO_SIZE     64
  46#define EXYNOS4210_UART2_FIFO_SIZE     16
  47#define EXYNOS4210_UART3_FIFO_SIZE     16
  48/* Interrupt Group of External Interrupt Combiner for UART */
  49#define EXYNOS4210_UART_INT_GRP        26
  50
  51/* External GIC */
  52#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  53#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  54
  55/* Combiner */
  56#define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  57#define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  58
  59/* PMU SFR base address */
  60#define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  61
  62/* Display controllers (FIMD) */
  63#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  64
  65static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  66                                    0x09, 0x00, 0x00, 0x00 };
  67
  68void exynos4210_write_secondary(CPUARMState *env,
  69        const struct arm_boot_info *info)
  70{
  71    int n;
  72    uint32_t smpboot[] = {
  73        0xe59f3024, /* ldr r3, External gic_cpu_if */
  74        0xe59f2024, /* ldr r2, Internal gic_cpu_if */
  75        0xe59f0024, /* ldr r0, startaddr */
  76        0xe3a01001, /* mov r1, #1 */
  77        0xe5821000, /* str r1, [r2] */
  78        0xe5831000, /* str r1, [r3] */
  79        0xe320f003, /* wfi */
  80        0xe5901000, /* ldr     r1, [r0] */
  81        0xe1110001, /* tst     r1, r1 */
  82        0x0afffffb, /* beq     <wfi> */
  83        0xe12fff11, /* bx      r1 */
  84        EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
  85        0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
  86        0           /* bootreg: Boot register address is held here */
  87    };
  88    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
  89    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
  90    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  91        smpboot[n] = tswap32(smpboot[n]);
  92    }
  93    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
  94                       info->smp_loader_start);
  95}
  96
  97Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
  98        unsigned long ram_size)
  99{
 100    qemu_irq cpu_irq[4];
 101    int n;
 102    Exynos4210State *s = g_new(Exynos4210State, 1);
 103    qemu_irq *irqp;
 104    qemu_irq gate_irq[EXYNOS4210_IRQ_GATE_NINPUTS];
 105    unsigned long mem_size;
 106    DeviceState *dev;
 107    SysBusDevice *busdev;
 108
 109    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 110        s->env[n] = cpu_init("cortex-a9");
 111        if (!s->env[n]) {
 112            fprintf(stderr, "Unable to find CPU %d definition\n", n);
 113            exit(1);
 114        }
 115        /* Create PIC controller for each processor instance */
 116        irqp = arm_pic_init_cpu(s->env[n]);
 117
 118        /*
 119         * Get GICs gpio_in cpu_irq to connect a combiner to them later.
 120         * Use only IRQ for a while.
 121         */
 122        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 123    }
 124
 125    /*** IRQs ***/
 126
 127    s->irq_table = exynos4210_init_irq(&s->irqs);
 128
 129    /* IRQ Gate */
 130    dev = qdev_create(NULL, "exynos4210.irq_gate");
 131    qdev_init_nofail(dev);
 132    /* Get IRQ Gate input in gate_irq */
 133    for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 134        gate_irq[n] = qdev_get_gpio_in(dev, n);
 135    }
 136    busdev = sysbus_from_qdev(dev);
 137    /* Connect IRQ Gate output to cpu_irq */
 138    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 139        sysbus_connect_irq(busdev, n, cpu_irq[n]);
 140    }
 141
 142    /* Private memory region and Internal GIC */
 143    dev = qdev_create(NULL, "a9mpcore_priv");
 144    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 145    qdev_init_nofail(dev);
 146    busdev = sysbus_from_qdev(dev);
 147    sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 148    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 149        sysbus_connect_irq(busdev, n, gate_irq[n * 2]);
 150    }
 151    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 152        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 153    }
 154
 155    /* Cache controller */
 156    sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 157
 158    /* External GIC */
 159    dev = qdev_create(NULL, "exynos4210.gic");
 160    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 161    qdev_init_nofail(dev);
 162    busdev = sysbus_from_qdev(dev);
 163    /* Map CPU interface */
 164    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 165    /* Map Distributer interface */
 166    sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 167    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 168        sysbus_connect_irq(busdev, n, gate_irq[n * 2 + 1]);
 169    }
 170    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 171        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 172    }
 173
 174    /* Internal Interrupt Combiner */
 175    dev = qdev_create(NULL, "exynos4210.combiner");
 176    qdev_init_nofail(dev);
 177    busdev = sysbus_from_qdev(dev);
 178    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 179        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 180    }
 181    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 182    sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 183
 184    /* External Interrupt Combiner */
 185    dev = qdev_create(NULL, "exynos4210.combiner");
 186    qdev_prop_set_uint32(dev, "external", 1);
 187    qdev_init_nofail(dev);
 188    busdev = sysbus_from_qdev(dev);
 189    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 190        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 191    }
 192    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 193    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 194
 195    /* Initialize board IRQs. */
 196    exynos4210_init_board_irqs(&s->irqs);
 197
 198    /*** Memory ***/
 199
 200    /* Chip-ID and OMR */
 201    memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
 202            sizeof(chipid_and_omr), chipid_and_omr);
 203    memory_region_set_readonly(&s->chipid_mem, true);
 204    memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 205                                &s->chipid_mem);
 206
 207    /* Internal ROM */
 208    memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
 209                           EXYNOS4210_IROM_SIZE);
 210    memory_region_set_readonly(&s->irom_mem, true);
 211    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 212                                &s->irom_mem);
 213    /* mirror of iROM */
 214    memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
 215                             &s->irom_mem,
 216                             EXYNOS4210_IROM_BASE_ADDR,
 217                             EXYNOS4210_IROM_SIZE);
 218    memory_region_set_readonly(&s->irom_alias_mem, true);
 219    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 220                                &s->irom_alias_mem);
 221
 222    /* Internal RAM */
 223    memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
 224                           EXYNOS4210_IRAM_SIZE);
 225    vmstate_register_ram_global(&s->iram_mem);
 226    memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 227                                &s->iram_mem);
 228
 229    /* DRAM */
 230    mem_size = ram_size;
 231    if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 232        memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
 233                mem_size - EXYNOS4210_DRAM_MAX_SIZE);
 234        vmstate_register_ram_global(&s->dram1_mem);
 235        memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 236                &s->dram1_mem);
 237        mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 238    }
 239    memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
 240    vmstate_register_ram_global(&s->dram0_mem);
 241    memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 242            &s->dram0_mem);
 243
 244   /* PMU.
 245    * The only reason of existence at the moment is that secondary CPU boot
 246    * loader uses PMU INFORM5 register as a holding pen.
 247    */
 248    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 249
 250    /* PWM */
 251    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 252                          s->irq_table[exynos4210_get_irq(22, 0)],
 253                          s->irq_table[exynos4210_get_irq(22, 1)],
 254                          s->irq_table[exynos4210_get_irq(22, 2)],
 255                          s->irq_table[exynos4210_get_irq(22, 3)],
 256                          s->irq_table[exynos4210_get_irq(22, 4)],
 257                          NULL);
 258
 259    /* Multi Core Timer */
 260    dev = qdev_create(NULL, "exynos4210.mct");
 261    qdev_init_nofail(dev);
 262    busdev = sysbus_from_qdev(dev);
 263    for (n = 0; n < 4; n++) {
 264        /* Connect global timer interrupts to Combiner gpio_in */
 265        sysbus_connect_irq(busdev, n,
 266                s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 267    }
 268    /* Connect local timer interrupts to Combiner gpio_in */
 269    sysbus_connect_irq(busdev, 4,
 270            s->irq_table[exynos4210_get_irq(51, 0)]);
 271    sysbus_connect_irq(busdev, 5,
 272            s->irq_table[exynos4210_get_irq(35, 3)]);
 273    sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 274
 275    /*** UARTs ***/
 276    exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 277                           EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 278                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 279
 280    exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 281                           EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 282                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 283
 284    exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 285                           EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 286                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 287
 288    exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 289                           EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 290                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 291
 292    /*** Display controller (FIMD) ***/
 293    sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 294            s->irq_table[exynos4210_get_irq(11, 0)],
 295            s->irq_table[exynos4210_get_irq(11, 1)],
 296            s->irq_table[exynos4210_get_irq(11, 2)],
 297            NULL);
 298
 299    return s;
 300}
 301