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25#include "hw.h"
26#include "pc.h"
27#include "pci.h"
28#include "pci_host.h"
29#include "isa.h"
30#include "sysbus.h"
31#include "range.h"
32#include "xen.h"
33
34
35
36
37
38
39typedef PCIHostState I440FXState;
40
41#define PIIX_NUM_PIC_IRQS 16
42#define PIIX_NUM_PIRQS 4ULL
43#define XEN_PIIX_NUM_PIRQS 128ULL
44#define PIIX_PIRQC 0x60
45
46typedef struct PIIX3State {
47 PCIDevice dev;
48
49
50
51
52
53
54
55
56
57
58#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
59#error "unable to encode pic state in 64bit in pic_levels."
60#endif
61 uint64_t pic_levels;
62
63 qemu_irq *pic;
64
65
66 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
67} PIIX3State;
68
69typedef struct PAMMemoryRegion {
70 MemoryRegion mem;
71 bool initialized;
72} PAMMemoryRegion;
73
74struct PCII440FXState {
75 PCIDevice dev;
76 MemoryRegion *system_memory;
77 MemoryRegion *pci_address_space;
78 MemoryRegion *ram_memory;
79 MemoryRegion pci_hole;
80 MemoryRegion pci_hole_64bit;
81 PAMMemoryRegion pam_regions[13];
82 MemoryRegion smram_region;
83 uint8_t smm_enabled;
84};
85
86
87#define I440FX_PAM 0x59
88#define I440FX_PAM_SIZE 7
89#define I440FX_SMRAM 0x72
90
91static void piix3_set_irq(void *opaque, int pirq, int level);
92static void piix3_write_config_xen(PCIDevice *dev,
93 uint32_t address, uint32_t val, int len);
94
95
96
97
98static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
99{
100 int slot_addend;
101 slot_addend = (pci_dev->devfn >> 3) - 1;
102 return (pci_intx + slot_addend) & 3;
103}
104
105static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
106 PAMMemoryRegion *mem)
107{
108 if (mem->initialized) {
109 memory_region_del_subregion(d->system_memory, &mem->mem);
110 memory_region_destroy(&mem->mem);
111 }
112
113
114 switch(r) {
115 case 3:
116
117 memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
118 start, end - start);
119 break;
120 case 1:
121
122 memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
123 start, end - start);
124 memory_region_set_readonly(&mem->mem, true);
125 break;
126 case 2:
127 case 0:
128
129 memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
130 start, end - start);
131 break;
132 }
133 memory_region_add_subregion_overlap(d->system_memory,
134 start, &mem->mem, 1);
135 mem->initialized = true;
136}
137
138static void i440fx_update_memory_mappings(PCII440FXState *d)
139{
140 int i, r;
141 uint32_t smram;
142 bool smram_enabled;
143
144 memory_region_transaction_begin();
145 update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
146 &d->pam_regions[0]);
147 for(i = 0; i < 12; i++) {
148 r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
149 update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
150 &d->pam_regions[i+1]);
151 }
152 smram = d->dev.config[I440FX_SMRAM];
153 smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
154 memory_region_set_enabled(&d->smram_region, !smram_enabled);
155 memory_region_transaction_commit();
156}
157
158static void i440fx_set_smm(int val, void *arg)
159{
160 PCII440FXState *d = arg;
161
162 val = (val != 0);
163 if (d->smm_enabled != val) {
164 d->smm_enabled = val;
165 i440fx_update_memory_mappings(d);
166 }
167}
168
169
170static void i440fx_write_config(PCIDevice *dev,
171 uint32_t address, uint32_t val, int len)
172{
173 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
174
175
176 pci_default_write_config(dev, address, val, len);
177 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
178 range_covers_byte(address, len, I440FX_SMRAM)) {
179 i440fx_update_memory_mappings(d);
180 }
181}
182
183static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
184{
185 PCII440FXState *d = opaque;
186 int ret, i;
187
188 ret = pci_device_load(&d->dev, f);
189 if (ret < 0)
190 return ret;
191 i440fx_update_memory_mappings(d);
192 qemu_get_8s(f, &d->smm_enabled);
193
194 if (version_id == 2) {
195 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
196 qemu_get_be32(f);
197 }
198 }
199
200 return 0;
201}
202
203static int i440fx_post_load(void *opaque, int version_id)
204{
205 PCII440FXState *d = opaque;
206
207 i440fx_update_memory_mappings(d);
208 return 0;
209}
210
211static const VMStateDescription vmstate_i440fx = {
212 .name = "I440FX",
213 .version_id = 3,
214 .minimum_version_id = 3,
215 .minimum_version_id_old = 1,
216 .load_state_old = i440fx_load_old,
217 .post_load = i440fx_post_load,
218 .fields = (VMStateField []) {
219 VMSTATE_PCI_DEVICE(dev, PCII440FXState),
220 VMSTATE_UINT8(smm_enabled, PCII440FXState),
221 VMSTATE_END_OF_LIST()
222 }
223};
224
225static int i440fx_pcihost_initfn(SysBusDevice *dev)
226{
227 I440FXState *s = FROM_SYSBUS(I440FXState, dev);
228
229 memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
230 "pci-conf-idx", 4);
231 sysbus_add_io(dev, 0xcf8, &s->conf_mem);
232 sysbus_init_ioports(&s->busdev, 0xcf8, 4);
233
234 memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
235 "pci-conf-data", 4);
236 sysbus_add_io(dev, 0xcfc, &s->data_mem);
237 sysbus_init_ioports(&s->busdev, 0xcfc, 4);
238
239 return 0;
240}
241
242static int i440fx_initfn(PCIDevice *dev)
243{
244 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
245
246 d->dev.config[I440FX_SMRAM] = 0x02;
247
248 cpu_smm_register(&i440fx_set_smm, d);
249 return 0;
250}
251
252static PCIBus *i440fx_common_init(const char *device_name,
253 PCII440FXState **pi440fx_state,
254 int *piix3_devfn,
255 ISABus **isa_bus, qemu_irq *pic,
256 MemoryRegion *address_space_mem,
257 MemoryRegion *address_space_io,
258 ram_addr_t ram_size,
259 target_phys_addr_t pci_hole_start,
260 target_phys_addr_t pci_hole_size,
261 target_phys_addr_t pci_hole64_start,
262 target_phys_addr_t pci_hole64_size,
263 MemoryRegion *pci_address_space,
264 MemoryRegion *ram_memory)
265{
266 DeviceState *dev;
267 PCIBus *b;
268 PCIDevice *d;
269 I440FXState *s;
270 PIIX3State *piix3;
271 PCII440FXState *f;
272
273 dev = qdev_create(NULL, "i440FX-pcihost");
274 s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
275 s->address_space = address_space_mem;
276 b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
277 address_space_io, 0);
278 s->bus = b;
279 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
280 qdev_init_nofail(dev);
281
282 d = pci_create_simple(b, 0, device_name);
283 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
284 f = *pi440fx_state;
285 f->system_memory = address_space_mem;
286 f->pci_address_space = pci_address_space;
287 f->ram_memory = ram_memory;
288 memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
289 pci_hole_start, pci_hole_size);
290 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
291 memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
292 f->pci_address_space,
293 pci_hole64_start, pci_hole64_size);
294 if (pci_hole64_size) {
295 memory_region_add_subregion(f->system_memory, pci_hole64_start,
296 &f->pci_hole_64bit);
297 }
298 memory_region_init_alias(&f->smram_region, "smram-region",
299 f->pci_address_space, 0xa0000, 0x20000);
300 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
301 &f->smram_region, 1);
302 memory_region_set_enabled(&f->smram_region, false);
303
304
305
306
307
308 if (xen_enabled()) {
309 piix3 = DO_UPCAST(PIIX3State, dev,
310 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
311 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
312 piix3, XEN_PIIX_NUM_PIRQS);
313 } else {
314 piix3 = DO_UPCAST(PIIX3State, dev,
315 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
316 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
317 PIIX_NUM_PIRQS);
318 }
319 piix3->pic = pic;
320 *isa_bus = DO_UPCAST(ISABus, qbus,
321 qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
322
323 *piix3_devfn = piix3->dev.devfn;
324
325 ram_size = ram_size / 8 / 1024 / 1024;
326 if (ram_size > 255)
327 ram_size = 255;
328 (*pi440fx_state)->dev.config[0x57]=ram_size;
329
330 i440fx_update_memory_mappings(f);
331
332 return b;
333}
334
335PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
336 ISABus **isa_bus, qemu_irq *pic,
337 MemoryRegion *address_space_mem,
338 MemoryRegion *address_space_io,
339 ram_addr_t ram_size,
340 target_phys_addr_t pci_hole_start,
341 target_phys_addr_t pci_hole_size,
342 target_phys_addr_t pci_hole64_start,
343 target_phys_addr_t pci_hole64_size,
344 MemoryRegion *pci_memory, MemoryRegion *ram_memory)
345
346{
347 PCIBus *b;
348
349 b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
350 address_space_mem, address_space_io, ram_size,
351 pci_hole_start, pci_hole_size,
352 pci_hole64_start, pci_hole64_size,
353 pci_memory, ram_memory);
354 return b;
355}
356
357
358static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
359{
360 qemu_set_irq(piix3->pic[pic_irq],
361 !!(piix3->pic_levels &
362 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
363 (pic_irq * PIIX_NUM_PIRQS))));
364}
365
366static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
367{
368 int pic_irq;
369 uint64_t mask;
370
371 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
372 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
373 return;
374 }
375
376 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
377 piix3->pic_levels &= ~mask;
378 piix3->pic_levels |= mask * !!level;
379
380 piix3_set_irq_pic(piix3, pic_irq);
381}
382
383static void piix3_set_irq(void *opaque, int pirq, int level)
384{
385 PIIX3State *piix3 = opaque;
386 piix3_set_irq_level(piix3, pirq, level);
387}
388
389
390static void piix3_update_irq_levels(PIIX3State *piix3)
391{
392 int pirq;
393
394 piix3->pic_levels = 0;
395 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
396 piix3_set_irq_level(piix3, pirq,
397 pci_bus_get_irq_level(piix3->dev.bus, pirq));
398 }
399}
400
401static void piix3_write_config(PCIDevice *dev,
402 uint32_t address, uint32_t val, int len)
403{
404 pci_default_write_config(dev, address, val, len);
405 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
406 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
407 int pic_irq;
408 piix3_update_irq_levels(piix3);
409 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
410 piix3_set_irq_pic(piix3, pic_irq);
411 }
412 }
413}
414
415static void piix3_write_config_xen(PCIDevice *dev,
416 uint32_t address, uint32_t val, int len)
417{
418 xen_piix_pci_write_config_client(address, val, len);
419 piix3_write_config(dev, address, val, len);
420}
421
422static void piix3_reset(void *opaque)
423{
424 PIIX3State *d = opaque;
425 uint8_t *pci_conf = d->dev.config;
426
427 pci_conf[0x04] = 0x07;
428 pci_conf[0x05] = 0x00;
429 pci_conf[0x06] = 0x00;
430 pci_conf[0x07] = 0x02;
431 pci_conf[0x4c] = 0x4d;
432 pci_conf[0x4e] = 0x03;
433 pci_conf[0x4f] = 0x00;
434 pci_conf[0x60] = 0x80;
435 pci_conf[0x61] = 0x80;
436 pci_conf[0x62] = 0x80;
437 pci_conf[0x63] = 0x80;
438 pci_conf[0x69] = 0x02;
439 pci_conf[0x70] = 0x80;
440 pci_conf[0x76] = 0x0c;
441 pci_conf[0x77] = 0x0c;
442 pci_conf[0x78] = 0x02;
443 pci_conf[0x79] = 0x00;
444 pci_conf[0x80] = 0x00;
445 pci_conf[0x82] = 0x00;
446 pci_conf[0xa0] = 0x08;
447 pci_conf[0xa2] = 0x00;
448 pci_conf[0xa3] = 0x00;
449 pci_conf[0xa4] = 0x00;
450 pci_conf[0xa5] = 0x00;
451 pci_conf[0xa6] = 0x00;
452 pci_conf[0xa7] = 0x00;
453 pci_conf[0xa8] = 0x0f;
454 pci_conf[0xaa] = 0x00;
455 pci_conf[0xab] = 0x00;
456 pci_conf[0xac] = 0x00;
457 pci_conf[0xae] = 0x00;
458
459 d->pic_levels = 0;
460}
461
462static int piix3_post_load(void *opaque, int version_id)
463{
464 PIIX3State *piix3 = opaque;
465 piix3_update_irq_levels(piix3);
466 return 0;
467}
468
469static void piix3_pre_save(void *opaque)
470{
471 int i;
472 PIIX3State *piix3 = opaque;
473
474 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
475 piix3->pci_irq_levels_vmstate[i] =
476 pci_bus_get_irq_level(piix3->dev.bus, i);
477 }
478}
479
480static const VMStateDescription vmstate_piix3 = {
481 .name = "PIIX3",
482 .version_id = 3,
483 .minimum_version_id = 2,
484 .minimum_version_id_old = 2,
485 .post_load = piix3_post_load,
486 .pre_save = piix3_pre_save,
487 .fields = (VMStateField []) {
488 VMSTATE_PCI_DEVICE(dev, PIIX3State),
489 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
490 PIIX_NUM_PIRQS, 3),
491 VMSTATE_END_OF_LIST()
492 }
493};
494
495static int piix3_initfn(PCIDevice *dev)
496{
497 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
498
499 isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
500 qemu_register_reset(piix3_reset, d);
501 return 0;
502}
503
504static void piix3_class_init(ObjectClass *klass, void *data)
505{
506 DeviceClass *dc = DEVICE_CLASS(klass);
507 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
508
509 dc->desc = "ISA bridge";
510 dc->vmsd = &vmstate_piix3;
511 dc->no_user = 1,
512 k->no_hotplug = 1;
513 k->init = piix3_initfn;
514 k->config_write = piix3_write_config;
515 k->vendor_id = PCI_VENDOR_ID_INTEL;
516 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
517 k->class_id = PCI_CLASS_BRIDGE_ISA;
518}
519
520static TypeInfo piix3_info = {
521 .name = "PIIX3",
522 .parent = TYPE_PCI_DEVICE,
523 .instance_size = sizeof(PIIX3State),
524 .class_init = piix3_class_init,
525};
526
527static void piix3_xen_class_init(ObjectClass *klass, void *data)
528{
529 DeviceClass *dc = DEVICE_CLASS(klass);
530 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
531
532 dc->desc = "ISA bridge";
533 dc->vmsd = &vmstate_piix3;
534 dc->no_user = 1;
535 k->no_hotplug = 1;
536 k->init = piix3_initfn;
537 k->config_write = piix3_write_config_xen;
538 k->vendor_id = PCI_VENDOR_ID_INTEL;
539 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
540 k->class_id = PCI_CLASS_BRIDGE_ISA;
541};
542
543static TypeInfo piix3_xen_info = {
544 .name = "PIIX3-xen",
545 .parent = TYPE_PCI_DEVICE,
546 .instance_size = sizeof(PIIX3State),
547 .class_init = piix3_xen_class_init,
548};
549
550static void i440fx_class_init(ObjectClass *klass, void *data)
551{
552 DeviceClass *dc = DEVICE_CLASS(klass);
553 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
554
555 k->no_hotplug = 1;
556 k->init = i440fx_initfn;
557 k->config_write = i440fx_write_config;
558 k->vendor_id = PCI_VENDOR_ID_INTEL;
559 k->device_id = PCI_DEVICE_ID_INTEL_82441;
560 k->revision = 0x02;
561 k->class_id = PCI_CLASS_BRIDGE_HOST;
562 dc->desc = "Host bridge";
563 dc->no_user = 1;
564 dc->vmsd = &vmstate_i440fx;
565}
566
567static TypeInfo i440fx_info = {
568 .name = "i440FX",
569 .parent = TYPE_PCI_DEVICE,
570 .instance_size = sizeof(PCII440FXState),
571 .class_init = i440fx_class_init,
572};
573
574static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
575{
576 DeviceClass *dc = DEVICE_CLASS(klass);
577 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
578
579 k->init = i440fx_pcihost_initfn;
580 dc->fw_name = "pci";
581 dc->no_user = 1;
582}
583
584static TypeInfo i440fx_pcihost_info = {
585 .name = "i440FX-pcihost",
586 .parent = TYPE_SYS_BUS_DEVICE,
587 .instance_size = sizeof(I440FXState),
588 .class_init = i440fx_pcihost_class_init,
589};
590
591static void i440fx_register_types(void)
592{
593 type_register_static(&i440fx_info);
594 type_register_static(&piix3_info);
595 type_register_static(&piix3_xen_info);
596 type_register_static(&i440fx_pcihost_info);
597}
598
599type_init(i440fx_register_types)
600
