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29#include "sysbus.h"
30#include "strongarm.h"
31#include "qemu-error.h"
32#include "arm-misc.h"
33#include "sysemu.h"
34#include "ssi.h"
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54
55#ifdef DEBUG
56# define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
57#else
58# define DPRINTF(format, ...) do { } while (0)
59#endif
60
61static struct {
62 target_phys_addr_t io_base;
63 int irq;
64} sa_serial[] = {
65 { 0x80010000, SA_PIC_UART1 },
66 { 0x80030000, SA_PIC_UART2 },
67 { 0x80050000, SA_PIC_UART3 },
68 { 0, 0 }
69};
70
71
72typedef struct {
73 SysBusDevice busdev;
74 MemoryRegion iomem;
75 qemu_irq irq;
76 qemu_irq fiq;
77
78 uint32_t pending;
79 uint32_t enabled;
80 uint32_t is_fiq;
81 uint32_t int_idle;
82} StrongARMPICState;
83
84#define ICIP 0x00
85#define ICMR 0x04
86#define ICLR 0x08
87#define ICFP 0x10
88#define ICPR 0x20
89#define ICCR 0x0c
90
91#define SA_PIC_SRCS 32
92
93
94static void strongarm_pic_update(void *opaque)
95{
96 StrongARMPICState *s = opaque;
97
98
99 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
100 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
101}
102
103static void strongarm_pic_set_irq(void *opaque, int irq, int level)
104{
105 StrongARMPICState *s = opaque;
106
107 if (level) {
108 s->pending |= 1 << irq;
109 } else {
110 s->pending &= ~(1 << irq);
111 }
112
113 strongarm_pic_update(s);
114}
115
116static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
117 unsigned size)
118{
119 StrongARMPICState *s = opaque;
120
121 switch (offset) {
122 case ICIP:
123 return s->pending & ~s->is_fiq & s->enabled;
124 case ICMR:
125 return s->enabled;
126 case ICLR:
127 return s->is_fiq;
128 case ICCR:
129 return s->int_idle == 0;
130 case ICFP:
131 return s->pending & s->is_fiq & s->enabled;
132 case ICPR:
133 return s->pending;
134 default:
135 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
136 __func__, offset);
137 return 0;
138 }
139}
140
141static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
142 uint64_t value, unsigned size)
143{
144 StrongARMPICState *s = opaque;
145
146 switch (offset) {
147 case ICMR:
148 s->enabled = value;
149 break;
150 case ICLR:
151 s->is_fiq = value;
152 break;
153 case ICCR:
154 s->int_idle = (value & 1) ? 0 : ~0;
155 break;
156 default:
157 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
158 __func__, offset);
159 break;
160 }
161 strongarm_pic_update(s);
162}
163
164static const MemoryRegionOps strongarm_pic_ops = {
165 .read = strongarm_pic_mem_read,
166 .write = strongarm_pic_mem_write,
167 .endianness = DEVICE_NATIVE_ENDIAN,
168};
169
170static int strongarm_pic_initfn(SysBusDevice *dev)
171{
172 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
173
174 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
175 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
176 sysbus_init_mmio(dev, &s->iomem);
177 sysbus_init_irq(dev, &s->irq);
178 sysbus_init_irq(dev, &s->fiq);
179
180 return 0;
181}
182
183static int strongarm_pic_post_load(void *opaque, int version_id)
184{
185 strongarm_pic_update(opaque);
186 return 0;
187}
188
189static VMStateDescription vmstate_strongarm_pic_regs = {
190 .name = "strongarm_pic",
191 .version_id = 0,
192 .minimum_version_id = 0,
193 .minimum_version_id_old = 0,
194 .post_load = strongarm_pic_post_load,
195 .fields = (VMStateField[]) {
196 VMSTATE_UINT32(pending, StrongARMPICState),
197 VMSTATE_UINT32(enabled, StrongARMPICState),
198 VMSTATE_UINT32(is_fiq, StrongARMPICState),
199 VMSTATE_UINT32(int_idle, StrongARMPICState),
200 VMSTATE_END_OF_LIST(),
201 },
202};
203
204static void strongarm_pic_class_init(ObjectClass *klass, void *data)
205{
206 DeviceClass *dc = DEVICE_CLASS(klass);
207 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
208
209 k->init = strongarm_pic_initfn;
210 dc->desc = "StrongARM PIC";
211 dc->vmsd = &vmstate_strongarm_pic_regs;
212}
213
214static TypeInfo strongarm_pic_info = {
215 .name = "strongarm_pic",
216 .parent = TYPE_SYS_BUS_DEVICE,
217 .instance_size = sizeof(StrongARMPICState),
218 .class_init = strongarm_pic_class_init,
219};
220
221
222#define RTAR 0x00
223#define RCNR 0x04
224#define RTTR 0x08
225#define RTSR 0x10
226
227#define RTSR_AL (1 << 0)
228#define RTSR_HZ (1 << 1)
229#define RTSR_ALE (1 << 2)
230#define RTSR_HZE (1 << 3)
231
232
233
234
235
236typedef struct {
237 SysBusDevice busdev;
238 MemoryRegion iomem;
239 uint32_t rttr;
240 uint32_t rtsr;
241 uint32_t rtar;
242 uint32_t last_rcnr;
243 int64_t last_hz;
244 QEMUTimer *rtc_alarm;
245 QEMUTimer *rtc_hz;
246 qemu_irq rtc_irq;
247 qemu_irq rtc_hz_irq;
248} StrongARMRTCState;
249
250static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
251{
252 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
253 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
254}
255
256static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
257{
258 int64_t rt = qemu_get_clock_ms(rtc_clock);
259 s->last_rcnr += ((rt - s->last_hz) << 15) /
260 (1000 * ((s->rttr & 0xffff) + 1));
261 s->last_hz = rt;
262}
263
264static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
265{
266 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
267 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
268 } else {
269 qemu_del_timer(s->rtc_hz);
270 }
271
272 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
273 qemu_mod_timer(s->rtc_alarm, s->last_hz +
274 (((s->rtar - s->last_rcnr) * 1000 *
275 ((s->rttr & 0xffff) + 1)) >> 15));
276 } else {
277 qemu_del_timer(s->rtc_alarm);
278 }
279}
280
281static inline void strongarm_rtc_alarm_tick(void *opaque)
282{
283 StrongARMRTCState *s = opaque;
284 s->rtsr |= RTSR_AL;
285 strongarm_rtc_timer_update(s);
286 strongarm_rtc_int_update(s);
287}
288
289static inline void strongarm_rtc_hz_tick(void *opaque)
290{
291 StrongARMRTCState *s = opaque;
292 s->rtsr |= RTSR_HZ;
293 strongarm_rtc_timer_update(s);
294 strongarm_rtc_int_update(s);
295}
296
297static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
298 unsigned size)
299{
300 StrongARMRTCState *s = opaque;
301
302 switch (addr) {
303 case RTTR:
304 return s->rttr;
305 case RTSR:
306 return s->rtsr;
307 case RTAR:
308 return s->rtar;
309 case RCNR:
310 return s->last_rcnr +
311 ((qemu_get_clock_ms(rtc_clock) - s->last_hz) << 15) /
312 (1000 * ((s->rttr & 0xffff) + 1));
313 default:
314 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
315 return 0;
316 }
317}
318
319static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
320 uint64_t value, unsigned size)
321{
322 StrongARMRTCState *s = opaque;
323 uint32_t old_rtsr;
324
325 switch (addr) {
326 case RTTR:
327 strongarm_rtc_hzupdate(s);
328 s->rttr = value;
329 strongarm_rtc_timer_update(s);
330 break;
331
332 case RTSR:
333 old_rtsr = s->rtsr;
334 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
335 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
336
337 if (s->rtsr != old_rtsr) {
338 strongarm_rtc_timer_update(s);
339 }
340
341 strongarm_rtc_int_update(s);
342 break;
343
344 case RTAR:
345 s->rtar = value;
346 strongarm_rtc_timer_update(s);
347 break;
348
349 case RCNR:
350 strongarm_rtc_hzupdate(s);
351 s->last_rcnr = value;
352 strongarm_rtc_timer_update(s);
353 break;
354
355 default:
356 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
357 }
358}
359
360static const MemoryRegionOps strongarm_rtc_ops = {
361 .read = strongarm_rtc_read,
362 .write = strongarm_rtc_write,
363 .endianness = DEVICE_NATIVE_ENDIAN,
364};
365
366static int strongarm_rtc_init(SysBusDevice *dev)
367{
368 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
369 struct tm tm;
370
371 s->rttr = 0x0;
372 s->rtsr = 0;
373
374 qemu_get_timedate(&tm, 0);
375
376 s->last_rcnr = (uint32_t) mktimegm(&tm);
377 s->last_hz = qemu_get_clock_ms(rtc_clock);
378
379 s->rtc_alarm = qemu_new_timer_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
380 s->rtc_hz = qemu_new_timer_ms(rtc_clock, strongarm_rtc_hz_tick, s);
381
382 sysbus_init_irq(dev, &s->rtc_irq);
383 sysbus_init_irq(dev, &s->rtc_hz_irq);
384
385 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
386 sysbus_init_mmio(dev, &s->iomem);
387
388 return 0;
389}
390
391static void strongarm_rtc_pre_save(void *opaque)
392{
393 StrongARMRTCState *s = opaque;
394
395 strongarm_rtc_hzupdate(s);
396}
397
398static int strongarm_rtc_post_load(void *opaque, int version_id)
399{
400 StrongARMRTCState *s = opaque;
401
402 strongarm_rtc_timer_update(s);
403 strongarm_rtc_int_update(s);
404
405 return 0;
406}
407
408static const VMStateDescription vmstate_strongarm_rtc_regs = {
409 .name = "strongarm-rtc",
410 .version_id = 0,
411 .minimum_version_id = 0,
412 .minimum_version_id_old = 0,
413 .pre_save = strongarm_rtc_pre_save,
414 .post_load = strongarm_rtc_post_load,
415 .fields = (VMStateField[]) {
416 VMSTATE_UINT32(rttr, StrongARMRTCState),
417 VMSTATE_UINT32(rtsr, StrongARMRTCState),
418 VMSTATE_UINT32(rtar, StrongARMRTCState),
419 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
420 VMSTATE_INT64(last_hz, StrongARMRTCState),
421 VMSTATE_END_OF_LIST(),
422 },
423};
424
425static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
426{
427 DeviceClass *dc = DEVICE_CLASS(klass);
428 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
429
430 k->init = strongarm_rtc_init;
431 dc->desc = "StrongARM RTC Controller";
432 dc->vmsd = &vmstate_strongarm_rtc_regs;
433}
434
435static TypeInfo strongarm_rtc_sysbus_info = {
436 .name = "strongarm-rtc",
437 .parent = TYPE_SYS_BUS_DEVICE,
438 .instance_size = sizeof(StrongARMRTCState),
439 .class_init = strongarm_rtc_sysbus_class_init,
440};
441
442
443#define GPLR 0x00
444#define GPDR 0x04
445#define GPSR 0x08
446#define GPCR 0x0c
447#define GRER 0x10
448#define GFER 0x14
449#define GEDR 0x18
450#define GAFR 0x1c
451
452typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
453struct StrongARMGPIOInfo {
454 SysBusDevice busdev;
455 MemoryRegion iomem;
456 qemu_irq handler[28];
457 qemu_irq irqs[11];
458 qemu_irq irqX;
459
460 uint32_t ilevel;
461 uint32_t olevel;
462 uint32_t dir;
463 uint32_t rising;
464 uint32_t falling;
465 uint32_t status;
466 uint32_t gpsr;
467 uint32_t gafr;
468
469 uint32_t prev_level;
470};
471
472
473static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
474{
475 int i;
476 for (i = 0; i < 11; i++) {
477 qemu_set_irq(s->irqs[i], s->status & (1 << i));
478 }
479
480 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
481}
482
483static void strongarm_gpio_set(void *opaque, int line, int level)
484{
485 StrongARMGPIOInfo *s = opaque;
486 uint32_t mask;
487
488 mask = 1 << line;
489
490 if (level) {
491 s->status |= s->rising & mask &
492 ~s->ilevel & ~s->dir;
493 s->ilevel |= mask;
494 } else {
495 s->status |= s->falling & mask &
496 s->ilevel & ~s->dir;
497 s->ilevel &= ~mask;
498 }
499
500 if (s->status & mask) {
501 strongarm_gpio_irq_update(s);
502 }
503}
504
505static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
506{
507 uint32_t level, diff;
508 int bit;
509
510 level = s->olevel & s->dir;
511
512 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
513 bit = ffs(diff) - 1;
514 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
515 }
516
517 s->prev_level = level;
518}
519
520static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
521 unsigned size)
522{
523 StrongARMGPIOInfo *s = opaque;
524
525 switch (offset) {
526 case GPDR:
527 return s->dir;
528
529 case GPSR:
530 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
531 __func__, offset);
532 return s->gpsr;
533
534 case GPCR:
535 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
536 __func__, offset);
537 return 31337;
538
539 case GRER:
540 return s->rising;
541
542 case GFER:
543 return s->falling;
544
545 case GAFR:
546 return s->gafr;
547
548 case GPLR:
549 return (s->olevel & s->dir) |
550 (s->ilevel & ~s->dir);
551
552 case GEDR:
553 return s->status;
554
555 default:
556 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
557 }
558
559 return 0;
560}
561
562static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
563 uint64_t value, unsigned size)
564{
565 StrongARMGPIOInfo *s = opaque;
566
567 switch (offset) {
568 case GPDR:
569 s->dir = value;
570 strongarm_gpio_handler_update(s);
571 break;
572
573 case GPSR:
574 s->olevel |= value;
575 strongarm_gpio_handler_update(s);
576 s->gpsr = value;
577 break;
578
579 case GPCR:
580 s->olevel &= ~value;
581 strongarm_gpio_handler_update(s);
582 break;
583
584 case GRER:
585 s->rising = value;
586 break;
587
588 case GFER:
589 s->falling = value;
590 break;
591
592 case GAFR:
593 s->gafr = value;
594 break;
595
596 case GEDR:
597 s->status &= ~value;
598 strongarm_gpio_irq_update(s);
599 break;
600
601 default:
602 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
603 }
604}
605
606static const MemoryRegionOps strongarm_gpio_ops = {
607 .read = strongarm_gpio_read,
608 .write = strongarm_gpio_write,
609 .endianness = DEVICE_NATIVE_ENDIAN,
610};
611
612static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
613 DeviceState *pic)
614{
615 DeviceState *dev;
616 int i;
617
618 dev = qdev_create(NULL, "strongarm-gpio");
619 qdev_init_nofail(dev);
620
621 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
622 for (i = 0; i < 12; i++)
623 sysbus_connect_irq(sysbus_from_qdev(dev), i,
624 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
625
626 return dev;
627}
628
629static int strongarm_gpio_initfn(SysBusDevice *dev)
630{
631 StrongARMGPIOInfo *s;
632 int i;
633
634 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
635
636 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
637 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
638
639 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
640
641 sysbus_init_mmio(dev, &s->iomem);
642 for (i = 0; i < 11; i++) {
643 sysbus_init_irq(dev, &s->irqs[i]);
644 }
645 sysbus_init_irq(dev, &s->irqX);
646
647 return 0;
648}
649
650static const VMStateDescription vmstate_strongarm_gpio_regs = {
651 .name = "strongarm-gpio",
652 .version_id = 0,
653 .minimum_version_id = 0,
654 .minimum_version_id_old = 0,
655 .fields = (VMStateField[]) {
656 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
657 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
658 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
659 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
660 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
661 VMSTATE_UINT32(status, StrongARMGPIOInfo),
662 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
663 VMSTATE_END_OF_LIST(),
664 },
665};
666
667static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
668{
669 DeviceClass *dc = DEVICE_CLASS(klass);
670 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
671
672 k->init = strongarm_gpio_initfn;
673 dc->desc = "StrongARM GPIO controller";
674}
675
676static TypeInfo strongarm_gpio_info = {
677 .name = "strongarm-gpio",
678 .parent = TYPE_SYS_BUS_DEVICE,
679 .instance_size = sizeof(StrongARMGPIOInfo),
680 .class_init = strongarm_gpio_class_init,
681};
682
683
684#define PPDR 0x00
685#define PPSR 0x04
686#define PPAR 0x08
687#define PSDR 0x0c
688#define PPFR 0x10
689
690typedef struct StrongARMPPCInfo StrongARMPPCInfo;
691struct StrongARMPPCInfo {
692 SysBusDevice busdev;
693 MemoryRegion iomem;
694 qemu_irq handler[28];
695
696 uint32_t ilevel;
697 uint32_t olevel;
698 uint32_t dir;
699 uint32_t ppar;
700 uint32_t psdr;
701 uint32_t ppfr;
702
703 uint32_t prev_level;
704};
705
706static void strongarm_ppc_set(void *opaque, int line, int level)
707{
708 StrongARMPPCInfo *s = opaque;
709
710 if (level) {
711 s->ilevel |= 1 << line;
712 } else {
713 s->ilevel &= ~(1 << line);
714 }
715}
716
717static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
718{
719 uint32_t level, diff;
720 int bit;
721
722 level = s->olevel & s->dir;
723
724 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
725 bit = ffs(diff) - 1;
726 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
727 }
728
729 s->prev_level = level;
730}
731
732static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
733 unsigned size)
734{
735 StrongARMPPCInfo *s = opaque;
736
737 switch (offset) {
738 case PPDR:
739 return s->dir | ~0x3fffff;
740
741 case PPSR:
742 return (s->olevel & s->dir) |
743 (s->ilevel & ~s->dir) |
744 ~0x3fffff;
745
746 case PPAR:
747 return s->ppar | ~0x41000;
748
749 case PSDR:
750 return s->psdr;
751
752 case PPFR:
753 return s->ppfr | ~0x7f001;
754
755 default:
756 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
757 }
758
759 return 0;
760}
761
762static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
763 uint64_t value, unsigned size)
764{
765 StrongARMPPCInfo *s = opaque;
766
767 switch (offset) {
768 case PPDR:
769 s->dir = value & 0x3fffff;
770 strongarm_ppc_handler_update(s);
771 break;
772
773 case PPSR:
774 s->olevel = value & s->dir & 0x3fffff;
775 strongarm_ppc_handler_update(s);
776 break;
777
778 case PPAR:
779 s->ppar = value & 0x41000;
780 break;
781
782 case PSDR:
783 s->psdr = value & 0x3fffff;
784 break;
785
786 case PPFR:
787 s->ppfr = value & 0x7f001;
788 break;
789
790 default:
791 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
792 }
793}
794
795static const MemoryRegionOps strongarm_ppc_ops = {
796 .read = strongarm_ppc_read,
797 .write = strongarm_ppc_write,
798 .endianness = DEVICE_NATIVE_ENDIAN,
799};
800
801static int strongarm_ppc_init(SysBusDevice *dev)
802{
803 StrongARMPPCInfo *s;
804
805 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
806
807 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
808 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
809
810 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
811
812 sysbus_init_mmio(dev, &s->iomem);
813
814 return 0;
815}
816
817static const VMStateDescription vmstate_strongarm_ppc_regs = {
818 .name = "strongarm-ppc",
819 .version_id = 0,
820 .minimum_version_id = 0,
821 .minimum_version_id_old = 0,
822 .fields = (VMStateField[]) {
823 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
824 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
825 VMSTATE_UINT32(dir, StrongARMPPCInfo),
826 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
827 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
828 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
829 VMSTATE_END_OF_LIST(),
830 },
831};
832
833static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
834{
835 DeviceClass *dc = DEVICE_CLASS(klass);
836 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
837
838 k->init = strongarm_ppc_init;
839 dc->desc = "StrongARM PPC controller";
840}
841
842static TypeInfo strongarm_ppc_info = {
843 .name = "strongarm-ppc",
844 .parent = TYPE_SYS_BUS_DEVICE,
845 .instance_size = sizeof(StrongARMPPCInfo),
846 .class_init = strongarm_ppc_class_init,
847};
848
849
850#define UTCR0 0x00
851#define UTCR1 0x04
852#define UTCR2 0x08
853#define UTCR3 0x0c
854#define UTDR 0x14
855#define UTSR0 0x1c
856#define UTSR1 0x20
857
858#define UTCR0_PE (1 << 0)
859#define UTCR0_OES (1 << 1)
860#define UTCR0_SBS (1 << 2)
861#define UTCR0_DSS (1 << 3)
862
863#define UTCR3_RXE (1 << 0)
864#define UTCR3_TXE (1 << 1)
865#define UTCR3_BRK (1 << 2)
866#define UTCR3_RIE (1 << 3)
867#define UTCR3_TIE (1 << 4)
868#define UTCR3_LBM (1 << 5)
869
870#define UTSR0_TFS (1 << 0)
871#define UTSR0_RFS (1 << 1)
872#define UTSR0_RID (1 << 2)
873#define UTSR0_RBB (1 << 3)
874#define UTSR0_REB (1 << 4)
875#define UTSR0_EIF (1 << 5)
876
877#define UTSR1_RNE (1 << 1)
878#define UTSR1_TNF (1 << 2)
879#define UTSR1_PRE (1 << 3)
880#define UTSR1_FRE (1 << 4)
881#define UTSR1_ROR (1 << 5)
882
883#define RX_FIFO_PRE (1 << 8)
884#define RX_FIFO_FRE (1 << 9)
885#define RX_FIFO_ROR (1 << 10)
886
887typedef struct {
888 SysBusDevice busdev;
889 MemoryRegion iomem;
890 CharDriverState *chr;
891 qemu_irq irq;
892
893 uint8_t utcr0;
894 uint16_t brd;
895 uint8_t utcr3;
896 uint8_t utsr0;
897 uint8_t utsr1;
898
899 uint8_t tx_fifo[8];
900 uint8_t tx_start;
901 uint8_t tx_len;
902 uint16_t rx_fifo[12];
903 uint8_t rx_start;
904 uint8_t rx_len;
905
906 uint64_t char_transmit_time;
907 bool wait_break_end;
908 QEMUTimer *rx_timeout_timer;
909 QEMUTimer *tx_timer;
910} StrongARMUARTState;
911
912static void strongarm_uart_update_status(StrongARMUARTState *s)
913{
914 uint16_t utsr1 = 0;
915
916 if (s->tx_len != 8) {
917 utsr1 |= UTSR1_TNF;
918 }
919
920 if (s->rx_len != 0) {
921 uint16_t ent = s->rx_fifo[s->rx_start];
922
923 utsr1 |= UTSR1_RNE;
924 if (ent & RX_FIFO_PRE) {
925 s->utsr1 |= UTSR1_PRE;
926 }
927 if (ent & RX_FIFO_FRE) {
928 s->utsr1 |= UTSR1_FRE;
929 }
930 if (ent & RX_FIFO_ROR) {
931 s->utsr1 |= UTSR1_ROR;
932 }
933 }
934
935 s->utsr1 = utsr1;
936}
937
938static void strongarm_uart_update_int_status(StrongARMUARTState *s)
939{
940 uint16_t utsr0 = s->utsr0 &
941 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
942 int i;
943
944 if ((s->utcr3 & UTCR3_TXE) &&
945 (s->utcr3 & UTCR3_TIE) &&
946 s->tx_len <= 4) {
947 utsr0 |= UTSR0_TFS;
948 }
949
950 if ((s->utcr3 & UTCR3_RXE) &&
951 (s->utcr3 & UTCR3_RIE) &&
952 s->rx_len > 4) {
953 utsr0 |= UTSR0_RFS;
954 }
955
956 for (i = 0; i < s->rx_len && i < 4; i++)
957 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
958 utsr0 |= UTSR0_EIF;
959 break;
960 }
961
962 s->utsr0 = utsr0;
963 qemu_set_irq(s->irq, utsr0);
964}
965
966static void strongarm_uart_update_parameters(StrongARMUARTState *s)
967{
968 int speed, parity, data_bits, stop_bits, frame_size;
969 QEMUSerialSetParams ssp;
970
971
972 frame_size = 1;
973 if (s->utcr0 & UTCR0_PE) {
974
975 frame_size++;
976 if (s->utcr0 & UTCR0_OES) {
977 parity = 'E';
978 } else {
979 parity = 'O';
980 }
981 } else {
982 parity = 'N';
983 }
984 if (s->utcr0 & UTCR0_SBS) {
985 stop_bits = 2;
986 } else {
987 stop_bits = 1;
988 }
989
990 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
991 frame_size += data_bits + stop_bits;
992 speed = 3686400 / 16 / (s->brd + 1);
993 ssp.speed = speed;
994 ssp.parity = parity;
995 ssp.data_bits = data_bits;
996 ssp.stop_bits = stop_bits;
997 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
998 if (s->chr) {
999 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1000 }
1001
1002 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1003 speed, parity, data_bits, stop_bits);
1004}
1005
1006static void strongarm_uart_rx_to(void *opaque)
1007{
1008 StrongARMUARTState *s = opaque;
1009
1010 if (s->rx_len) {
1011 s->utsr0 |= UTSR0_RID;
1012 strongarm_uart_update_int_status(s);
1013 }
1014}
1015
1016static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1017{
1018 if ((s->utcr3 & UTCR3_RXE) == 0) {
1019
1020 return;
1021 }
1022
1023 if (s->wait_break_end) {
1024 s->utsr0 |= UTSR0_REB;
1025 s->wait_break_end = false;
1026 }
1027
1028 if (s->rx_len < 12) {
1029 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1030 s->rx_len++;
1031 } else
1032 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1033}
1034
1035static int strongarm_uart_can_receive(void *opaque)
1036{
1037 StrongARMUARTState *s = opaque;
1038
1039 if (s->rx_len == 12) {
1040 return 0;
1041 }
1042
1043 if (s->rx_len < 8) {
1044 return 8 - s->rx_len;
1045 }
1046 return 1;
1047}
1048
1049static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1050{
1051 StrongARMUARTState *s = opaque;
1052 int i;
1053
1054 for (i = 0; i < size; i++) {
1055 strongarm_uart_rx_push(s, buf[i]);
1056 }
1057
1058
1059 qemu_mod_timer(s->rx_timeout_timer,
1060 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1061
1062 strongarm_uart_update_status(s);
1063 strongarm_uart_update_int_status(s);
1064}
1065
1066static void strongarm_uart_event(void *opaque, int event)
1067{
1068 StrongARMUARTState *s = opaque;
1069 if (event == CHR_EVENT_BREAK) {
1070 s->utsr0 |= UTSR0_RBB;
1071 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1072 s->wait_break_end = true;
1073 strongarm_uart_update_status(s);
1074 strongarm_uart_update_int_status(s);
1075 }
1076}
1077
1078static void strongarm_uart_tx(void *opaque)
1079{
1080 StrongARMUARTState *s = opaque;
1081 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1082
1083 if (s->utcr3 & UTCR3_LBM) {
1084 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1085 } else if (s->chr) {
1086 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1087 }
1088
1089 s->tx_start = (s->tx_start + 1) % 8;
1090 s->tx_len--;
1091 if (s->tx_len) {
1092 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1093 }
1094 strongarm_uart_update_status(s);
1095 strongarm_uart_update_int_status(s);
1096}
1097
1098static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
1099 unsigned size)
1100{
1101 StrongARMUARTState *s = opaque;
1102 uint16_t ret;
1103
1104 switch (addr) {
1105 case UTCR0:
1106 return s->utcr0;
1107
1108 case UTCR1:
1109 return s->brd >> 8;
1110
1111 case UTCR2:
1112 return s->brd & 0xff;
1113
1114 case UTCR3:
1115 return s->utcr3;
1116
1117 case UTDR:
1118 if (s->rx_len != 0) {
1119 ret = s->rx_fifo[s->rx_start];
1120 s->rx_start = (s->rx_start + 1) % 12;
1121 s->rx_len--;
1122 strongarm_uart_update_status(s);
1123 strongarm_uart_update_int_status(s);
1124 return ret;
1125 }
1126 return 0;
1127
1128 case UTSR0:
1129 return s->utsr0;
1130
1131 case UTSR1:
1132 return s->utsr1;
1133
1134 default:
1135 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1136 return 0;
1137 }
1138}
1139
1140static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1141 uint64_t value, unsigned size)
1142{
1143 StrongARMUARTState *s = opaque;
1144
1145 switch (addr) {
1146 case UTCR0:
1147 s->utcr0 = value & 0x7f;
1148 strongarm_uart_update_parameters(s);
1149 break;
1150
1151 case UTCR1:
1152 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1153 strongarm_uart_update_parameters(s);
1154 break;
1155
1156 case UTCR2:
1157 s->brd = (s->brd & 0xf00) | (value & 0xff);
1158 strongarm_uart_update_parameters(s);
1159 break;
1160
1161 case UTCR3:
1162 s->utcr3 = value & 0x3f;
1163 if ((s->utcr3 & UTCR3_RXE) == 0) {
1164 s->rx_len = 0;
1165 }
1166 if ((s->utcr3 & UTCR3_TXE) == 0) {
1167 s->tx_len = 0;
1168 }
1169 strongarm_uart_update_status(s);
1170 strongarm_uart_update_int_status(s);
1171 break;
1172
1173 case UTDR:
1174 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1175 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1176 s->tx_len++;
1177 strongarm_uart_update_status(s);
1178 strongarm_uart_update_int_status(s);
1179 if (s->tx_len == 1) {
1180 strongarm_uart_tx(s);
1181 }
1182 }
1183 break;
1184
1185 case UTSR0:
1186 s->utsr0 = s->utsr0 & ~(value &
1187 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1188 strongarm_uart_update_int_status(s);
1189 break;
1190
1191 default:
1192 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1193 }
1194}
1195
1196static const MemoryRegionOps strongarm_uart_ops = {
1197 .read = strongarm_uart_read,
1198 .write = strongarm_uart_write,
1199 .endianness = DEVICE_NATIVE_ENDIAN,
1200};
1201
1202static int strongarm_uart_init(SysBusDevice *dev)
1203{
1204 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1205
1206 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1207 sysbus_init_mmio(dev, &s->iomem);
1208 sysbus_init_irq(dev, &s->irq);
1209
1210 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1211 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1212
1213 if (s->chr) {
1214 qemu_chr_add_handlers(s->chr,
1215 strongarm_uart_can_receive,
1216 strongarm_uart_receive,
1217 strongarm_uart_event,
1218 s);
1219 }
1220
1221 return 0;
1222}
1223
1224static void strongarm_uart_reset(DeviceState *dev)
1225{
1226 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1227
1228 s->utcr0 = UTCR0_DSS;
1229 s->brd = 23;
1230
1231 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1232
1233 s->rx_len = s->tx_len = 0;
1234
1235 strongarm_uart_update_parameters(s);
1236 strongarm_uart_update_status(s);
1237 strongarm_uart_update_int_status(s);
1238}
1239
1240static int strongarm_uart_post_load(void *opaque, int version_id)
1241{
1242 StrongARMUARTState *s = opaque;
1243
1244 strongarm_uart_update_parameters(s);
1245 strongarm_uart_update_status(s);
1246 strongarm_uart_update_int_status(s);
1247
1248
1249 if (s->tx_len) {
1250 strongarm_uart_tx(s);
1251 }
1252
1253
1254 if (s->rx_len) {
1255 qemu_mod_timer(s->rx_timeout_timer,
1256 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1257 }
1258
1259 return 0;
1260}
1261
1262static const VMStateDescription vmstate_strongarm_uart_regs = {
1263 .name = "strongarm-uart",
1264 .version_id = 0,
1265 .minimum_version_id = 0,
1266 .minimum_version_id_old = 0,
1267 .post_load = strongarm_uart_post_load,
1268 .fields = (VMStateField[]) {
1269 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1270 VMSTATE_UINT16(brd, StrongARMUARTState),
1271 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1272 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1273 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1274 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1275 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1276 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1277 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1278 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1279 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1280 VMSTATE_END_OF_LIST(),
1281 },
1282};
1283
1284static Property strongarm_uart_properties[] = {
1285 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1286 DEFINE_PROP_END_OF_LIST(),
1287};
1288
1289static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1290{
1291 DeviceClass *dc = DEVICE_CLASS(klass);
1292 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1293
1294 k->init = strongarm_uart_init;
1295 dc->desc = "StrongARM UART controller";
1296 dc->reset = strongarm_uart_reset;
1297 dc->vmsd = &vmstate_strongarm_uart_regs;
1298 dc->props = strongarm_uart_properties;
1299}
1300
1301static TypeInfo strongarm_uart_info = {
1302 .name = "strongarm-uart",
1303 .parent = TYPE_SYS_BUS_DEVICE,
1304 .instance_size = sizeof(StrongARMUARTState),
1305 .class_init = strongarm_uart_class_init,
1306};
1307
1308
1309typedef struct {
1310 SysBusDevice busdev;
1311 MemoryRegion iomem;
1312 qemu_irq irq;
1313 SSIBus *bus;
1314
1315 uint16_t sscr[2];
1316 uint16_t sssr;
1317
1318 uint16_t rx_fifo[8];
1319 uint8_t rx_level;
1320 uint8_t rx_start;
1321} StrongARMSSPState;
1322
1323#define SSCR0 0x60
1324#define SSCR1 0x64
1325#define SSDR 0x6c
1326#define SSSR 0x74
1327
1328
1329#define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1330#define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1331#define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1332#define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1333#define SSCR0_SSE (1 << 7)
1334#define SSCR0_DSS(x) (((x) & 0xf) + 1)
1335#define SSCR1_RIE (1 << 0)
1336#define SSCR1_TIE (1 << 1)
1337#define SSCR1_LBM (1 << 2)
1338#define SSSR_TNF (1 << 2)
1339#define SSSR_RNE (1 << 3)
1340#define SSSR_TFS (1 << 5)
1341#define SSSR_RFS (1 << 6)
1342#define SSSR_ROR (1 << 7)
1343#define SSSR_RW 0x0080
1344
1345static void strongarm_ssp_int_update(StrongARMSSPState *s)
1346{
1347 int level = 0;
1348
1349 level |= (s->sssr & SSSR_ROR);
1350 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1351 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1352 qemu_set_irq(s->irq, level);
1353}
1354
1355static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1356{
1357 s->sssr &= ~SSSR_TFS;
1358 s->sssr &= ~SSSR_TNF;
1359 if (s->sscr[0] & SSCR0_SSE) {
1360 if (s->rx_level >= 4) {
1361 s->sssr |= SSSR_RFS;
1362 } else {
1363 s->sssr &= ~SSSR_RFS;
1364 }
1365 if (s->rx_level) {
1366 s->sssr |= SSSR_RNE;
1367 } else {
1368 s->sssr &= ~SSSR_RNE;
1369 }
1370
1371
1372 s->sssr |= SSSR_TFS;
1373 s->sssr |= SSSR_TNF;
1374 }
1375
1376 strongarm_ssp_int_update(s);
1377}
1378
1379static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
1380 unsigned size)
1381{
1382 StrongARMSSPState *s = opaque;
1383 uint32_t retval;
1384
1385 switch (addr) {
1386 case SSCR0:
1387 return s->sscr[0];
1388 case SSCR1:
1389 return s->sscr[1];
1390 case SSSR:
1391 return s->sssr;
1392 case SSDR:
1393 if (~s->sscr[0] & SSCR0_SSE) {
1394 return 0xffffffff;
1395 }
1396 if (s->rx_level < 1) {
1397 printf("%s: SSP Rx Underrun\n", __func__);
1398 return 0xffffffff;
1399 }
1400 s->rx_level--;
1401 retval = s->rx_fifo[s->rx_start++];
1402 s->rx_start &= 0x7;
1403 strongarm_ssp_fifo_update(s);
1404 return retval;
1405 default:
1406 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1407 break;
1408 }
1409 return 0;
1410}
1411
1412static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1413 uint64_t value, unsigned size)
1414{
1415 StrongARMSSPState *s = opaque;
1416
1417 switch (addr) {
1418 case SSCR0:
1419 s->sscr[0] = value & 0xffbf;
1420 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1421 printf("%s: Wrong data size: %i bits\n", __func__,
1422 (int)SSCR0_DSS(value));
1423 }
1424 if (!(value & SSCR0_SSE)) {
1425 s->sssr = 0;
1426 s->rx_level = 0;
1427 }
1428 strongarm_ssp_fifo_update(s);
1429 break;
1430
1431 case SSCR1:
1432 s->sscr[1] = value & 0x2f;
1433 if (value & SSCR1_LBM) {
1434 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1435 }
1436 strongarm_ssp_fifo_update(s);
1437 break;
1438
1439 case SSSR:
1440 s->sssr &= ~(value & SSSR_RW);
1441 strongarm_ssp_int_update(s);
1442 break;
1443
1444 case SSDR:
1445 if (SSCR0_UWIRE(s->sscr[0])) {
1446 value &= 0xff;
1447 } else
1448
1449 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1450
1451
1452
1453
1454 if (s->sscr[0] & SSCR0_SSE) {
1455 uint32_t readval;
1456 if (s->sscr[1] & SSCR1_LBM) {
1457 readval = value;
1458 } else {
1459 readval = ssi_transfer(s->bus, value);
1460 }
1461
1462 if (s->rx_level < 0x08) {
1463 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1464 } else {
1465 s->sssr |= SSSR_ROR;
1466 }
1467 }
1468 strongarm_ssp_fifo_update(s);
1469 break;
1470
1471 default:
1472 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1473 break;
1474 }
1475}
1476
1477static const MemoryRegionOps strongarm_ssp_ops = {
1478 .read = strongarm_ssp_read,
1479 .write = strongarm_ssp_write,
1480 .endianness = DEVICE_NATIVE_ENDIAN,
1481};
1482
1483static int strongarm_ssp_post_load(void *opaque, int version_id)
1484{
1485 StrongARMSSPState *s = opaque;
1486
1487 strongarm_ssp_fifo_update(s);
1488
1489 return 0;
1490}
1491
1492static int strongarm_ssp_init(SysBusDevice *dev)
1493{
1494 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1495
1496 sysbus_init_irq(dev, &s->irq);
1497
1498 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1499 sysbus_init_mmio(dev, &s->iomem);
1500
1501 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1502 return 0;
1503}
1504
1505static void strongarm_ssp_reset(DeviceState *dev)
1506{
1507 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1508 s->sssr = 0x03;
1509 s->rx_start = 0;
1510 s->rx_level = 0;
1511}
1512
1513static const VMStateDescription vmstate_strongarm_ssp_regs = {
1514 .name = "strongarm-ssp",
1515 .version_id = 0,
1516 .minimum_version_id = 0,
1517 .minimum_version_id_old = 0,
1518 .post_load = strongarm_ssp_post_load,
1519 .fields = (VMStateField[]) {
1520 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1521 VMSTATE_UINT16(sssr, StrongARMSSPState),
1522 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1523 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1524 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1525 VMSTATE_END_OF_LIST(),
1526 },
1527};
1528
1529static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1530{
1531 DeviceClass *dc = DEVICE_CLASS(klass);
1532 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1533
1534 k->init = strongarm_ssp_init;
1535 dc->desc = "StrongARM SSP controller";
1536 dc->reset = strongarm_ssp_reset;
1537 dc->vmsd = &vmstate_strongarm_ssp_regs;
1538}
1539
1540static TypeInfo strongarm_ssp_info = {
1541 .name = "strongarm-ssp",
1542 .parent = TYPE_SYS_BUS_DEVICE,
1543 .instance_size = sizeof(StrongARMSSPState),
1544 .class_init = strongarm_ssp_class_init,
1545};
1546
1547
1548StrongARMState *sa1110_init(MemoryRegion *sysmem,
1549 unsigned int sdram_size, const char *rev)
1550{
1551 StrongARMState *s;
1552 qemu_irq *pic;
1553 int i;
1554
1555 s = g_malloc0(sizeof(StrongARMState));
1556
1557 if (!rev) {
1558 rev = "sa1110-b5";
1559 }
1560
1561 if (strncmp(rev, "sa1110", 6)) {
1562 error_report("Machine requires a SA1110 processor.");
1563 exit(1);
1564 }
1565
1566 s->env = cpu_init(rev);
1567
1568 if (!s->env) {
1569 error_report("Unable to find CPU definition");
1570 exit(1);
1571 }
1572
1573 memory_region_init_ram(&s->sdram, "strongarm.sdram", sdram_size);
1574 vmstate_register_ram_global(&s->sdram);
1575 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1576
1577 pic = arm_pic_init_cpu(s->env);
1578 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1579 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1580
1581 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1582 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1583 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1584 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1585 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1586 NULL);
1587
1588 sysbus_create_simple("strongarm-rtc", 0x90010000,
1589 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1590
1591 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1592
1593 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1594
1595 for (i = 0; sa_serial[i].io_base; i++) {
1596 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1597 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1598 qdev_init_nofail(dev);
1599 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1600 sa_serial[i].io_base);
1601 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1602 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1603 }
1604
1605 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1606 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1607 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1608
1609 return s;
1610}
1611
1612static void strongarm_register_types(void)
1613{
1614 type_register_static(&strongarm_pic_info);
1615 type_register_static(&strongarm_rtc_sysbus_info);
1616 type_register_static(&strongarm_gpio_info);
1617 type_register_static(&strongarm_ppc_info);
1618 type_register_static(&strongarm_uart_info);
1619 type_register_static(&strongarm_ssp_info);
1620}
1621
1622type_init(strongarm_register_types)
1623
