LXR qemu/hw/arm

   1/*
   2 * Status and system control registers for ARM RealView/Versatile boards.
   3 *
   4 * Copyright (c) 2006-2007 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9
  10#include "hw.h"
  11#include "qemu-timer.h"
  12#include "sysbus.h"
  13#include "primecell.h"
  14#include "sysemu.h"
  15
  16#define LOCK_VALUE 0xa05f
  17
  18typedef struct {
  19    SysBusDevice busdev;
  20    MemoryRegion iomem;
  21    qemu_irq pl110_mux_ctrl;
  22
  23    uint32_t sys_id;
  24    uint32_t leds;
  25    uint16_t lockval;
  26    uint32_t cfgdata1;
  27    uint32_t cfgdata2;
  28    uint32_t flags;
  29    uint32_t nvflags;
  30    uint32_t resetlevel;
  31    uint32_t proc_id;
  32    uint32_t sys_mci;
  33    uint32_t sys_cfgdata;
  34    uint32_t sys_cfgctrl;
  35    uint32_t sys_cfgstat;
  36    uint32_t sys_clcd;
  37} arm_sysctl_state;
  38
  39static const VMStateDescription vmstate_arm_sysctl = {
  40    .name = "realview_sysctl",
  41    .version_id = 3,
  42    .minimum_version_id = 1,
  43    .fields = (VMStateField[]) {
  44        VMSTATE_UINT32(leds, arm_sysctl_state),
  45        VMSTATE_UINT16(lockval, arm_sysctl_state),
  46        VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  47        VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  48        VMSTATE_UINT32(flags, arm_sysctl_state),
  49        VMSTATE_UINT32(nvflags, arm_sysctl_state),
  50        VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  51        VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  52        VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  53        VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  54        VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  55        VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
  56        VMSTATE_END_OF_LIST()
  57    }
  58};
  59
  60/* The PB926 actually uses a different format for
  61 * its SYS_ID register. Fortunately the bits which are
  62 * board type on later boards are distinct.
  63 */
  64#define BOARD_ID_PB926 0x100
  65#define BOARD_ID_EB 0x140
  66#define BOARD_ID_PBA8 0x178
  67#define BOARD_ID_PBX 0x182
  68#define BOARD_ID_VEXPRESS 0x190
  69
  70static int board_id(arm_sysctl_state *s)
  71{
  72    /* Extract the board ID field from the SYS_ID register value */
  73    return (s->sys_id >> 16) & 0xfff;
  74}
  75
  76static void arm_sysctl_reset(DeviceState *d)
  77{
  78    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
  79
  80    s->leds = 0;
  81    s->lockval = 0;
  82    s->cfgdata1 = 0;
  83    s->cfgdata2 = 0;
  84    s->flags = 0;
  85    s->resetlevel = 0;
  86    if (board_id(s) == BOARD_ID_VEXPRESS) {
  87        /* On VExpress this register will RAZ/WI */
  88        s->sys_clcd = 0;
  89    } else {
  90        /* All others: CLCDID 0x1f, indicating VGA */
  91        s->sys_clcd = 0x1f00;
  92    }
  93}
  94
  95static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
  96                                unsigned size)
  97{
  98    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
  99
 100    switch (offset) {
 101    case 0x00: /* ID */
 102        return s->sys_id;
 103    case 0x04: /* SW */
 104        /* General purpose hardware switches.
 105           We don't have a useful way of exposing these to the user.  */
 106        return 0;
 107    case 0x08: /* LED */
 108        return s->leds;
 109    case 0x20: /* LOCK */
 110        return s->lockval;
 111    case 0x0c: /* OSC0 */
 112    case 0x10: /* OSC1 */
 113    case 0x14: /* OSC2 */
 114    case 0x18: /* OSC3 */
 115    case 0x1c: /* OSC4 */
 116    case 0x24: /* 100HZ */
 117        /* ??? Implement these.  */
 118        return 0;
 119    case 0x28: /* CFGDATA1 */
 120        return s->cfgdata1;
 121    case 0x2c: /* CFGDATA2 */
 122        return s->cfgdata2;
 123    case 0x30: /* FLAGS */
 124        return s->flags;
 125    case 0x38: /* NVFLAGS */
 126        return s->nvflags;
 127    case 0x40: /* RESETCTL */
 128        if (board_id(s) == BOARD_ID_VEXPRESS) {
 129            /* reserved: RAZ/WI */
 130            return 0;
 131        }
 132        return s->resetlevel;
 133    case 0x44: /* PCICTL */
 134        return 1;
 135    case 0x48: /* MCI */
 136        return s->sys_mci;
 137    case 0x4c: /* FLASH */
 138        return 0;
 139    case 0x50: /* CLCD */
 140        return s->sys_clcd;
 141    case 0x54: /* CLCDSER */
 142        return 0;
 143    case 0x58: /* BOOTCS */
 144        return 0;
 145    case 0x5c: /* 24MHz */
 146        return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
 147    case 0x60: /* MISC */
 148        return 0;
 149    case 0x84: /* PROCID0 */
 150        return s->proc_id;
 151    case 0x88: /* PROCID1 */
 152        return 0xff000000;
 153    case 0x64: /* DMAPSR0 */
 154    case 0x68: /* DMAPSR1 */
 155    case 0x6c: /* DMAPSR2 */
 156    case 0x70: /* IOSEL */
 157    case 0x74: /* PLDCTL */
 158    case 0x80: /* BUSID */
 159    case 0x8c: /* OSCRESET0 */
 160    case 0x90: /* OSCRESET1 */
 161    case 0x94: /* OSCRESET2 */
 162    case 0x98: /* OSCRESET3 */
 163    case 0x9c: /* OSCRESET4 */
 164    case 0xc0: /* SYS_TEST_OSC0 */
 165    case 0xc4: /* SYS_TEST_OSC1 */
 166    case 0xc8: /* SYS_TEST_OSC2 */
 167    case 0xcc: /* SYS_TEST_OSC3 */
 168    case 0xd0: /* SYS_TEST_OSC4 */
 169        return 0;
 170    case 0xa0: /* SYS_CFGDATA */
 171        if (board_id(s) != BOARD_ID_VEXPRESS) {
 172            goto bad_reg;
 173        }
 174        return s->sys_cfgdata;
 175    case 0xa4: /* SYS_CFGCTRL */
 176        if (board_id(s) != BOARD_ID_VEXPRESS) {
 177            goto bad_reg;
 178        }
 179        return s->sys_cfgctrl;
 180    case 0xa8: /* SYS_CFGSTAT */
 181        if (board_id(s) != BOARD_ID_VEXPRESS) {
 182            goto bad_reg;
 183        }
 184        return s->sys_cfgstat;
 185    default:
 186    bad_reg:
 187        printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
 188        return 0;
 189    }
 190}
 191
 192static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
 193                             uint64_t val, unsigned size)
 194{
 195    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 196
 197    switch (offset) {
 198    case 0x08: /* LED */
 199        s->leds = val;
 200    case 0x0c: /* OSC0 */
 201    case 0x10: /* OSC1 */
 202    case 0x14: /* OSC2 */
 203    case 0x18: /* OSC3 */
 204    case 0x1c: /* OSC4 */
 205        /* ??? */
 206        break;
 207    case 0x20: /* LOCK */
 208        if (val == LOCK_VALUE)
 209            s->lockval = val;
 210        else
 211            s->lockval = val & 0x7fff;
 212        break;
 213    case 0x28: /* CFGDATA1 */
 214        /* ??? Need to implement this.  */
 215        s->cfgdata1 = val;
 216        break;
 217    case 0x2c: /* CFGDATA2 */
 218        /* ??? Need to implement this.  */
 219        s->cfgdata2 = val;
 220        break;
 221    case 0x30: /* FLAGSSET */
 222        s->flags |= val;
 223        break;
 224    case 0x34: /* FLAGSCLR */
 225        s->flags &= ~val;
 226        break;
 227    case 0x38: /* NVFLAGSSET */
 228        s->nvflags |= val;
 229        break;
 230    case 0x3c: /* NVFLAGSCLR */
 231        s->nvflags &= ~val;
 232        break;
 233    case 0x40: /* RESETCTL */
 234        switch (board_id(s)) {
 235        case BOARD_ID_PB926:
 236            if (s->lockval == LOCK_VALUE) {
 237                s->resetlevel = val;
 238                if (val & 0x100) {
 239                    qemu_system_reset_request();
 240                }
 241            }
 242            break;
 243        case BOARD_ID_PBX:
 244        case BOARD_ID_PBA8:
 245            if (s->lockval == LOCK_VALUE) {
 246                s->resetlevel = val;
 247                if (val & 0x04) {
 248                    qemu_system_reset_request();
 249                }
 250            }
 251            break;
 252        case BOARD_ID_VEXPRESS:
 253        case BOARD_ID_EB:
 254        default:
 255            /* reserved: RAZ/WI */
 256            break;
 257        }
 258        break;
 259    case 0x44: /* PCICTL */
 260        /* nothing to do.  */
 261        break;
 262    case 0x4c: /* FLASH */
 263        break;
 264    case 0x50: /* CLCD */
 265        switch (board_id(s)) {
 266        case BOARD_ID_PB926:
 267            /* On 926 bits 13:8 are R/O, bits 1:0 control
 268             * the mux that defines how to interpret the PL110
 269             * graphics format, and other bits are r/w but we
 270             * don't implement them to do anything.
 271             */
 272            s->sys_clcd &= 0x3f00;
 273            s->sys_clcd |= val & ~0x3f00;
 274            qemu_set_irq(s->pl110_mux_ctrl, val & 3);
 275            break;
 276        case BOARD_ID_EB:
 277            /* The EB is the same except that there is no mux since
 278             * the EB has a PL111.
 279             */
 280            s->sys_clcd &= 0x3f00;
 281            s->sys_clcd |= val & ~0x3f00;
 282            break;
 283        case BOARD_ID_PBA8:
 284        case BOARD_ID_PBX:
 285            /* On PBA8 and PBX bit 7 is r/w and all other bits
 286             * are either r/o or RAZ/WI.
 287             */
 288            s->sys_clcd &= (1 << 7);
 289            s->sys_clcd |= val & ~(1 << 7);
 290            break;
 291        case BOARD_ID_VEXPRESS:
 292        default:
 293            /* On VExpress this register is unimplemented and will RAZ/WI */
 294            break;
 295        }
 296    case 0x54: /* CLCDSER */
 297    case 0x64: /* DMAPSR0 */
 298    case 0x68: /* DMAPSR1 */
 299    case 0x6c: /* DMAPSR2 */
 300    case 0x70: /* IOSEL */
 301    case 0x74: /* PLDCTL */
 302    case 0x80: /* BUSID */
 303    case 0x84: /* PROCID0 */
 304    case 0x88: /* PROCID1 */
 305    case 0x8c: /* OSCRESET0 */
 306    case 0x90: /* OSCRESET1 */
 307    case 0x94: /* OSCRESET2 */
 308    case 0x98: /* OSCRESET3 */
 309    case 0x9c: /* OSCRESET4 */
 310        break;
 311    case 0xa0: /* SYS_CFGDATA */
 312        if (board_id(s) != BOARD_ID_VEXPRESS) {
 313            goto bad_reg;
 314        }
 315        s->sys_cfgdata = val;
 316        return;
 317    case 0xa4: /* SYS_CFGCTRL */
 318        if (board_id(s) != BOARD_ID_VEXPRESS) {
 319            goto bad_reg;
 320        }
 321        s->sys_cfgctrl = val & ~(3 << 18);
 322        s->sys_cfgstat = 1;            /* complete */
 323        switch (s->sys_cfgctrl) {
 324        case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
 325            qemu_system_shutdown_request();
 326            break;
 327        case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
 328            qemu_system_reset_request();
 329            break;
 330        default:
 331            s->sys_cfgstat |= 2;        /* error */
 332        }
 333        return;
 334    case 0xa8: /* SYS_CFGSTAT */
 335        if (board_id(s) != BOARD_ID_VEXPRESS) {
 336            goto bad_reg;
 337        }
 338        s->sys_cfgstat = val & 3;
 339        return;
 340    default:
 341    bad_reg:
 342        printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
 343        return;
 344    }
 345}
 346
 347static const MemoryRegionOps arm_sysctl_ops = {
 348    .read = arm_sysctl_read,
 349    .write = arm_sysctl_write,
 350    .endianness = DEVICE_NATIVE_ENDIAN,
 351};
 352
 353static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 354{
 355    arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 356    switch (line) {
 357    case ARM_SYSCTL_GPIO_MMC_WPROT:
 358    {
 359        /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 360         * for all later boards it is bit 1.
 361         */
 362        int bit = 2;
 363        if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 364            bit = 4;
 365        }
 366        s->sys_mci &= ~bit;
 367        if (level) {
 368            s->sys_mci |= bit;
 369        }
 370        break;
 371    }
 372    case ARM_SYSCTL_GPIO_MMC_CARDIN:
 373        s->sys_mci &= ~1;
 374        if (level) {
 375            s->sys_mci |= 1;
 376        }
 377        break;
 378    }
 379}
 380
 381static int arm_sysctl_init(SysBusDevice *dev)
 382{
 383    arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 384
 385    memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
 386    sysbus_init_mmio(dev, &s->iomem);
 387    qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
 388    qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
 389    return 0;
 390}
 391
 392static Property arm_sysctl_properties[] = {
 393    DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 394    DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 395    DEFINE_PROP_END_OF_LIST(),
 396};
 397
 398static void arm_sysctl_class_init(ObjectClass *klass, void *data)
 399{
 400    DeviceClass *dc = DEVICE_CLASS(klass);
 401    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 402
 403    k->init = arm_sysctl_init;
 404    dc->reset = arm_sysctl_reset;
 405    dc->vmsd = &vmstate_arm_sysctl;
 406    dc->props = arm_sysctl_properties;
 407}
 408
 409static TypeInfo arm_sysctl_info = {
 410    .name          = "realview_sysctl",
 411    .parent        = TYPE_SYS_BUS_DEVICE,
 412    .instance_size = sizeof(arm_sysctl_state),
 413    .class_init    = arm_sysctl_class_init,
 414};
 415
 416static void arm_sysctl_register_types(void)
 417{
 418    type_register_static(&arm_sysctl_info);
 419}
 420
 421type_init(arm_sysctl_register_types)
 422