LXR qemu/hw/exynos4210.c

   1/*
   2 *  Samsung exynos4210 SoC emulation
   3 *
   4 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5 *    Maksim Kozlov <m.kozlov@samsung.com>
   6 *    Evgeny Voevodin <e.voevodin@samsung.com>
   7 *    Igor Mitsyanko  <i.mitsyanko@samsung.com>
   8 *
   9 *  This program is free software; you can redistribute it and/or modify it
  10 *  under the terms of the GNU General Public License as published by the
  11 *  Free Software Foundation; either version 2 of the License, or
  12 *  (at your option) any later version.
  13 *
  14 *  This program is distributed in the hope that it will be useful, but WITHOUT
  15 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  17 *  for more details.
  18 *
  19 *  You should have received a copy of the GNU General Public License along
  20 *  with this program; if not, see <http://www.gnu.org/licenses/>.
  21 *
  22 */
  23
  24#include "boards.h"
  25#include "sysemu.h"
  26#include "sysbus.h"
  27#include "arm-misc.h"
  28#include "loader.h"
  29#include "exynos4210.h"
  30
  31#define EXYNOS4210_CHIPID_ADDR         0x10000000
  32
  33/* PWM */
  34#define EXYNOS4210_PWM_BASE_ADDR       0x139D0000
  35
  36/* RTC */
  37#define EXYNOS4210_RTC_BASE_ADDR       0x10070000
  38
  39/* MCT */
  40#define EXYNOS4210_MCT_BASE_ADDR       0x10050000
  41
  42/* I2C */
  43#define EXYNOS4210_I2C_SHIFT           0x00010000
  44#define EXYNOS4210_I2C_BASE_ADDR       0x13860000
  45/* Interrupt Group of External Interrupt Combiner for I2C */
  46#define EXYNOS4210_I2C_INTG            27
  47#define EXYNOS4210_HDMI_INTG           16
  48
  49/* UART's definitions */
  50#define EXYNOS4210_UART0_BASE_ADDR     0x13800000
  51#define EXYNOS4210_UART1_BASE_ADDR     0x13810000
  52#define EXYNOS4210_UART2_BASE_ADDR     0x13820000
  53#define EXYNOS4210_UART3_BASE_ADDR     0x13830000
  54#define EXYNOS4210_UART0_FIFO_SIZE     256
  55#define EXYNOS4210_UART1_FIFO_SIZE     64
  56#define EXYNOS4210_UART2_FIFO_SIZE     16
  57#define EXYNOS4210_UART3_FIFO_SIZE     16
  58/* Interrupt Group of External Interrupt Combiner for UART */
  59#define EXYNOS4210_UART_INT_GRP        26
  60
  61/* External GIC */
  62#define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR    0x10480000
  63#define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR   0x10490000
  64
  65/* Combiner */
  66#define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
  67#define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
  68
  69/* PMU SFR base address */
  70#define EXYNOS4210_PMU_BASE_ADDR            0x10020000
  71
  72/* Display controllers (FIMD) */
  73#define EXYNOS4210_FIMD0_BASE_ADDR          0x11C00000
  74
  75static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
  76                                    0x09, 0x00, 0x00, 0x00 };
  77
  78void exynos4210_write_secondary(ARMCPU *cpu,
  79        const struct arm_boot_info *info)
  80{
  81    int n;
  82    uint32_t smpboot[] = {
  83        0xe59f3024, /* ldr r3, External gic_cpu_if */
  84        0xe59f2024, /* ldr r2, Internal gic_cpu_if */
  85        0xe59f0024, /* ldr r0, startaddr */
  86        0xe3a01001, /* mov r1, #1 */
  87        0xe5821000, /* str r1, [r2] */
  88        0xe5831000, /* str r1, [r3] */
  89        0xe320f003, /* wfi */
  90        0xe5901000, /* ldr     r1, [r0] */
  91        0xe1110001, /* tst     r1, r1 */
  92        0x0afffffb, /* beq     <wfi> */
  93        0xe12fff11, /* bx      r1 */
  94        EXYNOS4210_EXT_GIC_CPU_BASE_ADDR,
  95        0,          /* gic_cpu_if: base address of Internal GIC CPU interface */
  96        0           /* bootreg: Boot register address is held here */
  97    };
  98    smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
  99    smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr;
 100    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
 101        smpboot[n] = tswap32(smpboot[n]);
 102    }
 103    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 104                       info->smp_loader_start);
 105}
 106
 107Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
 108        unsigned long ram_size)
 109{
 110    qemu_irq cpu_irq[EXYNOS4210_NCPUS];
 111    int i, n;
 112    Exynos4210State *s = g_new(Exynos4210State, 1);
 113    qemu_irq *irqp;
 114    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
 115    unsigned long mem_size;
 116    DeviceState *dev;
 117    SysBusDevice *busdev;
 118
 119    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 120        s->cpu[n] = cpu_arm_init("cortex-a9");
 121        if (!s->cpu[n]) {
 122            fprintf(stderr, "Unable to find CPU %d definition\n", n);
 123            exit(1);
 124        }
 125
 126        /* Create PIC controller for each processor instance */
 127        irqp = arm_pic_init_cpu(s->cpu[n]);
 128
 129        /*
 130         * Get GICs gpio_in cpu_irq to connect a combiner to them later.
 131         * Use only IRQ for a while.
 132         */
 133        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 134    }
 135
 136    /*** IRQs ***/
 137
 138    s->irq_table = exynos4210_init_irq(&s->irqs);
 139
 140    /* IRQ Gate */
 141    for (i = 0; i < EXYNOS4210_NCPUS; i++) {
 142        dev = qdev_create(NULL, "exynos4210.irq_gate");
 143        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
 144        qdev_init_nofail(dev);
 145        /* Get IRQ Gate input in gate_irq */
 146        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
 147            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
 148        }
 149        busdev = sysbus_from_qdev(dev);
 150
 151        /* Connect IRQ Gate output to cpu_irq */
 152        sysbus_connect_irq(busdev, 0, cpu_irq[i]);
 153    }
 154
 155    /* Private memory region and Internal GIC */
 156    dev = qdev_create(NULL, "a9mpcore_priv");
 157    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 158    qdev_init_nofail(dev);
 159    busdev = sysbus_from_qdev(dev);
 160    sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
 161    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 162        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
 163    }
 164    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 165        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 166    }
 167
 168    /* Cache controller */
 169    sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 170
 171    /* External GIC */
 172    dev = qdev_create(NULL, "exynos4210.gic");
 173    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 174    qdev_init_nofail(dev);
 175    busdev = sysbus_from_qdev(dev);
 176    /* Map CPU interface */
 177    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
 178    /* Map Distributer interface */
 179    sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
 180    for (n = 0; n < EXYNOS4210_NCPUS; n++) {
 181        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
 182    }
 183    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
 184        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
 185    }
 186
 187    /* Internal Interrupt Combiner */
 188    dev = qdev_create(NULL, "exynos4210.combiner");
 189    qdev_init_nofail(dev);
 190    busdev = sysbus_from_qdev(dev);
 191    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 192        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
 193    }
 194    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
 195    sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 196
 197    /* External Interrupt Combiner */
 198    dev = qdev_create(NULL, "exynos4210.combiner");
 199    qdev_prop_set_uint32(dev, "external", 1);
 200    qdev_init_nofail(dev);
 201    busdev = sysbus_from_qdev(dev);
 202    for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
 203        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
 204    }
 205    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
 206    sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 207
 208    /* Initialize board IRQs. */
 209    exynos4210_init_board_irqs(&s->irqs);
 210
 211    /*** Memory ***/
 212
 213    /* Chip-ID and OMR */
 214    memory_region_init_ram_ptr(&s->chipid_mem, "exynos4210.chipid",
 215            sizeof(chipid_and_omr), chipid_and_omr);
 216    memory_region_set_readonly(&s->chipid_mem, true);
 217    memory_region_add_subregion(system_mem, EXYNOS4210_CHIPID_ADDR,
 218                                &s->chipid_mem);
 219
 220    /* Internal ROM */
 221    memory_region_init_ram(&s->irom_mem, "exynos4210.irom",
 222                           EXYNOS4210_IROM_SIZE);
 223    memory_region_set_readonly(&s->irom_mem, true);
 224    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR,
 225                                &s->irom_mem);
 226    /* mirror of iROM */
 227    memory_region_init_alias(&s->irom_alias_mem, "exynos4210.irom_alias",
 228                             &s->irom_mem,
 229                             0,
 230                             EXYNOS4210_IROM_SIZE);
 231    memory_region_set_readonly(&s->irom_alias_mem, true);
 232    memory_region_add_subregion(system_mem, EXYNOS4210_IROM_MIRROR_BASE_ADDR,
 233                                &s->irom_alias_mem);
 234
 235    /* Internal RAM */
 236    memory_region_init_ram(&s->iram_mem, "exynos4210.iram",
 237                           EXYNOS4210_IRAM_SIZE);
 238    vmstate_register_ram_global(&s->iram_mem);
 239    memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR,
 240                                &s->iram_mem);
 241
 242    /* DRAM */
 243    mem_size = ram_size;
 244    if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) {
 245        memory_region_init_ram(&s->dram1_mem, "exynos4210.dram1",
 246                mem_size - EXYNOS4210_DRAM_MAX_SIZE);
 247        vmstate_register_ram_global(&s->dram1_mem);
 248        memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR,
 249                &s->dram1_mem);
 250        mem_size = EXYNOS4210_DRAM_MAX_SIZE;
 251    }
 252    memory_region_init_ram(&s->dram0_mem, "exynos4210.dram0", mem_size);
 253    vmstate_register_ram_global(&s->dram0_mem);
 254    memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
 255            &s->dram0_mem);
 256
 257   /* PMU.
 258    * The only reason of existence at the moment is that secondary CPU boot
 259    * loader uses PMU INFORM5 register as a holding pen.
 260    */
 261    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
 262
 263    /* PWM */
 264    sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
 265                          s->irq_table[exynos4210_get_irq(22, 0)],
 266                          s->irq_table[exynos4210_get_irq(22, 1)],
 267                          s->irq_table[exynos4210_get_irq(22, 2)],
 268                          s->irq_table[exynos4210_get_irq(22, 3)],
 269                          s->irq_table[exynos4210_get_irq(22, 4)],
 270                          NULL);
 271    /* RTC */
 272    sysbus_create_varargs("exynos4210.rtc", EXYNOS4210_RTC_BASE_ADDR,
 273                          s->irq_table[exynos4210_get_irq(23, 0)],
 274                          s->irq_table[exynos4210_get_irq(23, 1)],
 275                          NULL);
 276
 277    /* Multi Core Timer */
 278    dev = qdev_create(NULL, "exynos4210.mct");
 279    qdev_init_nofail(dev);
 280    busdev = sysbus_from_qdev(dev);
 281    for (n = 0; n < 4; n++) {
 282        /* Connect global timer interrupts to Combiner gpio_in */
 283        sysbus_connect_irq(busdev, n,
 284                s->irq_table[exynos4210_get_irq(1, 4 + n)]);
 285    }
 286    /* Connect local timer interrupts to Combiner gpio_in */
 287    sysbus_connect_irq(busdev, 4,
 288            s->irq_table[exynos4210_get_irq(51, 0)]);
 289    sysbus_connect_irq(busdev, 5,
 290            s->irq_table[exynos4210_get_irq(35, 3)]);
 291    sysbus_mmio_map(busdev, 0, EXYNOS4210_MCT_BASE_ADDR);
 292
 293    /*** I2C ***/
 294    for (n = 0; n < EXYNOS4210_I2C_NUMBER; n++) {
 295        uint32_t addr = EXYNOS4210_I2C_BASE_ADDR + EXYNOS4210_I2C_SHIFT * n;
 296        qemu_irq i2c_irq;
 297
 298        if (n < 8) {
 299            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_I2C_INTG, n)];
 300        } else {
 301            i2c_irq = s->irq_table[exynos4210_get_irq(EXYNOS4210_HDMI_INTG, 1)];
 302        }
 303
 304        dev = qdev_create(NULL, "exynos4210.i2c");
 305        qdev_init_nofail(dev);
 306        busdev = sysbus_from_qdev(dev);
 307        sysbus_connect_irq(busdev, 0, i2c_irq);
 308        sysbus_mmio_map(busdev, 0, addr);
 309        s->i2c_if[n] = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
 310    }
 311
 312
 313    /*** UARTs ***/
 314    exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
 315                           EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
 316                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
 317
 318    exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
 319                           EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
 320                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
 321
 322    exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
 323                           EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
 324                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
 325
 326    exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
 327                           EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
 328                  s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
 329
 330    /*** Display controller (FIMD) ***/
 331    sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR,
 332            s->irq_table[exynos4210_get_irq(11, 0)],
 333            s->irq_table[exynos4210_get_irq(11, 1)],
 334            s->irq_table[exynos4210_get_irq(11, 2)],
 335            NULL);
 336
 337    return s;
 338}
 339