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25#include "hw.h"
26#include "pc.h"
27#include "pci.h"
28#include "pci_host.h"
29#include "isa.h"
30#include "sysbus.h"
31#include "range.h"
32#include "xen.h"
33
34
35
36
37
38
39typedef struct I440FXState {
40 PCIHostState parent_obj;
41} I440FXState;
42
43#define PIIX_NUM_PIC_IRQS 16
44#define PIIX_NUM_PIRQS 4ULL
45#define XEN_PIIX_NUM_PIRQS 128ULL
46#define PIIX_PIRQC 0x60
47
48typedef struct PIIX3State {
49 PCIDevice dev;
50
51
52
53
54
55
56
57
58
59
60#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
61#error "unable to encode pic state in 64bit in pic_levels."
62#endif
63 uint64_t pic_levels;
64
65 qemu_irq *pic;
66
67
68 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
69} PIIX3State;
70
71typedef struct PAMMemoryRegion {
72 MemoryRegion mem;
73 bool initialized;
74} PAMMemoryRegion;
75
76struct PCII440FXState {
77 PCIDevice dev;
78 MemoryRegion *system_memory;
79 MemoryRegion *pci_address_space;
80 MemoryRegion *ram_memory;
81 MemoryRegion pci_hole;
82 MemoryRegion pci_hole_64bit;
83 PAMMemoryRegion pam_regions[13];
84 MemoryRegion smram_region;
85 uint8_t smm_enabled;
86};
87
88
89#define I440FX_PAM 0x59
90#define I440FX_PAM_SIZE 7
91#define I440FX_SMRAM 0x72
92
93static void piix3_set_irq(void *opaque, int pirq, int level);
94static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
95static void piix3_write_config_xen(PCIDevice *dev,
96 uint32_t address, uint32_t val, int len);
97
98
99
100
101static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
102{
103 int slot_addend;
104 slot_addend = (pci_dev->devfn >> 3) - 1;
105 return (pci_intx + slot_addend) & 3;
106}
107
108static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
109 PAMMemoryRegion *mem)
110{
111 if (mem->initialized) {
112 memory_region_del_subregion(d->system_memory, &mem->mem);
113 memory_region_destroy(&mem->mem);
114 }
115
116
117 switch(r) {
118 case 3:
119
120 memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
121 start, end - start);
122 break;
123 case 1:
124
125 memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
126 start, end - start);
127 memory_region_set_readonly(&mem->mem, true);
128 break;
129 case 2:
130 case 0:
131
132 memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
133 start, end - start);
134 break;
135 }
136 memory_region_add_subregion_overlap(d->system_memory,
137 start, &mem->mem, 1);
138 mem->initialized = true;
139}
140
141static void i440fx_update_memory_mappings(PCII440FXState *d)
142{
143 int i, r;
144 uint32_t smram;
145 bool smram_enabled;
146
147 memory_region_transaction_begin();
148 update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
149 &d->pam_regions[0]);
150 for(i = 0; i < 12; i++) {
151 r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
152 update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
153 &d->pam_regions[i+1]);
154 }
155 smram = d->dev.config[I440FX_SMRAM];
156 smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
157 memory_region_set_enabled(&d->smram_region, !smram_enabled);
158 memory_region_transaction_commit();
159}
160
161static void i440fx_set_smm(int val, void *arg)
162{
163 PCII440FXState *d = arg;
164
165 val = (val != 0);
166 if (d->smm_enabled != val) {
167 d->smm_enabled = val;
168 i440fx_update_memory_mappings(d);
169 }
170}
171
172
173static void i440fx_write_config(PCIDevice *dev,
174 uint32_t address, uint32_t val, int len)
175{
176 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
177
178
179 pci_default_write_config(dev, address, val, len);
180 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
181 range_covers_byte(address, len, I440FX_SMRAM)) {
182 i440fx_update_memory_mappings(d);
183 }
184}
185
186static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
187{
188 PCII440FXState *d = opaque;
189 int ret, i;
190
191 ret = pci_device_load(&d->dev, f);
192 if (ret < 0)
193 return ret;
194 i440fx_update_memory_mappings(d);
195 qemu_get_8s(f, &d->smm_enabled);
196
197 if (version_id == 2) {
198 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
199 qemu_get_be32(f);
200 }
201 }
202
203 return 0;
204}
205
206static int i440fx_post_load(void *opaque, int version_id)
207{
208 PCII440FXState *d = opaque;
209
210 i440fx_update_memory_mappings(d);
211 return 0;
212}
213
214static const VMStateDescription vmstate_i440fx = {
215 .name = "I440FX",
216 .version_id = 3,
217 .minimum_version_id = 3,
218 .minimum_version_id_old = 1,
219 .load_state_old = i440fx_load_old,
220 .post_load = i440fx_post_load,
221 .fields = (VMStateField []) {
222 VMSTATE_PCI_DEVICE(dev, PCII440FXState),
223 VMSTATE_UINT8(smm_enabled, PCII440FXState),
224 VMSTATE_END_OF_LIST()
225 }
226};
227
228static int i440fx_pcihost_initfn(SysBusDevice *dev)
229{
230 PCIHostState *s = PCI_HOST_BRIDGE(dev);
231
232 memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
233 "pci-conf-idx", 4);
234 sysbus_add_io(dev, 0xcf8, &s->conf_mem);
235 sysbus_init_ioports(&s->busdev, 0xcf8, 4);
236
237 memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
238 "pci-conf-data", 4);
239 sysbus_add_io(dev, 0xcfc, &s->data_mem);
240 sysbus_init_ioports(&s->busdev, 0xcfc, 4);
241
242 return 0;
243}
244
245static int i440fx_initfn(PCIDevice *dev)
246{
247 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
248
249 d->dev.config[I440FX_SMRAM] = 0x02;
250
251 cpu_smm_register(&i440fx_set_smm, d);
252 return 0;
253}
254
255static PCIBus *i440fx_common_init(const char *device_name,
256 PCII440FXState **pi440fx_state,
257 int *piix3_devfn,
258 ISABus **isa_bus, qemu_irq *pic,
259 MemoryRegion *address_space_mem,
260 MemoryRegion *address_space_io,
261 ram_addr_t ram_size,
262 target_phys_addr_t pci_hole_start,
263 target_phys_addr_t pci_hole_size,
264 target_phys_addr_t pci_hole64_start,
265 target_phys_addr_t pci_hole64_size,
266 MemoryRegion *pci_address_space,
267 MemoryRegion *ram_memory)
268{
269 DeviceState *dev;
270 PCIBus *b;
271 PCIDevice *d;
272 PCIHostState *s;
273 PIIX3State *piix3;
274 PCII440FXState *f;
275
276 dev = qdev_create(NULL, "i440FX-pcihost");
277 s = PCI_HOST_BRIDGE(dev);
278 s->address_space = address_space_mem;
279 b = pci_bus_new(dev, NULL, pci_address_space,
280 address_space_io, 0);
281 s->bus = b;
282 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
283 qdev_init_nofail(dev);
284
285 d = pci_create_simple(b, 0, device_name);
286 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
287 f = *pi440fx_state;
288 f->system_memory = address_space_mem;
289 f->pci_address_space = pci_address_space;
290 f->ram_memory = ram_memory;
291 memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
292 pci_hole_start, pci_hole_size);
293 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
294 memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
295 f->pci_address_space,
296 pci_hole64_start, pci_hole64_size);
297 if (pci_hole64_size) {
298 memory_region_add_subregion(f->system_memory, pci_hole64_start,
299 &f->pci_hole_64bit);
300 }
301 memory_region_init_alias(&f->smram_region, "smram-region",
302 f->pci_address_space, 0xa0000, 0x20000);
303 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
304 &f->smram_region, 1);
305 memory_region_set_enabled(&f->smram_region, false);
306
307
308
309
310
311 if (xen_enabled()) {
312 piix3 = DO_UPCAST(PIIX3State, dev,
313 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
314 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
315 piix3, XEN_PIIX_NUM_PIRQS);
316 } else {
317 piix3 = DO_UPCAST(PIIX3State, dev,
318 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
319 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
320 PIIX_NUM_PIRQS);
321 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
322 }
323 piix3->pic = pic;
324 *isa_bus = DO_UPCAST(ISABus, qbus,
325 qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
326
327 *piix3_devfn = piix3->dev.devfn;
328
329 ram_size = ram_size / 8 / 1024 / 1024;
330 if (ram_size > 255)
331 ram_size = 255;
332 (*pi440fx_state)->dev.config[0x57]=ram_size;
333
334 i440fx_update_memory_mappings(f);
335
336 return b;
337}
338
339PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
340 ISABus **isa_bus, qemu_irq *pic,
341 MemoryRegion *address_space_mem,
342 MemoryRegion *address_space_io,
343 ram_addr_t ram_size,
344 target_phys_addr_t pci_hole_start,
345 target_phys_addr_t pci_hole_size,
346 target_phys_addr_t pci_hole64_start,
347 target_phys_addr_t pci_hole64_size,
348 MemoryRegion *pci_memory, MemoryRegion *ram_memory)
349
350{
351 PCIBus *b;
352
353 b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
354 address_space_mem, address_space_io, ram_size,
355 pci_hole_start, pci_hole_size,
356 pci_hole64_start, pci_hole64_size,
357 pci_memory, ram_memory);
358 return b;
359}
360
361
362static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
363{
364 qemu_set_irq(piix3->pic[pic_irq],
365 !!(piix3->pic_levels &
366 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
367 (pic_irq * PIIX_NUM_PIRQS))));
368}
369
370static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
371{
372 int pic_irq;
373 uint64_t mask;
374
375 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
376 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
377 return;
378 }
379
380 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
381 piix3->pic_levels &= ~mask;
382 piix3->pic_levels |= mask * !!level;
383
384 piix3_set_irq_pic(piix3, pic_irq);
385}
386
387static void piix3_set_irq(void *opaque, int pirq, int level)
388{
389 PIIX3State *piix3 = opaque;
390 piix3_set_irq_level(piix3, pirq, level);
391}
392
393static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
394{
395 PIIX3State *piix3 = opaque;
396 int irq = piix3->dev.config[PIIX_PIRQC + pin];
397 PCIINTxRoute route;
398
399 if (irq < PIIX_NUM_PIC_IRQS) {
400 route.mode = PCI_INTX_ENABLED;
401 route.irq = irq;
402 } else {
403 route.mode = PCI_INTX_DISABLED;
404 route.irq = -1;
405 }
406 return route;
407}
408
409
410static void piix3_update_irq_levels(PIIX3State *piix3)
411{
412 int pirq;
413
414 piix3->pic_levels = 0;
415 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
416 piix3_set_irq_level(piix3, pirq,
417 pci_bus_get_irq_level(piix3->dev.bus, pirq));
418 }
419}
420
421static void piix3_write_config(PCIDevice *dev,
422 uint32_t address, uint32_t val, int len)
423{
424 pci_default_write_config(dev, address, val, len);
425 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
426 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
427 int pic_irq;
428
429 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
430 piix3_update_irq_levels(piix3);
431 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
432 piix3_set_irq_pic(piix3, pic_irq);
433 }
434 }
435}
436
437static void piix3_write_config_xen(PCIDevice *dev,
438 uint32_t address, uint32_t val, int len)
439{
440 xen_piix_pci_write_config_client(address, val, len);
441 piix3_write_config(dev, address, val, len);
442}
443
444static void piix3_reset(void *opaque)
445{
446 PIIX3State *d = opaque;
447 uint8_t *pci_conf = d->dev.config;
448
449 pci_conf[0x04] = 0x07;
450 pci_conf[0x05] = 0x00;
451 pci_conf[0x06] = 0x00;
452 pci_conf[0x07] = 0x02;
453 pci_conf[0x4c] = 0x4d;
454 pci_conf[0x4e] = 0x03;
455 pci_conf[0x4f] = 0x00;
456 pci_conf[0x60] = 0x80;
457 pci_conf[0x61] = 0x80;
458 pci_conf[0x62] = 0x80;
459 pci_conf[0x63] = 0x80;
460 pci_conf[0x69] = 0x02;
461 pci_conf[0x70] = 0x80;
462 pci_conf[0x76] = 0x0c;
463 pci_conf[0x77] = 0x0c;
464 pci_conf[0x78] = 0x02;
465 pci_conf[0x79] = 0x00;
466 pci_conf[0x80] = 0x00;
467 pci_conf[0x82] = 0x00;
468 pci_conf[0xa0] = 0x08;
469 pci_conf[0xa2] = 0x00;
470 pci_conf[0xa3] = 0x00;
471 pci_conf[0xa4] = 0x00;
472 pci_conf[0xa5] = 0x00;
473 pci_conf[0xa6] = 0x00;
474 pci_conf[0xa7] = 0x00;
475 pci_conf[0xa8] = 0x0f;
476 pci_conf[0xaa] = 0x00;
477 pci_conf[0xab] = 0x00;
478 pci_conf[0xac] = 0x00;
479 pci_conf[0xae] = 0x00;
480
481 d->pic_levels = 0;
482}
483
484static int piix3_post_load(void *opaque, int version_id)
485{
486 PIIX3State *piix3 = opaque;
487 piix3_update_irq_levels(piix3);
488 return 0;
489}
490
491static void piix3_pre_save(void *opaque)
492{
493 int i;
494 PIIX3State *piix3 = opaque;
495
496 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
497 piix3->pci_irq_levels_vmstate[i] =
498 pci_bus_get_irq_level(piix3->dev.bus, i);
499 }
500}
501
502static const VMStateDescription vmstate_piix3 = {
503 .name = "PIIX3",
504 .version_id = 3,
505 .minimum_version_id = 2,
506 .minimum_version_id_old = 2,
507 .post_load = piix3_post_load,
508 .pre_save = piix3_pre_save,
509 .fields = (VMStateField []) {
510 VMSTATE_PCI_DEVICE(dev, PIIX3State),
511 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
512 PIIX_NUM_PIRQS, 3),
513 VMSTATE_END_OF_LIST()
514 }
515};
516
517static int piix3_initfn(PCIDevice *dev)
518{
519 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
520
521 isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
522 qemu_register_reset(piix3_reset, d);
523 return 0;
524}
525
526static void piix3_class_init(ObjectClass *klass, void *data)
527{
528 DeviceClass *dc = DEVICE_CLASS(klass);
529 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
530
531 dc->desc = "ISA bridge";
532 dc->vmsd = &vmstate_piix3;
533 dc->no_user = 1,
534 k->no_hotplug = 1;
535 k->init = piix3_initfn;
536 k->config_write = piix3_write_config;
537 k->vendor_id = PCI_VENDOR_ID_INTEL;
538 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
539 k->class_id = PCI_CLASS_BRIDGE_ISA;
540}
541
542static const TypeInfo piix3_info = {
543 .name = "PIIX3",
544 .parent = TYPE_PCI_DEVICE,
545 .instance_size = sizeof(PIIX3State),
546 .class_init = piix3_class_init,
547};
548
549static void piix3_xen_class_init(ObjectClass *klass, void *data)
550{
551 DeviceClass *dc = DEVICE_CLASS(klass);
552 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
553
554 dc->desc = "ISA bridge";
555 dc->vmsd = &vmstate_piix3;
556 dc->no_user = 1;
557 k->no_hotplug = 1;
558 k->init = piix3_initfn;
559 k->config_write = piix3_write_config_xen;
560 k->vendor_id = PCI_VENDOR_ID_INTEL;
561 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
562 k->class_id = PCI_CLASS_BRIDGE_ISA;
563};
564
565static const TypeInfo piix3_xen_info = {
566 .name = "PIIX3-xen",
567 .parent = TYPE_PCI_DEVICE,
568 .instance_size = sizeof(PIIX3State),
569 .class_init = piix3_xen_class_init,
570};
571
572static void i440fx_class_init(ObjectClass *klass, void *data)
573{
574 DeviceClass *dc = DEVICE_CLASS(klass);
575 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
576
577 k->no_hotplug = 1;
578 k->init = i440fx_initfn;
579 k->config_write = i440fx_write_config;
580 k->vendor_id = PCI_VENDOR_ID_INTEL;
581 k->device_id = PCI_DEVICE_ID_INTEL_82441;
582 k->revision = 0x02;
583 k->class_id = PCI_CLASS_BRIDGE_HOST;
584 dc->desc = "Host bridge";
585 dc->no_user = 1;
586 dc->vmsd = &vmstate_i440fx;
587}
588
589static const TypeInfo i440fx_info = {
590 .name = "i440FX",
591 .parent = TYPE_PCI_DEVICE,
592 .instance_size = sizeof(PCII440FXState),
593 .class_init = i440fx_class_init,
594};
595
596static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
597{
598 DeviceClass *dc = DEVICE_CLASS(klass);
599 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
600
601 k->init = i440fx_pcihost_initfn;
602 dc->fw_name = "pci";
603 dc->no_user = 1;
604}
605
606static const TypeInfo i440fx_pcihost_info = {
607 .name = "i440FX-pcihost",
608 .parent = TYPE_PCI_HOST_BRIDGE,
609 .instance_size = sizeof(I440FXState),
610 .class_init = i440fx_pcihost_class_init,
611};
612
613static void i440fx_register_types(void)
614{
615 type_register_static(&i440fx_info);
616 type_register_static(&piix3_info);
617 type_register_static(&piix3_xen_info);
618 type_register_static(&i440fx_pcihost_info);
619}
620
621type_init(i440fx_register_types)
622
