1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include "sysbus.h"
25#include "qemu-timer.h"
26#include "sun4m.h"
27#include "nvram.h"
28#include "sparc32_dma.h"
29#include "fdc.h"
30#include "sysemu.h"
31#include "net.h"
32#include "boards.h"
33#include "firmware_abi.h"
34#include "esp.h"
35#include "pc.h"
36#include "isa.h"
37#include "fw_cfg.h"
38#include "escc.h"
39#include "empty_slot.h"
40#include "qdev-addr.h"
41#include "loader.h"
42#include "elf.h"
43#include "blockdev.h"
44#include "trace.h"
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74#define KERNEL_LOAD_ADDR 0x00004000
75#define CMDLINE_ADDR 0x007ff000
76#define INITRD_LOAD_ADDR 0x00800000
77#define PROM_SIZE_MAX (1024 * 1024)
78#define PROM_VADDR 0xffd00000
79#define PROM_FILENAME "openbios-sparc32"
80#define CFG_ADDR 0xd00000510ULL
81#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83#define MAX_CPUS 16
84#define MAX_PILS 16
85#define MAX_VSIMMS 4
86
87#define ESCC_CLOCK 4915200
88
89struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106};
107
108#define MAX_IOUNITS 5
109
110struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123};
124
125struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136};
137
138int DMA_get_channel_mode (int nchan)
139{
140 return 0;
141}
142int DMA_read_memory (int nchan, void *buf, int pos, int size)
143{
144 return 0;
145}
146int DMA_write_memory (int nchan, void *buf, int pos, int size)
147{
148 return 0;
149}
150void DMA_hold_DREQ (int nchan) {}
151void DMA_release_DREQ (int nchan) {}
152void DMA_schedule(int nchan) {}
153
154void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155{
156}
157
158void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161{
162}
163
164static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165{
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168}
169
170static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175{
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185
186
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215}
216
217static DeviceState *slavio_intctl;
218
219void sun4m_pic_info(Monitor *mon)
220{
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223}
224
225void sun4m_irq_info(Monitor *mon)
226{
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229}
230
231void cpu_check_irqs(CPUSPARCState *env)
232{
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254}
255
256static void cpu_kick_irq(CPUSPARCState *env)
257{
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261}
262
263static void cpu_set_irq(void *opaque, int irq, int level)
264{
265 CPUSPARCState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276}
277
278static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279{
280}
281
282static void main_cpu_reset(void *opaque)
283{
284 SPARCCPU *cpu = opaque;
285 CPUSPARCState *env = &cpu->env;
286
287 cpu_reset(CPU(cpu));
288 env->halted = 0;
289}
290
291static void secondary_cpu_reset(void *opaque)
292{
293 SPARCCPU *cpu = opaque;
294 CPUSPARCState *env = &cpu->env;
295
296 cpu_reset(CPU(cpu));
297 env->halted = 1;
298}
299
300static void cpu_halt_signal(void *opaque, int irq, int level)
301{
302 if (level && cpu_single_env)
303 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
304}
305
306static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
307{
308 return addr - 0xf0000000ULL;
309}
310
311static unsigned long sun4m_load_kernel(const char *kernel_filename,
312 const char *initrd_filename,
313 ram_addr_t RAM_size)
314{
315 int linux_boot;
316 unsigned int i;
317 long initrd_size, kernel_size;
318 uint8_t *ptr;
319
320 linux_boot = (kernel_filename != NULL);
321
322 kernel_size = 0;
323 if (linux_boot) {
324 int bswap_needed;
325
326#ifdef BSWAP_NEEDED
327 bswap_needed = 1;
328#else
329 bswap_needed = 0;
330#endif
331 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
332 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
333 if (kernel_size < 0)
334 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
336 TARGET_PAGE_SIZE);
337 if (kernel_size < 0)
338 kernel_size = load_image_targphys(kernel_filename,
339 KERNEL_LOAD_ADDR,
340 RAM_size - KERNEL_LOAD_ADDR);
341 if (kernel_size < 0) {
342 fprintf(stderr, "qemu: could not load kernel '%s'\n",
343 kernel_filename);
344 exit(1);
345 }
346
347
348 initrd_size = 0;
349 if (initrd_filename) {
350 initrd_size = load_image_targphys(initrd_filename,
351 INITRD_LOAD_ADDR,
352 RAM_size - INITRD_LOAD_ADDR);
353 if (initrd_size < 0) {
354 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
355 initrd_filename);
356 exit(1);
357 }
358 }
359 if (initrd_size > 0) {
360 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
361 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
362 if (ldl_p(ptr) == 0x48647253) {
363 stl_p(ptr + 16, INITRD_LOAD_ADDR);
364 stl_p(ptr + 20, initrd_size);
365 break;
366 }
367 }
368 }
369 }
370 return kernel_size;
371}
372
373static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
374{
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "iommu");
379 qdev_prop_set_uint32(dev, "version", version);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, irq);
383 sysbus_mmio_map(s, 0, addr);
384
385 return s;
386}
387
388static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
389 void *iommu, qemu_irq *dev_irq, int is_ledma)
390{
391 DeviceState *dev;
392 SysBusDevice *s;
393
394 dev = qdev_create(NULL, "sparc32_dma");
395 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
396 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
397 qdev_init_nofail(dev);
398 s = sysbus_from_qdev(dev);
399 sysbus_connect_irq(s, 0, parent_irq);
400 *dev_irq = qdev_get_gpio_in(dev, 0);
401 sysbus_mmio_map(s, 0, daddr);
402
403 return s;
404}
405
406static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
407 void *dma_opaque, qemu_irq irq)
408{
409 DeviceState *dev;
410 SysBusDevice *s;
411 qemu_irq reset;
412
413 qemu_check_nic_model(&nd_table[0], "lance");
414
415 dev = qdev_create(NULL, "lance");
416 qdev_set_nic_properties(dev, nd);
417 qdev_prop_set_ptr(dev, "dma", dma_opaque);
418 qdev_init_nofail(dev);
419 s = sysbus_from_qdev(dev);
420 sysbus_mmio_map(s, 0, leaddr);
421 sysbus_connect_irq(s, 0, irq);
422 reset = qdev_get_gpio_in(dev, 0);
423 qdev_connect_gpio_out(dma_opaque, 0, reset);
424}
425
426static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
427 target_phys_addr_t addrg,
428 qemu_irq **parent_irq)
429{
430 DeviceState *dev;
431 SysBusDevice *s;
432 unsigned int i, j;
433
434 dev = qdev_create(NULL, "slavio_intctl");
435 qdev_init_nofail(dev);
436
437 s = sysbus_from_qdev(dev);
438
439 for (i = 0; i < MAX_CPUS; i++) {
440 for (j = 0; j < MAX_PILS; j++) {
441 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
442 }
443 }
444 sysbus_mmio_map(s, 0, addrg);
445 for (i = 0; i < MAX_CPUS; i++) {
446 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
447 }
448
449 return dev;
450}
451
452#define SYS_TIMER_OFFSET 0x10000ULL
453#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
454
455static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
456 qemu_irq *cpu_irqs, unsigned int num_cpus)
457{
458 DeviceState *dev;
459 SysBusDevice *s;
460 unsigned int i;
461
462 dev = qdev_create(NULL, "slavio_timer");
463 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
464 qdev_init_nofail(dev);
465 s = sysbus_from_qdev(dev);
466 sysbus_connect_irq(s, 0, master_irq);
467 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
468
469 for (i = 0; i < MAX_CPUS; i++) {
470 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
471 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
472 }
473}
474
475#define MISC_LEDS 0x01600000
476#define MISC_CFG 0x01800000
477#define MISC_DIAG 0x01a00000
478#define MISC_MDM 0x01b00000
479#define MISC_SYS 0x01f00000
480
481static void slavio_misc_init(target_phys_addr_t base,
482 target_phys_addr_t aux1_base,
483 target_phys_addr_t aux2_base, qemu_irq irq,
484 qemu_irq fdc_tc)
485{
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_create(NULL, "slavio_misc");
490 qdev_init_nofail(dev);
491 s = sysbus_from_qdev(dev);
492 if (base) {
493
494
495 sysbus_mmio_map(s, 0, base + MISC_CFG);
496
497 sysbus_mmio_map(s, 1, base + MISC_DIAG);
498
499 sysbus_mmio_map(s, 2, base + MISC_MDM);
500
501
502 sysbus_mmio_map(s, 3, base + MISC_LEDS);
503
504
505 sysbus_mmio_map(s, 4, base + MISC_SYS);
506 }
507 if (aux1_base) {
508
509 sysbus_mmio_map(s, 5, aux1_base);
510 }
511 if (aux2_base) {
512
513 sysbus_mmio_map(s, 6, aux2_base);
514 }
515 sysbus_connect_irq(s, 0, irq);
516 sysbus_connect_irq(s, 1, fdc_tc);
517 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
518}
519
520static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
521{
522 DeviceState *dev;
523 SysBusDevice *s;
524
525 dev = qdev_create(NULL, "eccmemctl");
526 qdev_prop_set_uint32(dev, "version", version);
527 qdev_init_nofail(dev);
528 s = sysbus_from_qdev(dev);
529 sysbus_connect_irq(s, 0, irq);
530 sysbus_mmio_map(s, 0, base);
531 if (version == 0) {
532 sysbus_mmio_map(s, 1, base + 0x1000);
533 }
534}
535
536static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
537{
538 DeviceState *dev;
539 SysBusDevice *s;
540
541 dev = qdev_create(NULL, "apc");
542 qdev_init_nofail(dev);
543 s = sysbus_from_qdev(dev);
544
545 sysbus_mmio_map(s, 0, power_base);
546 sysbus_connect_irq(s, 0, cpu_halt);
547}
548
549static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
550 int height, int depth)
551{
552 DeviceState *dev;
553 SysBusDevice *s;
554
555 dev = qdev_create(NULL, "SUNW,tcx");
556 qdev_prop_set_taddr(dev, "addr", addr);
557 qdev_prop_set_uint32(dev, "vram_size", vram_size);
558 qdev_prop_set_uint16(dev, "width", width);
559 qdev_prop_set_uint16(dev, "height", height);
560 qdev_prop_set_uint16(dev, "depth", depth);
561 qdev_init_nofail(dev);
562 s = sysbus_from_qdev(dev);
563
564 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
565
566 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
567
568 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
569
570 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
571 if (depth == 24) {
572
573 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
574
575 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
576 } else {
577
578 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
579 }
580}
581
582
583static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
584
585static void idreg_init(target_phys_addr_t addr)
586{
587 DeviceState *dev;
588 SysBusDevice *s;
589
590 dev = qdev_create(NULL, "macio_idreg");
591 qdev_init_nofail(dev);
592 s = sysbus_from_qdev(dev);
593
594 sysbus_mmio_map(s, 0, addr);
595 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
596}
597
598typedef struct IDRegState {
599 SysBusDevice busdev;
600 MemoryRegion mem;
601} IDRegState;
602
603static int idreg_init1(SysBusDevice *dev)
604{
605 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
606
607 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
608 vmstate_register_ram_global(&s->mem);
609 memory_region_set_readonly(&s->mem, true);
610 sysbus_init_mmio(dev, &s->mem);
611 return 0;
612}
613
614static void idreg_class_init(ObjectClass *klass, void *data)
615{
616 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
617
618 k->init = idreg_init1;
619}
620
621static TypeInfo idreg_info = {
622 .name = "macio_idreg",
623 .parent = TYPE_SYS_BUS_DEVICE,
624 .instance_size = sizeof(IDRegState),
625 .class_init = idreg_class_init,
626};
627
628typedef struct AFXState {
629 SysBusDevice busdev;
630 MemoryRegion mem;
631} AFXState;
632
633
634static void afx_init(target_phys_addr_t addr)
635{
636 DeviceState *dev;
637 SysBusDevice *s;
638
639 dev = qdev_create(NULL, "tcx_afx");
640 qdev_init_nofail(dev);
641 s = sysbus_from_qdev(dev);
642
643 sysbus_mmio_map(s, 0, addr);
644}
645
646static int afx_init1(SysBusDevice *dev)
647{
648 AFXState *s = FROM_SYSBUS(AFXState, dev);
649
650 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
651 vmstate_register_ram_global(&s->mem);
652 sysbus_init_mmio(dev, &s->mem);
653 return 0;
654}
655
656static void afx_class_init(ObjectClass *klass, void *data)
657{
658 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
659
660 k->init = afx_init1;
661}
662
663static TypeInfo afx_info = {
664 .name = "tcx_afx",
665 .parent = TYPE_SYS_BUS_DEVICE,
666 .instance_size = sizeof(AFXState),
667 .class_init = afx_class_init,
668};
669
670typedef struct PROMState {
671 SysBusDevice busdev;
672 MemoryRegion prom;
673} PROMState;
674
675
676static uint64_t translate_prom_address(void *opaque, uint64_t addr)
677{
678 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
679 return addr + *base_addr - PROM_VADDR;
680}
681
682static void prom_init(target_phys_addr_t addr, const char *bios_name)
683{
684 DeviceState *dev;
685 SysBusDevice *s;
686 char *filename;
687 int ret;
688
689 dev = qdev_create(NULL, "openprom");
690 qdev_init_nofail(dev);
691 s = sysbus_from_qdev(dev);
692
693 sysbus_mmio_map(s, 0, addr);
694
695
696 if (bios_name == NULL) {
697 bios_name = PROM_FILENAME;
698 }
699 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
700 if (filename) {
701 ret = load_elf(filename, translate_prom_address, &addr, NULL,
702 NULL, NULL, 1, ELF_MACHINE, 0);
703 if (ret < 0 || ret > PROM_SIZE_MAX) {
704 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
705 }
706 g_free(filename);
707 } else {
708 ret = -1;
709 }
710 if (ret < 0 || ret > PROM_SIZE_MAX) {
711 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
712 exit(1);
713 }
714}
715
716static int prom_init1(SysBusDevice *dev)
717{
718 PROMState *s = FROM_SYSBUS(PROMState, dev);
719
720 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
721 vmstate_register_ram_global(&s->prom);
722 memory_region_set_readonly(&s->prom, true);
723 sysbus_init_mmio(dev, &s->prom);
724 return 0;
725}
726
727static Property prom_properties[] = {
728 {},
729};
730
731static void prom_class_init(ObjectClass *klass, void *data)
732{
733 DeviceClass *dc = DEVICE_CLASS(klass);
734 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
735
736 k->init = prom_init1;
737 dc->props = prom_properties;
738}
739
740static TypeInfo prom_info = {
741 .name = "openprom",
742 .parent = TYPE_SYS_BUS_DEVICE,
743 .instance_size = sizeof(PROMState),
744 .class_init = prom_class_init,
745};
746
747typedef struct RamDevice
748{
749 SysBusDevice busdev;
750 MemoryRegion ram;
751 uint64_t size;
752} RamDevice;
753
754
755static int ram_init1(SysBusDevice *dev)
756{
757 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
758
759 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
760 vmstate_register_ram_global(&d->ram);
761 sysbus_init_mmio(dev, &d->ram);
762 return 0;
763}
764
765static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
766 uint64_t max_mem)
767{
768 DeviceState *dev;
769 SysBusDevice *s;
770 RamDevice *d;
771
772
773 if ((uint64_t)RAM_size > max_mem) {
774 fprintf(stderr,
775 "qemu: Too much memory for this machine: %d, maximum %d\n",
776 (unsigned int)(RAM_size / (1024 * 1024)),
777 (unsigned int)(max_mem / (1024 * 1024)));
778 exit(1);
779 }
780 dev = qdev_create(NULL, "memory");
781 s = sysbus_from_qdev(dev);
782
783 d = FROM_SYSBUS(RamDevice, s);
784 d->size = RAM_size;
785 qdev_init_nofail(dev);
786
787 sysbus_mmio_map(s, 0, addr);
788}
789
790static Property ram_properties[] = {
791 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
792 DEFINE_PROP_END_OF_LIST(),
793};
794
795static void ram_class_init(ObjectClass *klass, void *data)
796{
797 DeviceClass *dc = DEVICE_CLASS(klass);
798 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
799
800 k->init = ram_init1;
801 dc->props = ram_properties;
802}
803
804static TypeInfo ram_info = {
805 .name = "memory",
806 .parent = TYPE_SYS_BUS_DEVICE,
807 .instance_size = sizeof(RamDevice),
808 .class_init = ram_class_init,
809};
810
811static void cpu_devinit(const char *cpu_model, unsigned int id,
812 uint64_t prom_addr, qemu_irq **cpu_irqs)
813{
814 SPARCCPU *cpu;
815 CPUSPARCState *env;
816
817 cpu = cpu_sparc_init(cpu_model);
818 if (cpu == NULL) {
819 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
820 exit(1);
821 }
822 env = &cpu->env;
823
824 cpu_sparc_set_id(env, id);
825 if (id == 0) {
826 qemu_register_reset(main_cpu_reset, cpu);
827 } else {
828 qemu_register_reset(secondary_cpu_reset, cpu);
829 env->halted = 1;
830 }
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
832 env->prom_addr = prom_addr;
833}
834
835static void dummy_fdc_tc(void *opaque, int irq, int level)
836{
837}
838
839static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
840 const char *boot_device,
841 const char *kernel_filename,
842 const char *kernel_cmdline,
843 const char *initrd_filename, const char *cpu_model)
844{
845 unsigned int i;
846 void *iommu, *espdma, *ledma, *nvram;
847 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
848 espdma_irq, ledma_irq;
849 qemu_irq esp_reset, dma_enable;
850 qemu_irq fdc_tc;
851 qemu_irq *cpu_halt;
852 unsigned long kernel_size;
853 DriveInfo *fd[MAX_FD];
854 void *fw_cfg;
855 unsigned int num_vsimms;
856
857
858 if (!cpu_model)
859 cpu_model = hwdef->default_cpu_model;
860
861 for(i = 0; i < smp_cpus; i++) {
862 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
863 }
864
865 for (i = smp_cpus; i < MAX_CPUS; i++)
866 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
867
868
869
870 ram_init(0, RAM_size, hwdef->max_mem);
871
872 if (!hwdef->ecc_base) {
873 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
874 }
875
876 prom_init(hwdef->slavio_base, bios_name);
877
878 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
879 hwdef->intctl_base + 0x10000ULL,
880 cpu_irqs);
881
882 for (i = 0; i < 32; i++) {
883 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
884 }
885 for (i = 0; i < MAX_CPUS; i++) {
886 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
887 }
888
889 if (hwdef->idreg_base) {
890 idreg_init(hwdef->idreg_base);
891 }
892
893 if (hwdef->afx_base) {
894 afx_init(hwdef->afx_base);
895 }
896
897 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
898 slavio_irq[30]);
899
900 if (hwdef->iommu_pad_base) {
901
902
903
904
905 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
906 }
907
908 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
909 iommu, &espdma_irq, 0);
910
911 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
912 slavio_irq[16], iommu, &ledma_irq, 1);
913
914 if (graphic_depth != 8 && graphic_depth != 24) {
915 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
916 exit (1);
917 }
918 num_vsimms = 0;
919 if (num_vsimms == 0) {
920 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
921 graphic_depth);
922 }
923
924 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
925
926 if (hwdef->vsimm[i].reg_base) {
927 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
928 }
929 }
930
931 if (hwdef->sx_base) {
932 empty_slot_init(hwdef->sx_base, 0x2000);
933 }
934
935 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
936
937 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
938
939 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
940
941 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
942 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
943
944
945 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
946 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
947
948 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
949 if (hwdef->apc_base) {
950 apc_init(hwdef->apc_base, cpu_halt[0]);
951 }
952
953 if (hwdef->fd_base) {
954
955 memset(fd, 0, sizeof(fd));
956 fd[0] = drive_get(IF_FLOPPY, 0, 0);
957 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
958 &fdc_tc);
959 } else {
960 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
961 }
962
963 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
964 slavio_irq[30], fdc_tc);
965
966 if (drive_get_max_bus(IF_SCSI) > 0) {
967 fprintf(stderr, "qemu: too many SCSI bus\n");
968 exit(1);
969 }
970
971 esp_init(hwdef->esp_base, 2,
972 espdma_memory_read, espdma_memory_write,
973 espdma, espdma_irq, &esp_reset, &dma_enable);
974
975 qdev_connect_gpio_out(espdma, 0, esp_reset);
976 qdev_connect_gpio_out(espdma, 1, dma_enable);
977
978 if (hwdef->cs_base) {
979 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
980 slavio_irq[5]);
981 }
982
983 if (hwdef->dbri_base) {
984
985
986 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
987
988 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
989 }
990
991 if (hwdef->bpp_base) {
992
993 empty_slot_init(hwdef->bpp_base, 0x20);
994 }
995
996 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
997 RAM_size);
998
999 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1000 boot_device, RAM_size, kernel_size, graphic_width,
1001 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1002 "Sun4m");
1003
1004 if (hwdef->ecc_base)
1005 ecc_init(hwdef->ecc_base, slavio_irq[28],
1006 hwdef->ecc_version);
1007
1008 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1009 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1010 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1011 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1013 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1015 if (kernel_cmdline) {
1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1017 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1018 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1019 (uint8_t*)strdup(kernel_cmdline),
1020 strlen(kernel_cmdline) + 1);
1021 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1022 strlen(kernel_cmdline) + 1);
1023 } else {
1024 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1025 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1026 }
1027 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1029 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1030 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1031}
1032
1033enum {
1034 ss2_id = 0,
1035 ss5_id = 32,
1036 vger_id,
1037 lx_id,
1038 ss4_id,
1039 scls_id,
1040 sbook_id,
1041 ss10_id = 64,
1042 ss20_id,
1043 ss600mp_id,
1044 ss1000_id = 96,
1045 ss2000_id,
1046};
1047
1048static const struct sun4m_hwdef sun4m_hwdefs[] = {
1049
1050 {
1051 .iommu_base = 0x10000000,
1052 .iommu_pad_base = 0x10004000,
1053 .iommu_pad_len = 0x0fffb000,
1054 .tcx_base = 0x50000000,
1055 .cs_base = 0x6c000000,
1056 .slavio_base = 0x70000000,
1057 .ms_kb_base = 0x71000000,
1058 .serial_base = 0x71100000,
1059 .nvram_base = 0x71200000,
1060 .fd_base = 0x71400000,
1061 .counter_base = 0x71d00000,
1062 .intctl_base = 0x71e00000,
1063 .idreg_base = 0x78000000,
1064 .dma_base = 0x78400000,
1065 .esp_base = 0x78800000,
1066 .le_base = 0x78c00000,
1067 .apc_base = 0x6a000000,
1068 .afx_base = 0x6e000000,
1069 .aux1_base = 0x71900000,
1070 .aux2_base = 0x71910000,
1071 .nvram_machine_id = 0x80,
1072 .machine_id = ss5_id,
1073 .iommu_version = 0x05000000,
1074 .max_mem = 0x10000000,
1075 .default_cpu_model = "Fujitsu MB86904",
1076 },
1077
1078 {
1079 .iommu_base = 0xfe0000000ULL,
1080 .tcx_base = 0xe20000000ULL,
1081 .slavio_base = 0xff0000000ULL,
1082 .ms_kb_base = 0xff1000000ULL,
1083 .serial_base = 0xff1100000ULL,
1084 .nvram_base = 0xff1200000ULL,
1085 .fd_base = 0xff1700000ULL,
1086 .counter_base = 0xff1300000ULL,
1087 .intctl_base = 0xff1400000ULL,
1088 .idreg_base = 0xef0000000ULL,
1089 .dma_base = 0xef0400000ULL,
1090 .esp_base = 0xef0800000ULL,
1091 .le_base = 0xef0c00000ULL,
1092 .apc_base = 0xefa000000ULL,
1093 .aux1_base = 0xff1800000ULL,
1094 .aux2_base = 0xff1a01000ULL,
1095 .ecc_base = 0xf00000000ULL,
1096 .ecc_version = 0x10000000,
1097 .nvram_machine_id = 0x72,
1098 .machine_id = ss10_id,
1099 .iommu_version = 0x03000000,
1100 .max_mem = 0xf00000000ULL,
1101 .default_cpu_model = "TI SuperSparc II",
1102 },
1103
1104 {
1105 .iommu_base = 0xfe0000000ULL,
1106 .tcx_base = 0xe20000000ULL,
1107 .slavio_base = 0xff0000000ULL,
1108 .ms_kb_base = 0xff1000000ULL,
1109 .serial_base = 0xff1100000ULL,
1110 .nvram_base = 0xff1200000ULL,
1111 .counter_base = 0xff1300000ULL,
1112 .intctl_base = 0xff1400000ULL,
1113 .dma_base = 0xef0081000ULL,
1114 .esp_base = 0xef0080000ULL,
1115 .le_base = 0xef0060000ULL,
1116 .apc_base = 0xefa000000ULL,
1117 .aux1_base = 0xff1800000ULL,
1118 .aux2_base = 0xff1a01000ULL,
1119 .ecc_base = 0xf00000000ULL,
1120 .ecc_version = 0x00000000,
1121 .nvram_machine_id = 0x71,
1122 .machine_id = ss600mp_id,
1123 .iommu_version = 0x01000000,
1124 .max_mem = 0xf00000000ULL,
1125 .default_cpu_model = "TI SuperSparc II",
1126 },
1127
1128 {
1129 .iommu_base = 0xfe0000000ULL,
1130 .tcx_base = 0xe20000000ULL,
1131 .slavio_base = 0xff0000000ULL,
1132 .ms_kb_base = 0xff1000000ULL,
1133 .serial_base = 0xff1100000ULL,
1134 .nvram_base = 0xff1200000ULL,
1135 .fd_base = 0xff1700000ULL,
1136 .counter_base = 0xff1300000ULL,
1137 .intctl_base = 0xff1400000ULL,
1138 .idreg_base = 0xef0000000ULL,
1139 .dma_base = 0xef0400000ULL,
1140 .esp_base = 0xef0800000ULL,
1141 .le_base = 0xef0c00000ULL,
1142 .bpp_base = 0xef4800000ULL,
1143 .apc_base = 0xefa000000ULL,
1144 .aux1_base = 0xff1800000ULL,
1145 .aux2_base = 0xff1a01000ULL,
1146 .dbri_base = 0xee0000000ULL,
1147 .sx_base = 0xf80000000ULL,
1148 .vsimm = {
1149 {
1150 .reg_base = 0x9c000000ULL,
1151 .vram_base = 0xfc000000ULL
1152 }, {
1153 .reg_base = 0x90000000ULL,
1154 .vram_base = 0xf0000000ULL
1155 }, {
1156 .reg_base = 0x94000000ULL
1157 }, {
1158 .reg_base = 0x98000000ULL
1159 }
1160 },
1161 .ecc_base = 0xf00000000ULL,
1162 .ecc_version = 0x20000000,
1163 .nvram_machine_id = 0x72,
1164 .machine_id = ss20_id,
1165 .iommu_version = 0x13000000,
1166 .max_mem = 0xf00000000ULL,
1167 .default_cpu_model = "TI SuperSparc II",
1168 },
1169
1170 {
1171 .iommu_base = 0x10000000,
1172 .tcx_base = 0x50000000,
1173 .slavio_base = 0x70000000,
1174 .ms_kb_base = 0x71000000,
1175 .serial_base = 0x71100000,
1176 .nvram_base = 0x71200000,
1177 .fd_base = 0x71400000,
1178 .counter_base = 0x71d00000,
1179 .intctl_base = 0x71e00000,
1180 .idreg_base = 0x78000000,
1181 .dma_base = 0x78400000,
1182 .esp_base = 0x78800000,
1183 .le_base = 0x78c00000,
1184 .apc_base = 0x71300000,
1185 .aux1_base = 0x71900000,
1186 .aux2_base = 0x71910000,
1187 .nvram_machine_id = 0x80,
1188 .machine_id = vger_id,
1189 .iommu_version = 0x05000000,
1190 .max_mem = 0x10000000,
1191 .default_cpu_model = "Fujitsu MB86904",
1192 },
1193
1194 {
1195 .iommu_base = 0x10000000,
1196 .iommu_pad_base = 0x10004000,
1197 .iommu_pad_len = 0x0fffb000,
1198 .tcx_base = 0x50000000,
1199 .slavio_base = 0x70000000,
1200 .ms_kb_base = 0x71000000,
1201 .serial_base = 0x71100000,
1202 .nvram_base = 0x71200000,
1203 .fd_base = 0x71400000,
1204 .counter_base = 0x71d00000,
1205 .intctl_base = 0x71e00000,
1206 .idreg_base = 0x78000000,
1207 .dma_base = 0x78400000,
1208 .esp_base = 0x78800000,
1209 .le_base = 0x78c00000,
1210 .aux1_base = 0x71900000,
1211 .aux2_base = 0x71910000,
1212 .nvram_machine_id = 0x80,
1213 .machine_id = lx_id,
1214 .iommu_version = 0x04000000,
1215 .max_mem = 0x10000000,
1216 .default_cpu_model = "TI MicroSparc I",
1217 },
1218
1219 {
1220 .iommu_base = 0x10000000,
1221 .tcx_base = 0x50000000,
1222 .cs_base = 0x6c000000,
1223 .slavio_base = 0x70000000,
1224 .ms_kb_base = 0x71000000,
1225 .serial_base = 0x71100000,
1226 .nvram_base = 0x71200000,
1227 .fd_base = 0x71400000,
1228 .counter_base = 0x71d00000,
1229 .intctl_base = 0x71e00000,
1230 .idreg_base = 0x78000000,
1231 .dma_base = 0x78400000,
1232 .esp_base = 0x78800000,
1233 .le_base = 0x78c00000,
1234 .apc_base = 0x6a000000,
1235 .aux1_base = 0x71900000,
1236 .aux2_base = 0x71910000,
1237 .nvram_machine_id = 0x80,
1238 .machine_id = ss4_id,
1239 .iommu_version = 0x05000000,
1240 .max_mem = 0x10000000,
1241 .default_cpu_model = "Fujitsu MB86904",
1242 },
1243
1244 {
1245 .iommu_base = 0x10000000,
1246 .tcx_base = 0x50000000,
1247 .slavio_base = 0x70000000,
1248 .ms_kb_base = 0x71000000,
1249 .serial_base = 0x71100000,
1250 .nvram_base = 0x71200000,
1251 .fd_base = 0x71400000,
1252 .counter_base = 0x71d00000,
1253 .intctl_base = 0x71e00000,
1254 .idreg_base = 0x78000000,
1255 .dma_base = 0x78400000,
1256 .esp_base = 0x78800000,
1257 .le_base = 0x78c00000,
1258 .apc_base = 0x6a000000,
1259 .aux1_base = 0x71900000,
1260 .aux2_base = 0x71910000,
1261 .nvram_machine_id = 0x80,
1262 .machine_id = scls_id,
1263 .iommu_version = 0x05000000,
1264 .max_mem = 0x10000000,
1265 .default_cpu_model = "TI MicroSparc I",
1266 },
1267
1268 {
1269 .iommu_base = 0x10000000,
1270 .tcx_base = 0x50000000,
1271 .slavio_base = 0x70000000,
1272 .ms_kb_base = 0x71000000,
1273 .serial_base = 0x71100000,
1274 .nvram_base = 0x71200000,
1275 .fd_base = 0x71400000,
1276 .counter_base = 0x71d00000,
1277 .intctl_base = 0x71e00000,
1278 .idreg_base = 0x78000000,
1279 .dma_base = 0x78400000,
1280 .esp_base = 0x78800000,
1281 .le_base = 0x78c00000,
1282 .apc_base = 0x6a000000,
1283 .aux1_base = 0x71900000,
1284 .aux2_base = 0x71910000,
1285 .nvram_machine_id = 0x80,
1286 .machine_id = sbook_id,
1287 .iommu_version = 0x05000000,
1288 .max_mem = 0x10000000,
1289 .default_cpu_model = "TI MicroSparc I",
1290 },
1291};
1292
1293
1294static void ss5_init(ram_addr_t RAM_size,
1295 const char *boot_device,
1296 const char *kernel_filename, const char *kernel_cmdline,
1297 const char *initrd_filename, const char *cpu_model)
1298{
1299 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1300 kernel_cmdline, initrd_filename, cpu_model);
1301}
1302
1303
1304static void ss10_init(ram_addr_t RAM_size,
1305 const char *boot_device,
1306 const char *kernel_filename, const char *kernel_cmdline,
1307 const char *initrd_filename, const char *cpu_model)
1308{
1309 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1310 kernel_cmdline, initrd_filename, cpu_model);
1311}
1312
1313
1314static void ss600mp_init(ram_addr_t RAM_size,
1315 const char *boot_device,
1316 const char *kernel_filename,
1317 const char *kernel_cmdline,
1318 const char *initrd_filename, const char *cpu_model)
1319{
1320 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1321 kernel_cmdline, initrd_filename, cpu_model);
1322}
1323
1324
1325static void ss20_init(ram_addr_t RAM_size,
1326 const char *boot_device,
1327 const char *kernel_filename, const char *kernel_cmdline,
1328 const char *initrd_filename, const char *cpu_model)
1329{
1330 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1331 kernel_cmdline, initrd_filename, cpu_model);
1332}
1333
1334
1335static void vger_init(ram_addr_t RAM_size,
1336 const char *boot_device,
1337 const char *kernel_filename, const char *kernel_cmdline,
1338 const char *initrd_filename, const char *cpu_model)
1339{
1340 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1341 kernel_cmdline, initrd_filename, cpu_model);
1342}
1343
1344
1345static void ss_lx_init(ram_addr_t RAM_size,
1346 const char *boot_device,
1347 const char *kernel_filename, const char *kernel_cmdline,
1348 const char *initrd_filename, const char *cpu_model)
1349{
1350 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1351 kernel_cmdline, initrd_filename, cpu_model);
1352}
1353
1354
1355static void ss4_init(ram_addr_t RAM_size,
1356 const char *boot_device,
1357 const char *kernel_filename, const char *kernel_cmdline,
1358 const char *initrd_filename, const char *cpu_model)
1359{
1360 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1361 kernel_cmdline, initrd_filename, cpu_model);
1362}
1363
1364
1365static void scls_init(ram_addr_t RAM_size,
1366 const char *boot_device,
1367 const char *kernel_filename, const char *kernel_cmdline,
1368 const char *initrd_filename, const char *cpu_model)
1369{
1370 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1371 kernel_cmdline, initrd_filename, cpu_model);
1372}
1373
1374
1375static void sbook_init(ram_addr_t RAM_size,
1376 const char *boot_device,
1377 const char *kernel_filename, const char *kernel_cmdline,
1378 const char *initrd_filename, const char *cpu_model)
1379{
1380 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1381 kernel_cmdline, initrd_filename, cpu_model);
1382}
1383
1384static QEMUMachine ss5_machine = {
1385 .name = "SS-5",
1386 .desc = "Sun4m platform, SPARCstation 5",
1387 .init = ss5_init,
1388 .use_scsi = 1,
1389 .is_default = 1,
1390};
1391
1392static QEMUMachine ss10_machine = {
1393 .name = "SS-10",
1394 .desc = "Sun4m platform, SPARCstation 10",
1395 .init = ss10_init,
1396 .use_scsi = 1,
1397 .max_cpus = 4,
1398};
1399
1400static QEMUMachine ss600mp_machine = {
1401 .name = "SS-600MP",
1402 .desc = "Sun4m platform, SPARCserver 600MP",
1403 .init = ss600mp_init,
1404 .use_scsi = 1,
1405 .max_cpus = 4,
1406};
1407
1408static QEMUMachine ss20_machine = {
1409 .name = "SS-20",
1410 .desc = "Sun4m platform, SPARCstation 20",
1411 .init = ss20_init,
1412 .use_scsi = 1,
1413 .max_cpus = 4,
1414};
1415
1416static QEMUMachine voyager_machine = {
1417 .name = "Voyager",
1418 .desc = "Sun4m platform, SPARCstation Voyager",
1419 .init = vger_init,
1420 .use_scsi = 1,
1421};
1422
1423static QEMUMachine ss_lx_machine = {
1424 .name = "LX",
1425 .desc = "Sun4m platform, SPARCstation LX",
1426 .init = ss_lx_init,
1427 .use_scsi = 1,
1428};
1429
1430static QEMUMachine ss4_machine = {
1431 .name = "SS-4",
1432 .desc = "Sun4m platform, SPARCstation 4",
1433 .init = ss4_init,
1434 .use_scsi = 1,
1435};
1436
1437static QEMUMachine scls_machine = {
1438 .name = "SPARCClassic",
1439 .desc = "Sun4m platform, SPARCClassic",
1440 .init = scls_init,
1441 .use_scsi = 1,
1442};
1443
1444static QEMUMachine sbook_machine = {
1445 .name = "SPARCbook",
1446 .desc = "Sun4m platform, SPARCbook",
1447 .init = sbook_init,
1448 .use_scsi = 1,
1449};
1450
1451static const struct sun4d_hwdef sun4d_hwdefs[] = {
1452
1453 {
1454 .iounit_bases = {
1455 0xfe0200000ULL,
1456 0xfe1200000ULL,
1457 0xfe2200000ULL,
1458 0xfe3200000ULL,
1459 -1,
1460 },
1461 .tcx_base = 0x820000000ULL,
1462 .slavio_base = 0xf00000000ULL,
1463 .ms_kb_base = 0xf00240000ULL,
1464 .serial_base = 0xf00200000ULL,
1465 .nvram_base = 0xf00280000ULL,
1466 .counter_base = 0xf00300000ULL,
1467 .espdma_base = 0x800081000ULL,
1468 .esp_base = 0x800080000ULL,
1469 .ledma_base = 0x800040000ULL,
1470 .le_base = 0x800060000ULL,
1471 .sbi_base = 0xf02800000ULL,
1472 .nvram_machine_id = 0x80,
1473 .machine_id = ss1000_id,
1474 .iounit_version = 0x03000000,
1475 .max_mem = 0xf00000000ULL,
1476 .default_cpu_model = "TI SuperSparc II",
1477 },
1478
1479 {
1480 .iounit_bases = {
1481 0xfe0200000ULL,
1482 0xfe1200000ULL,
1483 0xfe2200000ULL,
1484 0xfe3200000ULL,
1485 0xfe4200000ULL,
1486 },
1487 .tcx_base = 0x820000000ULL,
1488 .slavio_base = 0xf00000000ULL,
1489 .ms_kb_base = 0xf00240000ULL,
1490 .serial_base = 0xf00200000ULL,
1491 .nvram_base = 0xf00280000ULL,
1492 .counter_base = 0xf00300000ULL,
1493 .espdma_base = 0x800081000ULL,
1494 .esp_base = 0x800080000ULL,
1495 .ledma_base = 0x800040000ULL,
1496 .le_base = 0x800060000ULL,
1497 .sbi_base = 0xf02800000ULL,
1498 .nvram_machine_id = 0x80,
1499 .machine_id = ss2000_id,
1500 .iounit_version = 0x03000000,
1501 .max_mem = 0xf00000000ULL,
1502 .default_cpu_model = "TI SuperSparc II",
1503 },
1504};
1505
1506static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1507{
1508 DeviceState *dev;
1509 SysBusDevice *s;
1510 unsigned int i;
1511
1512 dev = qdev_create(NULL, "sbi");
1513 qdev_init_nofail(dev);
1514
1515 s = sysbus_from_qdev(dev);
1516
1517 for (i = 0; i < MAX_CPUS; i++) {
1518 sysbus_connect_irq(s, i, *parent_irq[i]);
1519 }
1520
1521 sysbus_mmio_map(s, 0, addr);
1522
1523 return dev;
1524}
1525
1526static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1527 const char *boot_device,
1528 const char *kernel_filename,
1529 const char *kernel_cmdline,
1530 const char *initrd_filename, const char *cpu_model)
1531{
1532 unsigned int i;
1533 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1534 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1535 espdma_irq, ledma_irq;
1536 qemu_irq esp_reset, dma_enable;
1537 unsigned long kernel_size;
1538 void *fw_cfg;
1539 DeviceState *dev;
1540
1541
1542 if (!cpu_model)
1543 cpu_model = hwdef->default_cpu_model;
1544
1545 for(i = 0; i < smp_cpus; i++) {
1546 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1547 }
1548
1549 for (i = smp_cpus; i < MAX_CPUS; i++)
1550 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1551
1552
1553 ram_init(0, RAM_size, hwdef->max_mem);
1554
1555 prom_init(hwdef->slavio_base, bios_name);
1556
1557 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1558
1559 for (i = 0; i < 32; i++) {
1560 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1561 }
1562 for (i = 0; i < MAX_CPUS; i++) {
1563 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1564 }
1565
1566 for (i = 0; i < MAX_IOUNITS; i++)
1567 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1568 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1569 hwdef->iounit_version,
1570 sbi_irq[0]);
1571
1572 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1573 iounits[0], &espdma_irq, 0);
1574
1575
1576 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1577 iounits[0], &ledma_irq, 0);
1578
1579 if (graphic_depth != 8 && graphic_depth != 24) {
1580 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1581 exit (1);
1582 }
1583 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1584 graphic_depth);
1585
1586 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1587
1588 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1589
1590 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1591
1592 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1593 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1594
1595
1596 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1597 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1598
1599 if (drive_get_max_bus(IF_SCSI) > 0) {
1600 fprintf(stderr, "qemu: too many SCSI bus\n");
1601 exit(1);
1602 }
1603
1604 esp_init(hwdef->esp_base, 2,
1605 espdma_memory_read, espdma_memory_write,
1606 espdma, espdma_irq, &esp_reset, &dma_enable);
1607
1608 qdev_connect_gpio_out(espdma, 0, esp_reset);
1609 qdev_connect_gpio_out(espdma, 1, dma_enable);
1610
1611 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1612 RAM_size);
1613
1614 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1615 boot_device, RAM_size, kernel_size, graphic_width,
1616 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1617 "Sun4d");
1618
1619 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1620 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1621 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1622 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1623 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1624 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1625 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1626 if (kernel_cmdline) {
1627 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1628 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1629 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1630 (uint8_t*)strdup(kernel_cmdline),
1631 strlen(kernel_cmdline) + 1);
1632 } else {
1633 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1634 }
1635 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1636 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1637 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1638 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1639}
1640
1641
1642static void ss1000_init(ram_addr_t RAM_size,
1643 const char *boot_device,
1644 const char *kernel_filename, const char *kernel_cmdline,
1645 const char *initrd_filename, const char *cpu_model)
1646{
1647 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1648 kernel_cmdline, initrd_filename, cpu_model);
1649}
1650
1651
1652static void ss2000_init(ram_addr_t RAM_size,
1653 const char *boot_device,
1654 const char *kernel_filename, const char *kernel_cmdline,
1655 const char *initrd_filename, const char *cpu_model)
1656{
1657 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1658 kernel_cmdline, initrd_filename, cpu_model);
1659}
1660
1661static QEMUMachine ss1000_machine = {
1662 .name = "SS-1000",
1663 .desc = "Sun4d platform, SPARCserver 1000",
1664 .init = ss1000_init,
1665 .use_scsi = 1,
1666 .max_cpus = 8,
1667};
1668
1669static QEMUMachine ss2000_machine = {
1670 .name = "SS-2000",
1671 .desc = "Sun4d platform, SPARCcenter 2000",
1672 .init = ss2000_init,
1673 .use_scsi = 1,
1674 .max_cpus = 20,
1675};
1676
1677static const struct sun4c_hwdef sun4c_hwdefs[] = {
1678
1679 {
1680 .iommu_base = 0xf8000000,
1681 .tcx_base = 0xfe000000,
1682 .slavio_base = 0xf6000000,
1683 .intctl_base = 0xf5000000,
1684 .counter_base = 0xf3000000,
1685 .ms_kb_base = 0xf0000000,
1686 .serial_base = 0xf1000000,
1687 .nvram_base = 0xf2000000,
1688 .fd_base = 0xf7200000,
1689 .dma_base = 0xf8400000,
1690 .esp_base = 0xf8800000,
1691 .le_base = 0xf8c00000,
1692 .aux1_base = 0xf7400003,
1693 .nvram_machine_id = 0x55,
1694 .machine_id = ss2_id,
1695 .max_mem = 0x10000000,
1696 .default_cpu_model = "Cypress CY7C601",
1697 },
1698};
1699
1700static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1701 qemu_irq *parent_irq)
1702{
1703 DeviceState *dev;
1704 SysBusDevice *s;
1705 unsigned int i;
1706
1707 dev = qdev_create(NULL, "sun4c_intctl");
1708 qdev_init_nofail(dev);
1709
1710 s = sysbus_from_qdev(dev);
1711
1712 for (i = 0; i < MAX_PILS; i++) {
1713 sysbus_connect_irq(s, i, parent_irq[i]);
1714 }
1715 sysbus_mmio_map(s, 0, addr);
1716
1717 return dev;
1718}
1719
1720static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1721 const char *boot_device,
1722 const char *kernel_filename,
1723 const char *kernel_cmdline,
1724 const char *initrd_filename, const char *cpu_model)
1725{
1726 void *iommu, *espdma, *ledma, *nvram;
1727 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1728 qemu_irq esp_reset, dma_enable;
1729 qemu_irq fdc_tc;
1730 unsigned long kernel_size;
1731 DriveInfo *fd[MAX_FD];
1732 void *fw_cfg;
1733 DeviceState *dev;
1734 unsigned int i;
1735
1736
1737 if (!cpu_model)
1738 cpu_model = hwdef->default_cpu_model;
1739
1740 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1741
1742
1743 ram_init(0, RAM_size, hwdef->max_mem);
1744
1745 prom_init(hwdef->slavio_base, bios_name);
1746
1747 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1748
1749 for (i = 0; i < 8; i++) {
1750 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1751 }
1752
1753 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1754 slavio_irq[1]);
1755
1756 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1757 iommu, &espdma_irq, 0);
1758
1759 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1760 slavio_irq[3], iommu, &ledma_irq, 1);
1761
1762 if (graphic_depth != 8 && graphic_depth != 24) {
1763 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1764 exit (1);
1765 }
1766 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1767 graphic_depth);
1768
1769 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1770
1771 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1772
1773 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1774 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1775
1776
1777 escc_init(hwdef->serial_base, slavio_irq[1],
1778 slavio_irq[1], serial_hds[0], serial_hds[1],
1779 ESCC_CLOCK, 1);
1780
1781 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1782
1783 memset(fd, 0, sizeof(fd));
1784 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1785 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1786 &fdc_tc);
1787 } else {
1788 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1789 }
1790
1791 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1792
1793 if (drive_get_max_bus(IF_SCSI) > 0) {
1794 fprintf(stderr, "qemu: too many SCSI bus\n");
1795 exit(1);
1796 }
1797
1798 esp_init(hwdef->esp_base, 2,
1799 espdma_memory_read, espdma_memory_write,
1800 espdma, espdma_irq, &esp_reset, &dma_enable);
1801
1802 qdev_connect_gpio_out(espdma, 0, esp_reset);
1803 qdev_connect_gpio_out(espdma, 1, dma_enable);
1804
1805 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1806 RAM_size);
1807
1808 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1809 boot_device, RAM_size, kernel_size, graphic_width,
1810 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1811 "Sun4c");
1812
1813 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1814 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1815 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1816 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1817 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1818 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1819 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1820 if (kernel_cmdline) {
1821 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1822 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1823 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1824 (uint8_t*)strdup(kernel_cmdline),
1825 strlen(kernel_cmdline) + 1);
1826 } else {
1827 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1828 }
1829 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1830 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1831 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1832 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1833}
1834
1835
1836static void ss2_init(ram_addr_t RAM_size,
1837 const char *boot_device,
1838 const char *kernel_filename, const char *kernel_cmdline,
1839 const char *initrd_filename, const char *cpu_model)
1840{
1841 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1842 kernel_cmdline, initrd_filename, cpu_model);
1843}
1844
1845static QEMUMachine ss2_machine = {
1846 .name = "SS-2",
1847 .desc = "Sun4c platform, SPARCstation 2",
1848 .init = ss2_init,
1849 .use_scsi = 1,
1850};
1851
1852static void sun4m_register_types(void)
1853{
1854 type_register_static(&idreg_info);
1855 type_register_static(&afx_info);
1856 type_register_static(&prom_info);
1857 type_register_static(&ram_info);
1858}
1859
1860static void ss2_machine_init(void)
1861{
1862 qemu_register_machine(&ss5_machine);
1863 qemu_register_machine(&ss10_machine);
1864 qemu_register_machine(&ss600mp_machine);
1865 qemu_register_machine(&ss20_machine);
1866 qemu_register_machine(&voyager_machine);
1867 qemu_register_machine(&ss_lx_machine);
1868 qemu_register_machine(&ss4_machine);
1869 qemu_register_machine(&scls_machine);
1870 qemu_register_machine(&sbook_machine);
1871 qemu_register_machine(&ss1000_machine);
1872 qemu_register_machine(&ss2000_machine);
1873 qemu_register_machine(&ss2_machine);
1874}
1875
1876type_init(sun4m_register_types)
1877machine_init(ss2_machine_init);
1878
