LXR qemu/hw/apic_internal.h

   1/*
   2 *  APIC support - internal interfaces
   3 *
   4 *  Copyright (c) 2004-2005 Fabrice Bellard
   5 *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19 */
  20#ifndef QEMU_APIC_INTERNAL_H
  21#define QEMU_APIC_INTERNAL_H
  22
  23#include "memory.h"
  24#include "sysbus.h"
  25#include "qemu-timer.h"
  26
  27/* APIC Local Vector Table */
  28#define APIC_LVT_TIMER                  0
  29#define APIC_LVT_THERMAL                1
  30#define APIC_LVT_PERFORM                2
  31#define APIC_LVT_LINT0                  3
  32#define APIC_LVT_LINT1                  4
  33#define APIC_LVT_ERROR                  5
  34#define APIC_LVT_NB                     6
  35
  36/* APIC delivery modes */
  37#define APIC_DM_FIXED                   0
  38#define APIC_DM_LOWPRI                  1
  39#define APIC_DM_SMI                     2
  40#define APIC_DM_NMI                     4
  41#define APIC_DM_INIT                    5
  42#define APIC_DM_SIPI                    6
  43#define APIC_DM_EXTINT                  7
  44
  45/* APIC destination mode */
  46#define APIC_DESTMODE_FLAT              0xf
  47#define APIC_DESTMODE_CLUSTER           1
  48
  49#define APIC_TRIGGER_EDGE               0
  50#define APIC_TRIGGER_LEVEL              1
  51
  52#define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53#define APIC_LVT_MASKED                 (1<<16)
  54#define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55#define APIC_LVT_REMOTE_IRR             (1<<14)
  56#define APIC_INPUT_POLARITY             (1<<13)
  57#define APIC_SEND_PENDING               (1<<12)
  58
  59#define ESR_ILLEGAL_ADDRESS (1 << 7)
  60
  61#define APIC_SV_DIRECTED_IO             (1<<12)
  62#define APIC_SV_ENABLE                  (1<<8)
  63
  64#define VAPIC_ENABLE_BIT                0
  65#define VAPIC_ENABLE_MASK               (1 << VAPIC_ENABLE_BIT)
  66
  67#define MAX_APICS 255
  68
  69#define MSI_SPACE_SIZE                  0x100000
  70
  71typedef struct APICCommonState APICCommonState;
  72
  73#define TYPE_APIC_COMMON "apic-common"
  74#define APIC_COMMON(obj) \
  75     OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
  76#define APIC_COMMON_CLASS(klass) \
  77     OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
  78#define APIC_COMMON_GET_CLASS(obj) \
  79     OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
  80
  81typedef struct APICCommonClass
  82{
  83    SysBusDeviceClass parent_class;
  84
  85    void (*init)(APICCommonState *s);
  86    void (*set_base)(APICCommonState *s, uint64_t val);
  87    void (*set_tpr)(APICCommonState *s, uint8_t val);
  88    uint8_t (*get_tpr)(APICCommonState *s);
  89    void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
  90    void (*vapic_base_update)(APICCommonState *s);
  91    void (*external_nmi)(APICCommonState *s);
  92    void (*pre_save)(APICCommonState *s);
  93    void (*post_load)(APICCommonState *s);
  94} APICCommonClass;
  95
  96struct APICCommonState {
  97    SysBusDevice busdev;
  98
  99    MemoryRegion io_memory;
 100    X86CPU *cpu;
 101    uint32_t apicbase;
 102    uint8_t id;
 103    uint8_t arb_id;
 104    uint8_t tpr;
 105    uint32_t spurious_vec;
 106    uint8_t log_dest;
 107    uint8_t dest_mode;
 108    uint32_t isr[8];  /* in service register */
 109    uint32_t tmr[8];  /* trigger mode register */
 110    uint32_t irr[8]; /* interrupt request register */
 111    uint32_t lvt[APIC_LVT_NB];
 112    uint32_t esr; /* error register */
 113    uint32_t icr[2];
 114
 115    uint32_t divide_conf;
 116    int count_shift;
 117    uint32_t initial_count;
 118    int64_t initial_count_load_time;
 119    int64_t next_time;
 120    int idx;
 121    QEMUTimer *timer;
 122    int64_t timer_expiry;
 123    int sipi_vector;
 124    int wait_for_sipi;
 125
 126    uint32_t vapic_control;
 127    DeviceState *vapic;
 128    hwaddr vapic_paddr; /* note: persistence via kvmvapic */
 129};
 130
 131typedef struct VAPICState {
 132    uint8_t tpr;
 133    uint8_t isr;
 134    uint8_t zero;
 135    uint8_t irr;
 136    uint8_t enabled;
 137} QEMU_PACKED VAPICState;
 138
 139extern bool apic_report_tpr_access;
 140
 141void apic_report_irq_delivered(int delivered);
 142bool apic_next_timer(APICCommonState *s, int64_t current_time);
 143void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
 144void apic_enable_vapic(DeviceState *d, hwaddr paddr);
 145
 146void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
 147                             TPRAccess access);
 148
 149#endif /* !QEMU_APIC_INTERNAL_H */
 150