LXR qemu/target-openrisc/cpu.h

   1/*
   2 * OpenRISC virtual CPU header.
   3 *
   4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef CPU_OPENRISC_H
  21#define CPU_OPENRISC_H
  22
  23#define TARGET_LONG_BITS 32
  24#define ELF_MACHINE    EM_OPENRISC
  25
  26#define CPUArchState struct CPUOpenRISCState
  27
  28/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl.  */
  29struct OpenRISCCPU;
  30
  31#include "config.h"
  32#include "qemu-common.h"
  33#include "cpu-defs.h"
  34#include "softfloat.h"
  35#include "qemu/cpu.h"
  36#include "error.h"
  37
  38#define TYPE_OPENRISC_CPU "or32-cpu"
  39
  40#define OPENRISC_CPU_CLASS(klass) \
  41    OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
  42#define OPENRISC_CPU(obj) \
  43    OBJECT_CHECK(OpenRISCCPU, (obj), TYPE_OPENRISC_CPU)
  44#define OPENRISC_CPU_GET_CLASS(obj) \
  45    OBJECT_GET_CLASS(OpenRISCCPUClass, (obj), TYPE_OPENRISC_CPU)
  46
  47/**
  48 * OpenRISCCPUClass:
  49 * @parent_reset: The parent class' reset handler.
  50 *
  51 * A OpenRISC CPU model.
  52 */
  53typedef struct OpenRISCCPUClass {
  54    /*< private >*/
  55    CPUClass parent_class;
  56    /*< public >*/
  57
  58    void (*parent_reset)(CPUState *cpu);
  59} OpenRISCCPUClass;
  60
  61#define NB_MMU_MODES    3
  62
  63enum {
  64    MMU_NOMMU_IDX = 0,
  65    MMU_SUPERVISOR_IDX = 1,
  66    MMU_USER_IDX = 2,
  67};
  68
  69#define TARGET_PAGE_BITS 13
  70
  71#define TARGET_PHYS_ADDR_SPACE_BITS 32
  72#define TARGET_VIRT_ADDR_SPACE_BITS 32
  73
  74#define SET_FP_CAUSE(reg, v)    do {\
  75                                    (reg) = ((reg) & ~(0x3f << 12)) | \
  76                                            ((v & 0x3f) << 12);\
  77                                } while (0)
  78#define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  79#define UPDATE_FP_FLAGS(reg, v)   do {\
  80                                      (reg) |= ((v & 0x1f) << 2);\
  81                                  } while (0)
  82
  83/* Version Register */
  84#define SPR_VR 0xFFFF003F
  85
  86/* Internal flags, delay slot flag */
  87#define D_FLAG    1
  88
  89/* Interrupt */
  90#define NR_IRQS  32
  91
  92/* Unit presece register */
  93enum {
  94    UPR_UP = (1 << 0),
  95    UPR_DCP = (1 << 1),
  96    UPR_ICP = (1 << 2),
  97    UPR_DMP = (1 << 3),
  98    UPR_IMP = (1 << 4),
  99    UPR_MP = (1 << 5),
 100    UPR_DUP = (1 << 6),
 101    UPR_PCUR = (1 << 7),
 102    UPR_PMP = (1 << 8),
 103    UPR_PICP = (1 << 9),
 104    UPR_TTP = (1 << 10),
 105    UPR_CUP = (255 << 24),
 106};
 107
 108/* CPU configure register */
 109enum {
 110    CPUCFGR_NSGF = (15 << 0),
 111    CPUCFGR_CGF = (1 << 4),
 112    CPUCFGR_OB32S = (1 << 5),
 113    CPUCFGR_OB64S = (1 << 6),
 114    CPUCFGR_OF32S = (1 << 7),
 115    CPUCFGR_OF64S = (1 << 8),
 116    CPUCFGR_OV64S = (1 << 9),
 117};
 118
 119/* DMMU configure register */
 120enum {
 121    DMMUCFGR_NTW = (3 << 0),
 122    DMMUCFGR_NTS = (7 << 2),
 123    DMMUCFGR_NAE = (7 << 5),
 124    DMMUCFGR_CRI = (1 << 8),
 125    DMMUCFGR_PRI = (1 << 9),
 126    DMMUCFGR_TEIRI = (1 << 10),
 127    DMMUCFGR_HTR = (1 << 11),
 128};
 129
 130/* IMMU configure register */
 131enum {
 132    IMMUCFGR_NTW = (3 << 0),
 133    IMMUCFGR_NTS = (7 << 2),
 134    IMMUCFGR_NAE = (7 << 5),
 135    IMMUCFGR_CRI = (1 << 8),
 136    IMMUCFGR_PRI = (1 << 9),
 137    IMMUCFGR_TEIRI = (1 << 10),
 138    IMMUCFGR_HTR = (1 << 11),
 139};
 140
 141/* Float point control status register */
 142enum {
 143    FPCSR_FPEE = 1,
 144    FPCSR_RM = (3 << 1),
 145    FPCSR_OVF = (1 << 3),
 146    FPCSR_UNF = (1 << 4),
 147    FPCSR_SNF = (1 << 5),
 148    FPCSR_QNF = (1 << 6),
 149    FPCSR_ZF = (1 << 7),
 150    FPCSR_IXF = (1 << 8),
 151    FPCSR_IVF = (1 << 9),
 152    FPCSR_INF = (1 << 10),
 153    FPCSR_DZF = (1 << 11),
 154};
 155
 156/* Exceptions indices */
 157enum {
 158    EXCP_RESET    = 0x1,
 159    EXCP_BUSERR   = 0x2,
 160    EXCP_DPF      = 0x3,
 161    EXCP_IPF      = 0x4,
 162    EXCP_TICK     = 0x5,
 163    EXCP_ALIGN    = 0x6,
 164    EXCP_ILLEGAL  = 0x7,
 165    EXCP_INT      = 0x8,
 166    EXCP_DTLBMISS = 0x9,
 167    EXCP_ITLBMISS = 0xa,
 168    EXCP_RANGE    = 0xb,
 169    EXCP_SYSCALL  = 0xc,
 170    EXCP_FPE      = 0xd,
 171    EXCP_TRAP     = 0xe,
 172    EXCP_NR,
 173};
 174
 175/* Supervisor register */
 176enum {
 177    SR_SM = (1 << 0),
 178    SR_TEE = (1 << 1),
 179    SR_IEE = (1 << 2),
 180    SR_DCE = (1 << 3),
 181    SR_ICE = (1 << 4),
 182    SR_DME = (1 << 5),
 183    SR_IME = (1 << 6),
 184    SR_LEE = (1 << 7),
 185    SR_CE  = (1 << 8),
 186    SR_F   = (1 << 9),
 187    SR_CY  = (1 << 10),
 188    SR_OV  = (1 << 11),
 189    SR_OVE = (1 << 12),
 190    SR_DSX = (1 << 13),
 191    SR_EPH = (1 << 14),
 192    SR_FO  = (1 << 15),
 193    SR_SUMRA = (1 << 16),
 194    SR_SCE = (1 << 17),
 195};
 196
 197/* OpenRISC Hardware Capabilities */
 198enum {
 199    OPENRISC_FEATURE_NSGF = (15 << 0),
 200    OPENRISC_FEATURE_CGF = (1 << 4),
 201    OPENRISC_FEATURE_OB32S = (1 << 5),
 202    OPENRISC_FEATURE_OB64S = (1 << 6),
 203    OPENRISC_FEATURE_OF32S = (1 << 7),
 204    OPENRISC_FEATURE_OF64S = (1 << 8),
 205    OPENRISC_FEATURE_OV64S = (1 << 9),
 206};
 207
 208/* Tick Timer Mode Register */
 209enum {
 210    TTMR_TP = (0xfffffff),
 211    TTMR_IP = (1 << 28),
 212    TTMR_IE = (1 << 29),
 213    TTMR_M  = (3 << 30),
 214};
 215
 216/* Timer Mode */
 217enum {
 218    TIMER_NONE = (0 << 30),
 219    TIMER_INTR = (1 << 30),
 220    TIMER_SHOT = (2 << 30),
 221    TIMER_CONT = (3 << 30),
 222};
 223
 224/* TLB size */
 225enum {
 226    DTLB_WAYS = 1,
 227    DTLB_SIZE = 64,
 228    DTLB_MASK = (DTLB_SIZE-1),
 229    ITLB_WAYS = 1,
 230    ITLB_SIZE = 64,
 231    ITLB_MASK = (ITLB_SIZE-1),
 232};
 233
 234/* TLB prot */
 235enum {
 236    URE = (1 << 6),
 237    UWE = (1 << 7),
 238    SRE = (1 << 8),
 239    SWE = (1 << 9),
 240
 241    SXE = (1 << 6),
 242    UXE = (1 << 7),
 243};
 244
 245/* check if tlb available */
 246enum {
 247    TLBRET_INVALID = -3,
 248    TLBRET_NOMATCH = -2,
 249    TLBRET_BADADDR = -1,
 250    TLBRET_MATCH = 0
 251};
 252
 253typedef struct OpenRISCTLBEntry {
 254    uint32_t mr;
 255    uint32_t tr;
 256} OpenRISCTLBEntry;
 257
 258#ifndef CONFIG_USER_ONLY
 259typedef struct CPUOpenRISCTLBContext {
 260    OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
 261    OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
 262
 263    int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
 264                                         hwaddr *physical,
 265                                         int *prot,
 266                                         target_ulong address, int rw);
 267    int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu,
 268                                         hwaddr *physical,
 269                                         int *prot,
 270                                         target_ulong address, int rw);
 271} CPUOpenRISCTLBContext;
 272#endif
 273
 274typedef struct CPUOpenRISCState {
 275    target_ulong gpr[32];     /* General registers */
 276    target_ulong pc;          /* Program counter */
 277    target_ulong npc;         /* Next PC */
 278    target_ulong ppc;         /* Prev PC */
 279    target_ulong jmp_pc;      /* Jump PC */
 280
 281    target_ulong machi;       /* Multiply register MACHI */
 282    target_ulong maclo;       /* Multiply register MACLO */
 283
 284    target_ulong fpmaddhi;    /* Multiply and add float register FPMADDHI */
 285    target_ulong fpmaddlo;    /* Multiply and add float register FPMADDLO */
 286
 287    target_ulong epcr;        /* Exception PC register */
 288    target_ulong eear;        /* Exception EA register */
 289
 290    uint32_t sr;              /* Supervisor register */
 291    uint32_t vr;              /* Version register */
 292    uint32_t upr;             /* Unit presence register */
 293    uint32_t cpucfgr;         /* CPU configure register */
 294    uint32_t dmmucfgr;        /* DMMU configure register */
 295    uint32_t immucfgr;        /* IMMU configure register */
 296    uint32_t esr;             /* Exception supervisor register */
 297    uint32_t fpcsr;           /* Float register */
 298    float_status fp_status;
 299
 300    uint32_t flags;           /* cpu_flags, we only use it for exception
 301                                 in solt so far.  */
 302    uint32_t btaken;          /* the SR_F bit */
 303
 304    CPU_COMMON
 305
 306#ifndef CONFIG_USER_ONLY
 307    CPUOpenRISCTLBContext * tlb;
 308
 309    struct QEMUTimer *timer;
 310    uint32_t ttmr;          /* Timer tick mode register */
 311    uint32_t ttcr;          /* Timer tick count register */
 312
 313    uint32_t picmr;         /* Interrupt mask register */
 314    uint32_t picsr;         /* Interrupt contrl register*/
 315#endif
 316    void *irq[32];          /* Interrupt irq input */
 317} CPUOpenRISCState;
 318
 319/**
 320 * OpenRISCCPU:
 321 * @env: #CPUOpenRISCState
 322 *
 323 * A OpenRISC CPU.
 324 */
 325typedef struct OpenRISCCPU {
 326    /*< private >*/
 327    CPUState parent_obj;
 328    /*< public >*/
 329
 330    CPUOpenRISCState env;
 331
 332    uint32_t feature;       /* CPU Capabilities */
 333} OpenRISCCPU;
 334
 335static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
 336{
 337    return OPENRISC_CPU(container_of(env, OpenRISCCPU, env));
 338}
 339
 340#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
 341
 342OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
 343void openrisc_cpu_realize(Object *obj, Error **errp);
 344
 345void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
 346int cpu_openrisc_exec(CPUOpenRISCState *s);
 347void do_interrupt(CPUOpenRISCState *env);
 348void openrisc_translate_init(void);
 349int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 350                                  target_ulong address,
 351                                  int rw, int mmu_idx);
 352int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
 353
 354#define cpu_list cpu_openrisc_list
 355#define cpu_exec cpu_openrisc_exec
 356#define cpu_gen_code cpu_openrisc_gen_code
 357#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
 358#define cpu_signal_handler cpu_openrisc_signal_handler
 359
 360#ifndef CONFIG_USER_ONLY
 361/* hw/openrisc_pic.c */
 362void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 363
 364/* hw/openrisc_timer.c */
 365void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
 366void cpu_openrisc_count_update(OpenRISCCPU *cpu);
 367void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 368void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 369
 370void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
 371int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
 372                                hwaddr *physical,
 373                                int *prot, target_ulong address, int rw);
 374int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
 375                               hwaddr *physical,
 376                               int *prot, target_ulong address, int rw);
 377int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
 378                               hwaddr *physical,
 379                               int *prot, target_ulong address, int rw);
 380#endif
 381
 382static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
 383{
 384    OpenRISCCPU *cpu = cpu_openrisc_init(cpu_model);
 385    if (cpu) {
 386        return &cpu->env;
 387    }
 388    return NULL;
 389}
 390
 391#if defined(CONFIG_USER_ONLY)
 392static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
 393{
 394    if (newsp) {
 395        env->gpr[1] = newsp;
 396    }
 397    env->gpr[2] = 0;
 398}
 399#endif
 400
 401#include "cpu-all.h"
 402
 403static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
 404                                        target_ulong *pc,
 405                                        target_ulong *cs_base, int *flags)
 406{
 407    *pc = env->pc;
 408    *cs_base = 0;
 409    /* D_FLAG -- branch instruction exception */
 410    *flags = (env->flags & D_FLAG);
 411}
 412
 413static inline int cpu_mmu_index(CPUOpenRISCState *env)
 414{
 415    if (!(env->sr & SR_IME)) {
 416        return MMU_NOMMU_IDX;
 417    }
 418    return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
 419}
 420
 421#define CPU_INTERRUPT_TIMER   CPU_INTERRUPT_TGT_INT_0
 422static inline bool cpu_has_work(CPUState *cpu)
 423{
 424    CPUOpenRISCState *env = &OPENRISC_CPU(cpu)->env;
 425
 426    return env->interrupt_request & (CPU_INTERRUPT_HARD |
 427                                     CPU_INTERRUPT_TIMER);
 428}
 429
 430#include "exec-all.h"
 431
 432static inline target_ulong cpu_get_pc(CPUOpenRISCState *env)
 433{
 434    return env->pc;
 435}
 436
 437static inline void cpu_pc_from_tb(CPUOpenRISCState *env, TranslationBlock *tb)
 438{
 439    env->pc = tb->pc;
 440}
 441
 442#endif /* CPU_OPENRISC_H */
 443