qemu/hw/acpi_piix4.c
<<
>>
Prefs
   1/*
   2 * ACPI implementation
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License version 2 as published by the Free Software Foundation.
   9 *
  10 * This library is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * Lesser General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU Lesser General Public
  16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17 *
  18 * Contributions after 2012-01-13 are licensed under the terms of the
  19 * GNU GPL, version 2 or (at your option) any later version.
  20 */
  21#include "hw.h"
  22#include "pc.h"
  23#include "apm.h"
  24#include "pm_smbus.h"
  25#include "pci.h"
  26#include "acpi.h"
  27#include "sysemu.h"
  28#include "range.h"
  29#include "ioport.h"
  30#include "fw_cfg.h"
  31
  32//#define DEBUG
  33
  34#ifdef DEBUG
  35# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  36#else
  37# define PIIX4_DPRINTF(format, ...)     do { } while (0)
  38#endif
  39
  40#define ACPI_DBG_IO_ADDR  0xb044
  41
  42#define GPE_BASE 0xafe0
  43#define GPE_LEN 4
  44#define PCI_UP_BASE 0xae00
  45#define PCI_DOWN_BASE 0xae04
  46#define PCI_EJ_BASE 0xae08
  47#define PCI_RMV_BASE 0xae0c
  48
  49#define PIIX4_PCI_HOTPLUG_STATUS 2
  50
  51struct pci_status {
  52    uint32_t up; /* deprecated, maintained for migration compatibility */
  53    uint32_t down;
  54};
  55
  56typedef struct PIIX4PMState {
  57    PCIDevice dev;
  58    IORange ioport;
  59    ACPIREGS ar;
  60
  61    APMState apm;
  62
  63    PMSMBus smb;
  64    uint32_t smb_io_base;
  65
  66    qemu_irq irq;
  67    qemu_irq smi_irq;
  68    int kvm_enabled;
  69    Notifier machine_ready;
  70    Notifier powerdown_notifier;
  71
  72    /* for pci hotplug */
  73    struct pci_status pci0_status;
  74    uint32_t pci0_hotplug_enable;
  75    uint32_t pci0_slot_device_present;
  76
  77    uint8_t disable_s3;
  78    uint8_t disable_s4;
  79    uint8_t s4_val;
  80} PIIX4PMState;
  81
  82static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  83
  84#define ACPI_ENABLE 0xf1
  85#define ACPI_DISABLE 0xf0
  86
  87static void pm_update_sci(PIIX4PMState *s)
  88{
  89    int sci_level, pmsts;
  90
  91    pmsts = acpi_pm1_evt_get_sts(&s->ar);
  92    sci_level = (((pmsts & s->ar.pm1.evt.en) &
  93                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
  94                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
  95                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  96                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  97        (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
  98          & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  99
 100    qemu_set_irq(s->irq, sci_level);
 101    /* schedule a timer interruption if needed */
 102    acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 103                       !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 104}
 105
 106static void pm_tmr_timer(ACPIREGS *ar)
 107{
 108    PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 109    pm_update_sci(s);
 110}
 111
 112static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 113                            uint64_t val)
 114{
 115    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 116
 117    if (width != 2) {
 118        PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 119                      (unsigned)addr, width, (unsigned)val);
 120    }
 121
 122    switch(addr) {
 123    case 0x00:
 124        acpi_pm1_evt_write_sts(&s->ar, val);
 125        pm_update_sci(s);
 126        break;
 127    case 0x02:
 128        acpi_pm1_evt_write_en(&s->ar, val);
 129        pm_update_sci(s);
 130        break;
 131    case 0x04:
 132        acpi_pm1_cnt_write(&s->ar, val, s->s4_val);
 133        break;
 134    default:
 135        break;
 136    }
 137    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 138                  (unsigned int)val);
 139}
 140
 141static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 142                            uint64_t *data)
 143{
 144    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 145    uint32_t val;
 146
 147    switch(addr) {
 148    case 0x00:
 149        val = acpi_pm1_evt_get_sts(&s->ar);
 150        break;
 151    case 0x02:
 152        val = s->ar.pm1.evt.en;
 153        break;
 154    case 0x04:
 155        val = s->ar.pm1.cnt.cnt;
 156        break;
 157    case 0x08:
 158        val = acpi_pm_tmr_get(&s->ar);
 159        break;
 160    default:
 161        val = 0;
 162        break;
 163    }
 164    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 165    *data = val;
 166}
 167
 168static const IORangeOps pm_iorange_ops = {
 169    .read = pm_ioport_read,
 170    .write = pm_ioport_write,
 171};
 172
 173static void apm_ctrl_changed(uint32_t val, void *arg)
 174{
 175    PIIX4PMState *s = arg;
 176
 177    /* ACPI specs 3.0, 4.7.2.5 */
 178    acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 179
 180    if (s->dev.config[0x5b] & (1 << 1)) {
 181        if (s->smi_irq) {
 182            qemu_irq_raise(s->smi_irq);
 183        }
 184    }
 185}
 186
 187static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 188{
 189    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 190}
 191
 192static void pm_io_space_update(PIIX4PMState *s)
 193{
 194    uint32_t pm_io_base;
 195
 196    if (s->dev.config[0x80] & 1) {
 197        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 198        pm_io_base &= 0xffc0;
 199
 200        /* XXX: need to improve memory and ioport allocation */
 201        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 202        iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 203        ioport_register(&s->ioport);
 204    }
 205}
 206
 207static void pm_write_config(PCIDevice *d,
 208                            uint32_t address, uint32_t val, int len)
 209{
 210    pci_default_write_config(d, address, val, len);
 211    if (range_covers_byte(address, len, 0x80))
 212        pm_io_space_update((PIIX4PMState *)d);
 213}
 214
 215static void vmstate_pci_status_pre_save(void *opaque)
 216{
 217    struct pci_status *pci0_status = opaque;
 218    PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
 219
 220    /* We no longer track up, so build a safe value for migrating
 221     * to a version that still does... of course these might get lost
 222     * by an old buggy implementation, but we try. */
 223    pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 224}
 225
 226static int vmstate_acpi_post_load(void *opaque, int version_id)
 227{
 228    PIIX4PMState *s = opaque;
 229
 230    pm_io_space_update(s);
 231    return 0;
 232}
 233
 234#define VMSTATE_GPE_ARRAY(_field, _state)                            \
 235 {                                                                   \
 236     .name       = (stringify(_field)),                              \
 237     .version_id = 0,                                                \
 238     .info       = &vmstate_info_uint16,                             \
 239     .size       = sizeof(uint16_t),                                 \
 240     .flags      = VMS_SINGLE | VMS_POINTER,                         \
 241     .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 242 }
 243
 244static const VMStateDescription vmstate_gpe = {
 245    .name = "gpe",
 246    .version_id = 1,
 247    .minimum_version_id = 1,
 248    .minimum_version_id_old = 1,
 249    .fields      = (VMStateField []) {
 250        VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 251        VMSTATE_GPE_ARRAY(en, ACPIGPE),
 252        VMSTATE_END_OF_LIST()
 253    }
 254};
 255
 256static const VMStateDescription vmstate_pci_status = {
 257    .name = "pci_status",
 258    .version_id = 1,
 259    .minimum_version_id = 1,
 260    .minimum_version_id_old = 1,
 261    .pre_save = vmstate_pci_status_pre_save,
 262    .fields      = (VMStateField []) {
 263        VMSTATE_UINT32(up, struct pci_status),
 264        VMSTATE_UINT32(down, struct pci_status),
 265        VMSTATE_END_OF_LIST()
 266    }
 267};
 268
 269static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 270{
 271    PIIX4PMState *s = opaque;
 272    int ret, i;
 273    uint16_t temp;
 274
 275    ret = pci_device_load(&s->dev, f);
 276    if (ret < 0) {
 277        return ret;
 278    }
 279    qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 280    qemu_get_be16s(f, &s->ar.pm1.evt.en);
 281    qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 282
 283    ret = vmstate_load_state(f, &vmstate_apm, opaque, 1);
 284    if (ret) {
 285        return ret;
 286    }
 287
 288    qemu_get_timer(f, s->ar.tmr.timer);
 289    qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 290
 291    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 292    for (i = 0; i < 3; i++) {
 293        qemu_get_be16s(f, &temp);
 294    }
 295
 296    qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 297    for (i = 0; i < 3; i++) {
 298        qemu_get_be16s(f, &temp);
 299    }
 300
 301    ret = vmstate_load_state(f, &vmstate_pci_status, opaque, 1);
 302    return ret;
 303}
 304
 305/* qemu-kvm 1.2 uses version 3 but advertised as 2
 306 * To support incoming qemu-kvm 1.2 migration, change version_id
 307 * and minimum_version_id to 2 below (which breaks migration from
 308 * qemu 1.2).
 309 *
 310 */
 311static const VMStateDescription vmstate_acpi = {
 312    .name = "piix4_pm",
 313    .version_id = 3,
 314    .minimum_version_id = 3,
 315    .minimum_version_id_old = 1,
 316    .load_state_old = acpi_load_old,
 317    .post_load = vmstate_acpi_post_load,
 318    .fields      = (VMStateField []) {
 319        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 320        VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 321        VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 322        VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 323        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 324        VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 325        VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 326        VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 327        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 328                       struct pci_status),
 329        VMSTATE_END_OF_LIST()
 330    }
 331};
 332
 333static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
 334{
 335    BusChild *kid, *next;
 336    BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
 337    int slot = ffs(slots) - 1;
 338    bool slot_free = true;
 339
 340    /* Mark request as complete */
 341    s->pci0_status.down &= ~(1U << slot);
 342
 343    QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 344        DeviceState *qdev = kid->child;
 345        PCIDevice *dev = PCI_DEVICE(qdev);
 346        PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 347        if (PCI_SLOT(dev->devfn) == slot) {
 348            if (pc->no_hotplug) {
 349                slot_free = false;
 350            } else {
 351                qdev_free(qdev);
 352            }
 353        }
 354    }
 355    if (slot_free) {
 356        s->pci0_slot_device_present &= ~(1U << slot);
 357    }
 358}
 359
 360static void piix4_update_hotplug(PIIX4PMState *s)
 361{
 362    PCIDevice *dev = &s->dev;
 363    BusState *bus = qdev_get_parent_bus(&dev->qdev);
 364    BusChild *kid, *next;
 365
 366    /* Execute any pending removes during reset */
 367    while (s->pci0_status.down) {
 368        acpi_piix_eject_slot(s, s->pci0_status.down);
 369    }
 370
 371    s->pci0_hotplug_enable = ~0;
 372    s->pci0_slot_device_present = 0;
 373
 374    QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 375        DeviceState *qdev = kid->child;
 376        PCIDevice *pdev = PCI_DEVICE(qdev);
 377        PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 378        int slot = PCI_SLOT(pdev->devfn);
 379
 380        if (pc->no_hotplug) {
 381            s->pci0_hotplug_enable &= ~(1U << slot);
 382        }
 383
 384        s->pci0_slot_device_present |= (1U << slot);
 385    }
 386}
 387
 388static void piix4_reset(void *opaque)
 389{
 390    PIIX4PMState *s = opaque;
 391    uint8_t *pci_conf = s->dev.config;
 392
 393    pci_conf[0x58] = 0;
 394    pci_conf[0x59] = 0;
 395    pci_conf[0x5a] = 0;
 396    pci_conf[0x5b] = 0;
 397
 398    pci_conf[0x40] = 0x01; /* PM io base read only bit */
 399    pci_conf[0x80] = 0;
 400
 401    if (s->kvm_enabled) {
 402        /* Mark SMM as already inited (until KVM supports SMM). */
 403        pci_conf[0x5B] = 0x02;
 404    }
 405    piix4_update_hotplug(s);
 406}
 407
 408static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 409{
 410    PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 411
 412    assert(s != NULL);
 413    acpi_pm1_evt_power_down(&s->ar);
 414}
 415
 416static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 417{
 418    PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 419    uint8_t *pci_conf;
 420
 421    pci_conf = s->dev.config;
 422    pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 423    pci_conf[0x63] = 0x60;
 424    pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 425        (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 426
 427}
 428
 429static int piix4_pm_initfn(PCIDevice *dev)
 430{
 431    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 432    uint8_t *pci_conf;
 433
 434    pci_conf = s->dev.config;
 435    pci_conf[0x06] = 0x80;
 436    pci_conf[0x07] = 0x02;
 437    pci_conf[0x09] = 0x00;
 438    pci_conf[0x3d] = 0x01; // interrupt pin 1
 439
 440    /* APM */
 441    apm_init(&s->apm, apm_ctrl_changed, s);
 442
 443    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 444
 445    if (s->kvm_enabled) {
 446        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 447         * support SMM mode. */
 448        pci_conf[0x5B] = 0x02;
 449    }
 450
 451    /* XXX: which specification is used ? The i82731AB has different
 452       mappings */
 453    pci_conf[0x90] = s->smb_io_base | 1;
 454    pci_conf[0x91] = s->smb_io_base >> 8;
 455    pci_conf[0xd2] = 0x09;
 456    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 457    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 458
 459    acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
 460    acpi_gpe_init(&s->ar, GPE_LEN);
 461
 462    s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 463    qemu_register_powerdown_notifier(&s->powerdown_notifier);
 464
 465    pm_smbus_init(&s->dev.qdev, &s->smb);
 466    s->machine_ready.notify = piix4_pm_machine_ready;
 467    qemu_add_machine_init_done_notifier(&s->machine_ready);
 468    qemu_register_reset(piix4_reset, s);
 469    piix4_acpi_system_hot_add_init(dev->bus, s);
 470
 471    return 0;
 472}
 473
 474i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 475                       qemu_irq sci_irq, qemu_irq smi_irq,
 476                       int kvm_enabled, void *fw_cfg)
 477{
 478    PCIDevice *dev;
 479    PIIX4PMState *s;
 480
 481    dev = pci_create(bus, devfn, "PIIX4_PM");
 482    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 483
 484    s = DO_UPCAST(PIIX4PMState, dev, dev);
 485    s->irq = sci_irq;
 486    acpi_pm1_cnt_init(&s->ar);
 487    s->smi_irq = smi_irq;
 488    s->kvm_enabled = kvm_enabled;
 489
 490    qdev_init_nofail(&dev->qdev);
 491
 492    if (fw_cfg) {
 493        uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 494        suspend[3] = 1 | ((!s->disable_s3) << 7);
 495        suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 496
 497        fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 498    }
 499
 500    return s->smb.smbus;
 501}
 502
 503static Property piix4_pm_properties[] = {
 504    DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 505    DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
 506    DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
 507    DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
 508    DEFINE_PROP_END_OF_LIST(),
 509};
 510
 511static void piix4_pm_class_init(ObjectClass *klass, void *data)
 512{
 513    DeviceClass *dc = DEVICE_CLASS(klass);
 514    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 515
 516    k->no_hotplug = 1;
 517    k->init = piix4_pm_initfn;
 518    k->config_write = pm_write_config;
 519    k->vendor_id = PCI_VENDOR_ID_INTEL;
 520    k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 521    k->revision = 0x03;
 522    k->class_id = PCI_CLASS_BRIDGE_OTHER;
 523    dc->desc = "PM";
 524    dc->no_user = 1;
 525    dc->vmsd = &vmstate_acpi;
 526    dc->props = piix4_pm_properties;
 527}
 528
 529static TypeInfo piix4_pm_info = {
 530    .name          = "PIIX4_PM",
 531    .parent        = TYPE_PCI_DEVICE,
 532    .instance_size = sizeof(PIIX4PMState),
 533    .class_init    = piix4_pm_class_init,
 534};
 535
 536static void piix4_pm_register_types(void)
 537{
 538    type_register_static(&piix4_pm_info);
 539}
 540
 541type_init(piix4_pm_register_types)
 542
 543static uint32_t gpe_readb(void *opaque, uint32_t addr)
 544{
 545    PIIX4PMState *s = opaque;
 546    uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 547
 548    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 549    return val;
 550}
 551
 552static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 553{
 554    PIIX4PMState *s = opaque;
 555
 556    acpi_gpe_ioport_writeb(&s->ar, addr, val);
 557    pm_update_sci(s);
 558
 559    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 560}
 561
 562static uint32_t pci_up_read(void *opaque, uint32_t addr)
 563{
 564    PIIX4PMState *s = opaque;
 565    uint32_t val;
 566
 567    /* Manufacture an "up" value to cause a device check on any hotplug
 568     * slot with a device.  Extra device checks are harmless. */
 569    val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 570
 571    PIIX4_DPRINTF("pci_up_read %x\n", val);
 572    return val;
 573}
 574
 575static uint32_t pci_down_read(void *opaque, uint32_t addr)
 576{
 577    PIIX4PMState *s = opaque;
 578    uint32_t val = s->pci0_status.down;
 579
 580    PIIX4_DPRINTF("pci_down_read %x\n", val);
 581    return val;
 582}
 583
 584static uint32_t pci_features_read(void *opaque, uint32_t addr)
 585{
 586    /* No feature defined yet */
 587    PIIX4_DPRINTF("pci_features_read %x\n", 0);
 588    return 0;
 589}
 590
 591static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 592{
 593    acpi_piix_eject_slot(opaque, val);
 594
 595    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 596}
 597
 598static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 599{
 600    PIIX4PMState *s = opaque;
 601
 602    return s->pci0_hotplug_enable;
 603}
 604
 605static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 606                                PCIHotplugState state);
 607
 608static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 609{
 610
 611    register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 612    register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 613    acpi_gpe_blk(&s->ar, GPE_BASE);
 614
 615    register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
 616    register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
 617
 618    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
 619    register_ioport_read(PCI_EJ_BASE, 4, 4,  pci_features_read, s);
 620
 621    register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 622
 623    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 624}
 625
 626static void enable_device(PIIX4PMState *s, int slot)
 627{
 628    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 629    s->pci0_slot_device_present |= (1U << slot);
 630}
 631
 632static void disable_device(PIIX4PMState *s, int slot)
 633{
 634    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 635    s->pci0_status.down |= (1U << slot);
 636}
 637
 638static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 639                                PCIHotplugState state)
 640{
 641    int slot = PCI_SLOT(dev->devfn);
 642    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 643                                PCI_DEVICE(qdev));
 644
 645    /* Don't send event when device is enabled during qemu machine creation:
 646     * it is present on boot, no hotplug event is necessary. We do send an
 647     * event when the device is disabled later. */
 648    if (state == PCI_COLDPLUG_ENABLED) {
 649        s->pci0_slot_device_present |= (1U << slot);
 650        return 0;
 651    }
 652
 653    if (state == PCI_HOTPLUG_ENABLED) {
 654        enable_device(s, slot);
 655    } else {
 656        disable_device(s, slot);
 657    }
 658
 659    pm_update_sci(s);
 660
 661    return 0;
 662}
 663