LXR qemu/hw/pci_internals.h

   1#ifndef QEMU_PCI_INTERNALS_H
   2#define QEMU_PCI_INTERNALS_H
   3
   4/*
   5 * This header files is private to pci.c and pci_bridge.c
   6 * So following structures are opaque to others and shouldn't be
   7 * accessed.
   8 *
   9 * For pci-to-pci bridge needs to include this header file to embed
  10 * PCIBridge in its structure or to get sizeof(PCIBridge),
  11 * However, they shouldn't access those following members directly.
  12 * Use accessor function in pci.h, pci_bridge.h
  13 */
  14
  15#define TYPE_PCI_BUS "PCI"
  16#define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
  17
  18struct PCIBus {
  19    BusState qbus;
  20    PCIDMAContextFunc dma_context_fn;
  21    void *dma_context_opaque;
  22    uint8_t devfn_min;
  23    pci_set_irq_fn set_irq;
  24    pci_map_irq_fn map_irq;
  25    pci_route_irq_fn route_intx_to_irq;
  26    pci_hotplug_fn hotplug;
  27    DeviceState *hotplug_qdev;
  28    void *irq_opaque;
  29    PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
  30    PCIDevice *parent_dev;
  31    MemoryRegion *address_space_mem;
  32    MemoryRegion *address_space_io;
  33
  34    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  35    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  36
  37    /* The bus IRQ state is the logical OR of the connected devices.
  38       Keep a count of the number of devices with raised IRQs.  */
  39    int nirq;
  40    int *irq_count;
  41};
  42
  43typedef struct PCIBridgeWindows PCIBridgeWindows;
  44
  45/*
  46 * Aliases for each of the address space windows that the bridge
  47 * can forward. Mapped into the bridge's parent's address space,
  48 * as subregions.
  49 */
  50struct PCIBridgeWindows {
  51    MemoryRegion alias_pref_mem;
  52    MemoryRegion alias_mem;
  53    MemoryRegion alias_io;
  54};
  55
  56struct PCIBridge {
  57    PCIDevice dev;
  58
  59    /* private member */
  60    PCIBus sec_bus;
  61    /*
  62     * Memory regions for the bridge's address spaces.  These regions are not
  63     * directly added to system_memory/system_io or its descendants.
  64     * Bridge's secondary bus points to these, so that devices
  65     * under the bridge see these regions as its address spaces.
  66     * The regions are as large as the entire address space -
  67     * they don't take into account any windows.
  68     */
  69    MemoryRegion address_space_mem;
  70    MemoryRegion address_space_io;
  71
  72    PCIBridgeWindows *windows;
  73
  74    pci_map_irq_fn map_irq;
  75    const char *bus_name;
  76};
  77
  78#endif /* QEMU_PCI_INTERNALS_H */
  79