LXR qemu/hw/pcie.c

   1/*
   2 * pcie.c
   3 *
   4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5 *                    VA Linux Systems Japan K.K.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu-common.h"
  22#include "pci_bridge.h"
  23#include "pcie.h"
  24#include "msix.h"
  25#include "msi.h"
  26#include "pci_internals.h"
  27#include "pcie_regs.h"
  28#include "range.h"
  29
  30//#define DEBUG_PCIE
  31#ifdef DEBUG_PCIE
  32# define PCIE_DPRINTF(fmt, ...)                                         \
  33    fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  34#else
  35# define PCIE_DPRINTF(fmt, ...) do {} while (0)
  36#endif
  37#define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  38    PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  39
  40
  41/***************************************************************************
  42 * pci express capability helper functions
  43 */
  44int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  45{
  46    int pos;
  47    uint8_t *exp_cap;
  48
  49    assert(pci_is_express(dev));
  50
  51    pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  52                                 PCI_EXP_VER2_SIZEOF);
  53    if (pos < 0) {
  54        return pos;
  55    }
  56    dev->exp.exp_cap = pos;
  57    exp_cap = dev->config + pos;
  58
  59    /* capability register
  60       interrupt message number defaults to 0 */
  61    pci_set_word(exp_cap + PCI_EXP_FLAGS,
  62                 ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  63                 PCI_EXP_FLAGS_VER2);
  64
  65    /* device capability register
  66     * table 7-12:
  67     * roll based error reporting bit must be set by all
  68     * Functions conforming to the ECN, PCI Express Base
  69     * Specification, Revision 1.1., or subsequent PCI Express Base
  70     * Specification revisions.
  71     */
  72    pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  73
  74    pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  75                 (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  76                 PCI_EXP_LNKCAP_ASPMS_0S |
  77                 PCI_EXP_LNK_MLW_1 |
  78                 PCI_EXP_LNK_LS_25);
  79
  80    pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  81                 PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  82
  83    pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  84                 PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  85
  86    pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  87    return pos;
  88}
  89
  90void pcie_cap_exit(PCIDevice *dev)
  91{
  92    pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
  93}
  94
  95uint8_t pcie_cap_get_type(const PCIDevice *dev)
  96{
  97    uint32_t pos = dev->exp.exp_cap;
  98    assert(pos > 0);
  99    return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 100            PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 101}
 102
 103/* MSI/MSI-X */
 104/* pci express interrupt message number */
 105/* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 106void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 107{
 108    uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 109    assert(vector < 32);
 110    pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 111    pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 112                               vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 113}
 114
 115uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 116{
 117    return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 118            PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 119}
 120
 121void pcie_cap_deverr_init(PCIDevice *dev)
 122{
 123    uint32_t pos = dev->exp.exp_cap;
 124    pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 125                               PCI_EXP_DEVCAP_RBER);
 126    pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 127                               PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 128                               PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 129    pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 130                               PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 131                               PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 132}
 133
 134void pcie_cap_deverr_reset(PCIDevice *dev)
 135{
 136    uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 137    pci_long_test_and_clear_mask(devctl,
 138                                 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 139                                 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 140}
 141
 142static void hotplug_event_update_event_status(PCIDevice *dev)
 143{
 144    uint32_t pos = dev->exp.exp_cap;
 145    uint8_t *exp_cap = dev->config + pos;
 146    uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 147    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 148
 149    dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 150        (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 151}
 152
 153static void hotplug_event_notify(PCIDevice *dev)
 154{
 155    bool prev = dev->exp.hpev_notified;
 156
 157    hotplug_event_update_event_status(dev);
 158
 159    if (prev == dev->exp.hpev_notified) {
 160        return;
 161    }
 162
 163    /* Note: the logic above does not take into account whether interrupts
 164     * are masked. The result is that interrupt will be sent when it is
 165     * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 166     * The Port may optionally send an MSI when there are hot-plug events that
 167     * occur while interrupt generation is disabled, and interrupt generation is
 168     * subsequently enabled. */
 169    if (msix_enabled(dev)) {
 170        msix_notify(dev, pcie_cap_flags_get_vector(dev));
 171    } else if (msi_enabled(dev)) {
 172        msi_notify(dev, pcie_cap_flags_get_vector(dev));
 173    } else {
 174        qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
 175    }
 176}
 177
 178static void hotplug_event_clear(PCIDevice *dev)
 179{
 180    hotplug_event_update_event_status(dev);
 181    if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
 182        qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
 183    }
 184}
 185
 186/*
 187 * A PCI Express Hot-Plug Event has occurred, so update slot status register
 188 * and notify OS of the event if necessary.
 189 *
 190 * 6.7.3 PCI Express Hot-Plug Events
 191 * 6.7.3.4 Software Notification of Hot-Plug Events
 192 */
 193static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 194{
 195    /* Minor optimization: if nothing changed - no event is needed. */
 196    if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 197                                   PCI_EXP_SLTSTA, event)) {
 198        return;
 199    }
 200    hotplug_event_notify(dev);
 201}
 202
 203static int pcie_cap_slot_hotplug(DeviceState *qdev,
 204                                 PCIDevice *pci_dev, PCIHotplugState state)
 205{
 206    PCIDevice *d = PCI_DEVICE(qdev);
 207    uint8_t *exp_cap = d->config + d->exp.exp_cap;
 208    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 209
 210    /* Don't send event when device is enabled during qemu machine creation:
 211     * it is present on boot, no hotplug event is necessary. We do send an
 212     * event when the device is disabled later. */
 213    if (state == PCI_COLDPLUG_ENABLED) {
 214        pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 215                                   PCI_EXP_SLTSTA_PDS);
 216        return 0;
 217    }
 218
 219    PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 220    if (sltsta & PCI_EXP_SLTSTA_EIS) {
 221        /* the slot is electromechanically locked.
 222         * This error is propagated up to qdev and then to HMP/QMP.
 223         */
 224        return -EBUSY;
 225    }
 226
 227    /* TODO: multifunction hot-plug.
 228     * Right now, only a device of function = 0 is allowed to be
 229     * hot plugged/unplugged.
 230     */
 231    assert(PCI_FUNC(pci_dev->devfn) == 0);
 232
 233    if (state == PCI_HOTPLUG_ENABLED) {
 234        pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 235                                   PCI_EXP_SLTSTA_PDS);
 236        pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 237    } else {
 238        qdev_free(&pci_dev->qdev);
 239        pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 240                                     PCI_EXP_SLTSTA_PDS);
 241        pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 242    }
 243    return 0;
 244}
 245
 246/* pci express slot for pci express root/downstream port
 247   PCI express capability slot registers */
 248void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 249{
 250    uint32_t pos = dev->exp.exp_cap;
 251
 252    pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 253                               PCI_EXP_FLAGS_SLOT);
 254
 255    pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 256                                 ~PCI_EXP_SLTCAP_PSN);
 257    pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 258                               (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 259                               PCI_EXP_SLTCAP_EIP |
 260                               PCI_EXP_SLTCAP_HPS |
 261                               PCI_EXP_SLTCAP_HPC |
 262                               PCI_EXP_SLTCAP_PIP |
 263                               PCI_EXP_SLTCAP_AIP |
 264                               PCI_EXP_SLTCAP_ABP);
 265
 266    pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 267                                 PCI_EXP_SLTCTL_PIC |
 268                                 PCI_EXP_SLTCTL_AIC);
 269    pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 270                               PCI_EXP_SLTCTL_PIC_OFF |
 271                               PCI_EXP_SLTCTL_AIC_OFF);
 272    pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 273                               PCI_EXP_SLTCTL_PIC |
 274                               PCI_EXP_SLTCTL_AIC |
 275                               PCI_EXP_SLTCTL_HPIE |
 276                               PCI_EXP_SLTCTL_CCIE |
 277                               PCI_EXP_SLTCTL_PDCE |
 278                               PCI_EXP_SLTCTL_ABPE);
 279    /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 280     * make the bit writable here in order to detect 1b is written.
 281     * pcie_cap_slot_write_config() test-and-clear the bit, so
 282     * this bit always returns 0 to the guest.
 283     */
 284    pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 285                               PCI_EXP_SLTCTL_EIC);
 286
 287    pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 288                               PCI_EXP_HP_EV_SUPPORTED);
 289
 290    dev->exp.hpev_notified = false;
 291
 292    pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 293                    pcie_cap_slot_hotplug, &dev->qdev);
 294}
 295
 296void pcie_cap_slot_reset(PCIDevice *dev)
 297{
 298    uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 299
 300    PCIE_DEV_PRINTF(dev, "reset\n");
 301
 302    pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 303                                 PCI_EXP_SLTCTL_EIC |
 304                                 PCI_EXP_SLTCTL_PIC |
 305                                 PCI_EXP_SLTCTL_AIC |
 306                                 PCI_EXP_SLTCTL_HPIE |
 307                                 PCI_EXP_SLTCTL_CCIE |
 308                                 PCI_EXP_SLTCTL_PDCE |
 309                                 PCI_EXP_SLTCTL_ABPE);
 310    pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 311                               PCI_EXP_SLTCTL_PIC_OFF |
 312                               PCI_EXP_SLTCTL_AIC_OFF);
 313
 314    pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 315                                 PCI_EXP_SLTSTA_EIS |/* on reset,
 316                                                        the lock is released */
 317                                 PCI_EXP_SLTSTA_CC |
 318                                 PCI_EXP_SLTSTA_PDC |
 319                                 PCI_EXP_SLTSTA_ABP);
 320
 321    hotplug_event_update_event_status(dev);
 322}
 323
 324void pcie_cap_slot_write_config(PCIDevice *dev,
 325                                uint32_t addr, uint32_t val, int len)
 326{
 327    uint32_t pos = dev->exp.exp_cap;
 328    uint8_t *exp_cap = dev->config + pos;
 329    uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 330
 331    if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
 332        hotplug_event_clear(dev);
 333    }
 334
 335    if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 336        return;
 337    }
 338
 339    if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 340                                     PCI_EXP_SLTCTL_EIC)) {
 341        sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 342        pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 343        PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 344                        "sltsta -> 0x%02"PRIx16"\n",
 345                        sltsta);
 346    }
 347
 348    hotplug_event_notify(dev);
 349
 350    /* 
 351     * 6.7.3.2 Command Completed Events
 352     *
 353     * Software issues a command to a hot-plug capable Downstream Port by
 354     * issuing a write transaction that targets any portion of the Port’s Slot
 355     * Control register. A single write to the Slot Control register is
 356     * considered to be a single command, even if the write affects more than
 357     * one field in the Slot Control register. In response to this transaction,
 358     * the Port must carry out the requested actions and then set the
 359     * associated status field for the command completed event. */
 360
 361    /* Real hardware might take a while to complete requested command because
 362     * physical movement would be involved like locking the electromechanical
 363     * lock.  However in our case, command is completed instantaneously above,
 364     * so send a command completion event right now.
 365     */
 366    pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 367}
 368
 369int pcie_cap_slot_post_load(void *opaque, int version_id)
 370{
 371    PCIDevice *dev = opaque;
 372    hotplug_event_update_event_status(dev);
 373    return 0;
 374}
 375
 376void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 377{
 378    pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 379}
 380
 381/* root control/capabilities/status. PME isn't emulated for now */
 382void pcie_cap_root_init(PCIDevice *dev)
 383{
 384    pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 385                 PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 386                 PCI_EXP_RTCTL_SEFEE);
 387}
 388
 389void pcie_cap_root_reset(PCIDevice *dev)
 390{
 391    pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 392}
 393
 394/* function level reset(FLR) */
 395void pcie_cap_flr_init(PCIDevice *dev)
 396{
 397    pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 398                               PCI_EXP_DEVCAP_FLR);
 399
 400    /* Although reading BCR_FLR returns always 0,
 401     * the bit is made writable here in order to detect the 1b is written
 402     * pcie_cap_flr_write_config() test-and-clear the bit, so
 403     * this bit always returns 0 to the guest.
 404     */
 405    pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 406                               PCI_EXP_DEVCTL_BCR_FLR);
 407}
 408
 409void pcie_cap_flr_write_config(PCIDevice *dev,
 410                               uint32_t addr, uint32_t val, int len)
 411{
 412    uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 413    if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
 414        /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
 415           so the handler can detect FLR by looking at this bit. */
 416        pci_device_reset(dev);
 417        pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
 418    }
 419}
 420
 421/* Alternative Routing-ID Interpretation (ARI) */
 422/* ari forwarding support for down stream port */
 423void pcie_cap_ari_init(PCIDevice *dev)
 424{
 425    uint32_t pos = dev->exp.exp_cap;
 426    pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 427                               PCI_EXP_DEVCAP2_ARI);
 428    pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 429                               PCI_EXP_DEVCTL2_ARI);
 430}
 431
 432void pcie_cap_ari_reset(PCIDevice *dev)
 433{
 434    uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 435    pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 436}
 437
 438bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 439{
 440    if (!pci_is_express(dev)) {
 441        return false;
 442    }
 443    if (!dev->exp.exp_cap) {
 444        return false;
 445    }
 446
 447    return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 448        PCI_EXP_DEVCTL2_ARI;
 449}
 450
 451/**************************************************************************
 452 * pci express extended capability allocation functions
 453 * uint16_t ext_cap_id (16 bit)
 454 * uint8_t cap_ver (4 bit)
 455 * uint16_t cap_offset (12 bit)
 456 * uint16_t ext_cap_size
 457 */
 458
 459static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 460                                          uint16_t *prev_p)
 461{
 462    uint16_t prev = 0;
 463    uint16_t next;
 464    uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 465
 466    if (!header) {
 467        /* no extended capability */
 468        next = 0;
 469        goto out;
 470    }
 471    for (next = PCI_CONFIG_SPACE_SIZE; next;
 472         prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 473
 474        assert(next >= PCI_CONFIG_SPACE_SIZE);
 475        assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 476
 477        header = pci_get_long(dev->config + next);
 478        if (PCI_EXT_CAP_ID(header) == cap_id) {
 479            break;
 480        }
 481    }
 482
 483out:
 484    if (prev_p) {
 485        *prev_p = prev;
 486    }
 487    return next;
 488}
 489
 490uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 491{
 492    return pcie_find_capability_list(dev, cap_id, NULL);
 493}
 494
 495static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 496{
 497    uint16_t header = pci_get_long(dev->config + pos);
 498    assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 499    header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 500        ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 501    pci_set_long(dev->config + pos, header);
 502}
 503
 504/*
 505 * caller must supply valid (offset, size) * such that the range shouldn't
 506 * overlap with other capability or other registers.
 507 * This function doesn't check it.
 508 */
 509void pcie_add_capability(PCIDevice *dev,
 510                         uint16_t cap_id, uint8_t cap_ver,
 511                         uint16_t offset, uint16_t size)
 512{
 513    uint32_t header;
 514    uint16_t next;
 515
 516    assert(offset >= PCI_CONFIG_SPACE_SIZE);
 517    assert(offset < offset + size);
 518    assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 519    assert(size >= 8);
 520    assert(pci_is_express(dev));
 521
 522    if (offset == PCI_CONFIG_SPACE_SIZE) {
 523        header = pci_get_long(dev->config + offset);
 524        next = PCI_EXT_CAP_NEXT(header);
 525    } else {
 526        uint16_t prev;
 527
 528        /* 0 is reserved cap id. use internally to find the last capability
 529           in the linked list */
 530        next = pcie_find_capability_list(dev, 0, &prev);
 531
 532        assert(prev >= PCI_CONFIG_SPACE_SIZE);
 533        assert(next == 0);
 534        pcie_ext_cap_set_next(dev, prev, offset);
 535    }
 536    pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 537
 538    /* Make capability read-only by default */
 539    memset(dev->wmask + offset, 0, size);
 540    memset(dev->w1cmask + offset, 0, size);
 541    /* Check capability by default */
 542    memset(dev->cmask + offset, 0xFF, size);
 543}
 544
 545/**************************************************************************
 546 * pci express extended capability helper functions
 547 */
 548
 549/* ARI */
 550void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 551{
 552    pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 553                        offset, PCI_ARI_SIZEOF);
 554    pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 555}
 556