LXR qemu/target-m68k/cpu.h

   1/*
   2 * m68k virtual CPU header
   3 *
   4 *  Copyright (c) 2005-2007 CodeSourcery
   5 *  Written by Paul Brook
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#ifndef CPU_M68K_H
  21#define CPU_M68K_H
  22
  23#define TARGET_LONG_BITS 32
  24
  25#define CPUArchState struct CPUM68KState
  26
  27#include "config.h"
  28#include "qemu-common.h"
  29#include "cpu-defs.h"
  30
  31#include "softfloat.h"
  32
  33#define MAX_QREGS 32
  34
  35#define TARGET_HAS_ICE 1
  36
  37#define ELF_MACHINE     EM_68K
  38
  39#define EXCP_ACCESS         2   /* Access (MMU) error.  */
  40#define EXCP_ADDRESS        3   /* Address error.  */
  41#define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  42#define EXCP_DIV0           5   /* Divide by zero */
  43#define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  44#define EXCP_TRACE          9
  45#define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  46#define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  47#define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  48#define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  49#define EXCP_FORMAT         14  /* RTE format error.  */
  50#define EXCP_UNINITIALIZED  15
  51#define EXCP_TRAP0          32   /* User trap #0.  */
  52#define EXCP_TRAP15         47   /* User trap #15.  */
  53#define EXCP_UNSUPPORTED    61
  54#define EXCP_ICE            13
  55
  56#define EXCP_RTE            0x100
  57#define EXCP_HALT_INSN      0x101
  58
  59#define NB_MMU_MODES 2
  60
  61typedef struct CPUM68KState {
  62    uint32_t dregs[8];
  63    uint32_t aregs[8];
  64    uint32_t pc;
  65    uint32_t sr;
  66
  67    /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  68    int current_sp;
  69    uint32_t sp[2];
  70
  71    /* Condition flags.  */
  72    uint32_t cc_op;
  73    uint32_t cc_dest;
  74    uint32_t cc_src;
  75    uint32_t cc_x;
  76
  77    float64 fregs[8];
  78    float64 fp_result;
  79    uint32_t fpcr;
  80    uint32_t fpsr;
  81    float_status fp_status;
  82
  83    uint64_t mactmp;
  84    /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
  85       two 8-bit parts.  We store a single 64-bit value and
  86       rearrange/extend this when changing modes.  */
  87    uint64_t macc[4];
  88    uint32_t macsr;
  89    uint32_t mac_mask;
  90
  91    /* Temporary storage for DIV helpers.  */
  92    uint32_t div1;
  93    uint32_t div2;
  94
  95    /* MMU status.  */
  96    struct {
  97        uint32_t ar;
  98    } mmu;
  99
 100    /* Control registers.  */
 101    uint32_t vbr;
 102    uint32_t mbar;
 103    uint32_t rambar0;
 104    uint32_t cacr;
 105
 106    /* ??? remove this.  */
 107    uint32_t t1;
 108
 109    int pending_vector;
 110    int pending_level;
 111
 112    uint32_t qregs[MAX_QREGS];
 113
 114    CPU_COMMON
 115
 116    uint32_t features;
 117} CPUM68KState;
 118
 119#include "cpu-qom.h"
 120
 121void m68k_tcg_init(void);
 122CPUM68KState *cpu_m68k_init(const char *cpu_model);
 123int cpu_m68k_exec(CPUM68KState *s);
 124void do_interrupt(CPUM68KState *env1);
 125void do_interrupt_m68k_hardirq(CPUM68KState *env1);
 126/* you can call this signal handler from your SIGBUS and SIGSEGV
 127   signal handlers to inform the virtual CPU of exceptions. non zero
 128   is returned if the signal was handled by the virtual CPU.  */
 129int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 130                           void *puc);
 131void cpu_m68k_flush_flags(CPUM68KState *, int);
 132
 133enum {
 134    CC_OP_DYNAMIC, /* Use env->cc_op  */
 135    CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
 136    CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
 137    CC_OP_ADD,   /* CC_DEST = result, CC_SRC = source */
 138    CC_OP_SUB,   /* CC_DEST = result, CC_SRC = source */
 139    CC_OP_CMPB,  /* CC_DEST = result, CC_SRC = source */
 140    CC_OP_CMPW,  /* CC_DEST = result, CC_SRC = source */
 141    CC_OP_ADDX,  /* CC_DEST = result, CC_SRC = source */
 142    CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
 143    CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
 144};
 145
 146#define CCF_C 0x01
 147#define CCF_V 0x02
 148#define CCF_Z 0x04
 149#define CCF_N 0x08
 150#define CCF_X 0x10
 151
 152#define SR_I_SHIFT 8
 153#define SR_I  0x0700
 154#define SR_M  0x1000
 155#define SR_S  0x2000
 156#define SR_T  0x8000
 157
 158#define M68K_SSP    0
 159#define M68K_USP    1
 160
 161/* CACR fields are implementation defined, but some bits are common.  */
 162#define M68K_CACR_EUSP  0x10
 163
 164#define MACSR_PAV0  0x100
 165#define MACSR_OMC   0x080
 166#define MACSR_SU    0x040
 167#define MACSR_FI    0x020
 168#define MACSR_RT    0x010
 169#define MACSR_N     0x008
 170#define MACSR_Z     0x004
 171#define MACSR_V     0x002
 172#define MACSR_EV    0x001
 173
 174void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector);
 175void m68k_set_macsr(CPUM68KState *env, uint32_t val);
 176void m68k_switch_sp(CPUM68KState *env);
 177
 178#define M68K_FPCR_PREC (1 << 6)
 179
 180void do_m68k_semihosting(CPUM68KState *env, int nr);
 181
 182/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 183   Each feature covers the subset of instructions common to the
 184   ISA revisions mentioned.  */
 185
 186enum m68k_features {
 187    M68K_FEATURE_CF_ISA_A,
 188    M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 189    M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 190    M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 191    M68K_FEATURE_CF_FPU,
 192    M68K_FEATURE_CF_MAC,
 193    M68K_FEATURE_CF_EMAC,
 194    M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 195    M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 196    M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 197    M68K_FEATURE_WORD_INDEX /* word sized address index registers.  */
 198};
 199
 200static inline int m68k_feature(CPUM68KState *env, int feature)
 201{
 202    return (env->features & (1u << feature)) != 0;
 203}
 204
 205void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 206
 207void register_m68k_insns (CPUM68KState *env);
 208
 209#ifdef CONFIG_USER_ONLY
 210/* Linux uses 8k pages.  */
 211#define TARGET_PAGE_BITS 13
 212#else
 213/* Smallest TLB entry size is 1k.  */
 214#define TARGET_PAGE_BITS 10
 215#endif
 216
 217#define TARGET_PHYS_ADDR_SPACE_BITS 32
 218#define TARGET_VIRT_ADDR_SPACE_BITS 32
 219
 220#define cpu_init cpu_m68k_init
 221#define cpu_exec cpu_m68k_exec
 222#define cpu_gen_code cpu_m68k_gen_code
 223#define cpu_signal_handler cpu_m68k_signal_handler
 224#define cpu_list m68k_cpu_list
 225
 226/* MMU modes definitions */
 227#define MMU_MODE0_SUFFIX _kernel
 228#define MMU_MODE1_SUFFIX _user
 229#define MMU_USER_IDX 1
 230static inline int cpu_mmu_index (CPUM68KState *env)
 231{
 232    return (env->sr & SR_S) == 0 ? 1 : 0;
 233}
 234
 235int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
 236                              int mmu_idx);
 237#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
 238
 239#if defined(CONFIG_USER_ONLY)
 240static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
 241{
 242    if (newsp)
 243        env->aregs[7] = newsp;
 244    env->dregs[0] = 0;
 245}
 246#endif
 247
 248#include "cpu-all.h"
 249
 250static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 251                                        target_ulong *cs_base, int *flags)
 252{
 253    *pc = env->pc;
 254    *cs_base = 0;
 255    *flags = (env->fpcr & M68K_FPCR_PREC)       /* Bit  6 */
 256            | (env->sr & SR_S)                  /* Bit  13 */
 257            | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 258}
 259
 260static inline bool cpu_has_work(CPUState *cpu)
 261{
 262    CPUM68KState *env = &M68K_CPU(cpu)->env;
 263
 264    return env->interrupt_request & CPU_INTERRUPT_HARD;
 265}
 266
 267#include "exec-all.h"
 268
 269static inline void cpu_pc_from_tb(CPUM68KState *env, TranslationBlock *tb)
 270{
 271    env->pc = tb->pc;
 272}
 273
 274#endif
 275