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25#include "sysbus.h"
26#include "char/char.h"
27#include "qemu/log.h"
28
29#define D(x)
30
31#define RW_TR_CTRL (0x00 / 4)
32#define RW_TR_DMA_EN (0x04 / 4)
33#define RW_REC_CTRL (0x08 / 4)
34#define RW_DOUT (0x1c / 4)
35#define RS_STAT_DIN (0x20 / 4)
36#define R_STAT_DIN (0x24 / 4)
37#define RW_INTR_MASK (0x2c / 4)
38#define RW_ACK_INTR (0x30 / 4)
39#define R_INTR (0x34 / 4)
40#define R_MASKED_INTR (0x38 / 4)
41#define R_MAX (0x3c / 4)
42
43#define STAT_DAV 16
44#define STAT_TR_IDLE 22
45#define STAT_TR_RDY 24
46
47struct etrax_serial
48{
49 SysBusDevice busdev;
50 MemoryRegion mmio;
51 CharDriverState *chr;
52 qemu_irq irq;
53
54 int pending_tx;
55
56 uint8_t rx_fifo[16];
57 unsigned int rx_fifo_pos;
58 unsigned int rx_fifo_len;
59
60
61 uint32_t regs[R_MAX];
62};
63
64static void ser_update_irq(struct etrax_serial *s)
65{
66
67 if (s->rx_fifo_len) {
68 s->regs[R_INTR] |= 8;
69 } else {
70 s->regs[R_INTR] &= ~8;
71 }
72
73 s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
74 qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
75}
76
77static uint64_t
78ser_read(void *opaque, hwaddr addr, unsigned int size)
79{
80 struct etrax_serial *s = opaque;
81 D(CPUCRISState *env = s->env);
82 uint32_t r = 0;
83
84 addr >>= 2;
85 switch (addr)
86 {
87 case R_STAT_DIN:
88 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
89 if (s->rx_fifo_len) {
90 r |= 1 << STAT_DAV;
91 }
92 r |= 1 << STAT_TR_RDY;
93 r |= 1 << STAT_TR_IDLE;
94 break;
95 case RS_STAT_DIN:
96 r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
97 if (s->rx_fifo_len) {
98 r |= 1 << STAT_DAV;
99 s->rx_fifo_len--;
100 }
101 r |= 1 << STAT_TR_RDY;
102 r |= 1 << STAT_TR_IDLE;
103 break;
104 default:
105 r = s->regs[addr];
106 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
107 break;
108 }
109 return r;
110}
111
112static void
113ser_write(void *opaque, hwaddr addr,
114 uint64_t val64, unsigned int size)
115{
116 struct etrax_serial *s = opaque;
117 uint32_t value = val64;
118 unsigned char ch = val64;
119 D(CPUCRISState *env = s->env);
120
121 D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
122 addr >>= 2;
123 switch (addr)
124 {
125 case RW_DOUT:
126 qemu_chr_fe_write(s->chr, &ch, 1);
127 s->regs[R_INTR] |= 3;
128 s->pending_tx = 1;
129 s->regs[addr] = value;
130 break;
131 case RW_ACK_INTR:
132 if (s->pending_tx) {
133 value &= ~1;
134 s->pending_tx = 0;
135 D(qemu_log("fixedup value=%x r_intr=%x\n",
136 value, s->regs[R_INTR]));
137 }
138 s->regs[addr] = value;
139 s->regs[R_INTR] &= ~value;
140 D(printf("r_intr=%x\n", s->regs[R_INTR]));
141 break;
142 default:
143 s->regs[addr] = value;
144 break;
145 }
146 ser_update_irq(s);
147}
148
149static const MemoryRegionOps ser_ops = {
150 .read = ser_read,
151 .write = ser_write,
152 .endianness = DEVICE_NATIVE_ENDIAN,
153 .valid = {
154 .min_access_size = 4,
155 .max_access_size = 4
156 }
157};
158
159static void serial_receive(void *opaque, const uint8_t *buf, int size)
160{
161 struct etrax_serial *s = opaque;
162 int i;
163
164
165 if (s->rx_fifo_len >= 16) {
166 qemu_log("WARNING: UART dropped char.\n");
167 return;
168 }
169
170 for (i = 0; i < size; i++) {
171 s->rx_fifo[s->rx_fifo_pos] = buf[i];
172 s->rx_fifo_pos++;
173 s->rx_fifo_pos &= 15;
174 s->rx_fifo_len++;
175 }
176
177 ser_update_irq(s);
178}
179
180static int serial_can_receive(void *opaque)
181{
182 struct etrax_serial *s = opaque;
183 int r;
184
185
186 if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
187 return 0;
188 }
189
190 r = sizeof(s->rx_fifo) - s->rx_fifo_len;
191 return r;
192}
193
194static void serial_event(void *opaque, int event)
195{
196
197}
198
199static void etraxfs_ser_reset(DeviceState *d)
200{
201 struct etrax_serial *s = container_of(d, typeof(*s), busdev.qdev);
202
203
204 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
205 s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
206
207 s->regs[RW_REC_CTRL] = 0x10000;
208
209}
210
211static int etraxfs_ser_init(SysBusDevice *dev)
212{
213 struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
214
215 sysbus_init_irq(dev, &s->irq);
216 memory_region_init_io(&s->mmio, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
217 sysbus_init_mmio(dev, &s->mmio);
218
219 s->chr = qemu_char_get_next_serial();
220 if (s->chr)
221 qemu_chr_add_handlers(s->chr,
222 serial_can_receive, serial_receive,
223 serial_event, s);
224 return 0;
225}
226
227static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
228{
229 DeviceClass *dc = DEVICE_CLASS(klass);
230 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
231
232 k->init = etraxfs_ser_init;
233 dc->reset = etraxfs_ser_reset;
234}
235
236static const TypeInfo etraxfs_ser_info = {
237 .name = "etraxfs,serial",
238 .parent = TYPE_SYS_BUS_DEVICE,
239 .instance_size = sizeof(struct etrax_serial),
240 .class_init = etraxfs_ser_class_init,
241};
242
243static void etraxfs_serial_register_types(void)
244{
245 type_register_static(&etraxfs_ser_info);
246}
247
248type_init(etraxfs_serial_register_types)
249
