qemu/hw/stellaris_enet.c
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   1/*
   2 * Luminary Micro Stellaris Ethernet Controller
   3 *
   4 * Copyright (c) 2007 CodeSourcery.
   5 * Written by Paul Brook
   6 *
   7 * This code is licensed under the GPL.
   8 */
   9#include "sysbus.h"
  10#include "net/net.h"
  11#include <zlib.h>
  12
  13//#define DEBUG_STELLARIS_ENET 1
  14
  15#ifdef DEBUG_STELLARIS_ENET
  16#define DPRINTF(fmt, ...) \
  17do { printf("stellaris_enet: " fmt , ## __VA_ARGS__); } while (0)
  18#define BADF(fmt, ...) \
  19do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
  20#else
  21#define DPRINTF(fmt, ...) do {} while(0)
  22#define BADF(fmt, ...) \
  23do { fprintf(stderr, "stellaris_enet: error: " fmt , ## __VA_ARGS__);} while (0)
  24#endif
  25
  26#define SE_INT_RX       0x01
  27#define SE_INT_TXER     0x02
  28#define SE_INT_TXEMP    0x04
  29#define SE_INT_FOV      0x08
  30#define SE_INT_RXER     0x10
  31#define SE_INT_MD       0x20
  32#define SE_INT_PHY      0x40
  33
  34#define SE_RCTL_RXEN    0x01
  35#define SE_RCTL_AMUL    0x02
  36#define SE_RCTL_PRMS    0x04
  37#define SE_RCTL_BADCRC  0x08
  38#define SE_RCTL_RSTFIFO 0x10
  39
  40#define SE_TCTL_TXEN    0x01
  41#define SE_TCTL_PADEN   0x02
  42#define SE_TCTL_CRC     0x04
  43#define SE_TCTL_DUPLEX  0x08
  44
  45typedef struct {
  46    SysBusDevice busdev;
  47    uint32_t ris;
  48    uint32_t im;
  49    uint32_t rctl;
  50    uint32_t tctl;
  51    uint32_t thr;
  52    uint32_t mctl;
  53    uint32_t mdv;
  54    uint32_t mtxd;
  55    uint32_t mrxd;
  56    uint32_t np;
  57    int tx_frame_len;
  58    int tx_fifo_len;
  59    uint8_t tx_fifo[2048];
  60    /* Real hardware has a 2k fifo, which works out to be at most 31 packets.
  61       We implement a full 31 packet fifo.  */
  62    struct {
  63        uint8_t data[2048];
  64        int len;
  65    } rx[31];
  66    uint8_t *rx_fifo;
  67    int rx_fifo_len;
  68    int next_packet;
  69    NICState *nic;
  70    NICConf conf;
  71    qemu_irq irq;
  72    MemoryRegion mmio;
  73} stellaris_enet_state;
  74
  75static void stellaris_enet_update(stellaris_enet_state *s)
  76{
  77    qemu_set_irq(s->irq, (s->ris & s->im) != 0);
  78}
  79
  80/* TODO: Implement MAC address filtering.  */
  81static ssize_t stellaris_enet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
  82{
  83    stellaris_enet_state *s = qemu_get_nic_opaque(nc);
  84    int n;
  85    uint8_t *p;
  86    uint32_t crc;
  87
  88    if ((s->rctl & SE_RCTL_RXEN) == 0)
  89        return -1;
  90    if (s->np >= 31) {
  91        DPRINTF("Packet dropped\n");
  92        return -1;
  93    }
  94
  95    DPRINTF("Received packet len=%d\n", size);
  96    n = s->next_packet + s->np;
  97    if (n >= 31)
  98        n -= 31;
  99    s->np++;
 100
 101    s->rx[n].len = size + 6;
 102    p = s->rx[n].data;
 103    *(p++) = (size + 6);
 104    *(p++) = (size + 6) >> 8;
 105    memcpy (p, buf, size);
 106    p += size;
 107    crc = crc32(~0, buf, size);
 108    *(p++) = crc;
 109    *(p++) = crc >> 8;
 110    *(p++) = crc >> 16;
 111    *(p++) = crc >> 24;
 112    /* Clear the remaining bytes in the last word.  */
 113    if ((size & 3) != 2) {
 114        memset(p, 0, (6 - size) & 3);
 115    }
 116
 117    s->ris |= SE_INT_RX;
 118    stellaris_enet_update(s);
 119
 120    return size;
 121}
 122
 123static int stellaris_enet_can_receive(NetClientState *nc)
 124{
 125    stellaris_enet_state *s = qemu_get_nic_opaque(nc);
 126
 127    if ((s->rctl & SE_RCTL_RXEN) == 0)
 128        return 1;
 129
 130    return (s->np < 31);
 131}
 132
 133static uint64_t stellaris_enet_read(void *opaque, hwaddr offset,
 134                                    unsigned size)
 135{
 136    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 137    uint32_t val;
 138
 139    switch (offset) {
 140    case 0x00: /* RIS */
 141        DPRINTF("IRQ status %02x\n", s->ris);
 142        return s->ris;
 143    case 0x04: /* IM */
 144        return s->im;
 145    case 0x08: /* RCTL */
 146        return s->rctl;
 147    case 0x0c: /* TCTL */
 148        return s->tctl;
 149    case 0x10: /* DATA */
 150        if (s->rx_fifo_len == 0) {
 151            if (s->np == 0) {
 152                BADF("RX underflow\n");
 153                return 0;
 154            }
 155            s->rx_fifo_len = s->rx[s->next_packet].len;
 156            s->rx_fifo = s->rx[s->next_packet].data;
 157            DPRINTF("RX FIFO start packet len=%d\n", s->rx_fifo_len);
 158        }
 159        val = s->rx_fifo[0] | (s->rx_fifo[1] << 8) | (s->rx_fifo[2] << 16)
 160              | (s->rx_fifo[3] << 24);
 161        s->rx_fifo += 4;
 162        s->rx_fifo_len -= 4;
 163        if (s->rx_fifo_len <= 0) {
 164            s->rx_fifo_len = 0;
 165            s->next_packet++;
 166            if (s->next_packet >= 31)
 167                s->next_packet = 0;
 168            s->np--;
 169            DPRINTF("RX done np=%d\n", s->np);
 170        }
 171        return val;
 172    case 0x14: /* IA0 */
 173        return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
 174               | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
 175    case 0x18: /* IA1 */
 176        return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
 177    case 0x1c: /* THR */
 178        return s->thr;
 179    case 0x20: /* MCTL */
 180        return s->mctl;
 181    case 0x24: /* MDV */
 182        return s->mdv;
 183    case 0x28: /* MADD */
 184        return 0;
 185    case 0x2c: /* MTXD */
 186        return s->mtxd;
 187    case 0x30: /* MRXD */
 188        return s->mrxd;
 189    case 0x34: /* NP */
 190        return s->np;
 191    case 0x38: /* TR */
 192        return 0;
 193    case 0x3c: /* Undocuented: Timestamp? */
 194        return 0;
 195    default:
 196        hw_error("stellaris_enet_read: Bad offset %x\n", (int)offset);
 197        return 0;
 198    }
 199}
 200
 201static void stellaris_enet_write(void *opaque, hwaddr offset,
 202                                 uint64_t value, unsigned size)
 203{
 204    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 205
 206    switch (offset) {
 207    case 0x00: /* IACK */
 208        s->ris &= ~value;
 209        DPRINTF("IRQ ack %02x/%02x\n", value, s->ris);
 210        stellaris_enet_update(s);
 211        /* Clearing TXER also resets the TX fifo.  */
 212        if (value & SE_INT_TXER)
 213            s->tx_frame_len = -1;
 214        break;
 215    case 0x04: /* IM */
 216        DPRINTF("IRQ mask %02x/%02x\n", value, s->ris);
 217        s->im = value;
 218        stellaris_enet_update(s);
 219        break;
 220    case 0x08: /* RCTL */
 221        s->rctl = value;
 222        if (value & SE_RCTL_RSTFIFO) {
 223            s->rx_fifo_len = 0;
 224            s->np = 0;
 225            stellaris_enet_update(s);
 226        }
 227        break;
 228    case 0x0c: /* TCTL */
 229        s->tctl = value;
 230        break;
 231    case 0x10: /* DATA */
 232        if (s->tx_frame_len == -1) {
 233            s->tx_frame_len = value & 0xffff;
 234            if (s->tx_frame_len > 2032) {
 235                DPRINTF("TX frame too long (%d)\n", s->tx_frame_len);
 236                s->tx_frame_len = 0;
 237                s->ris |= SE_INT_TXER;
 238                stellaris_enet_update(s);
 239            } else {
 240                DPRINTF("Start TX frame len=%d\n", s->tx_frame_len);
 241                /* The value written does not include the ethernet header.  */
 242                s->tx_frame_len += 14;
 243                if ((s->tctl & SE_TCTL_CRC) == 0)
 244                    s->tx_frame_len += 4;
 245                s->tx_fifo_len = 0;
 246                s->tx_fifo[s->tx_fifo_len++] = value >> 16;
 247                s->tx_fifo[s->tx_fifo_len++] = value >> 24;
 248            }
 249        } else {
 250            s->tx_fifo[s->tx_fifo_len++] = value;
 251            s->tx_fifo[s->tx_fifo_len++] = value >> 8;
 252            s->tx_fifo[s->tx_fifo_len++] = value >> 16;
 253            s->tx_fifo[s->tx_fifo_len++] = value >> 24;
 254            if (s->tx_fifo_len >= s->tx_frame_len) {
 255                /* We don't implement explicit CRC, so just chop it off.  */
 256                if ((s->tctl & SE_TCTL_CRC) == 0)
 257                    s->tx_frame_len -= 4;
 258                if ((s->tctl & SE_TCTL_PADEN) && s->tx_frame_len < 60) {
 259                    memset(&s->tx_fifo[s->tx_frame_len], 0, 60 - s->tx_frame_len);
 260                    s->tx_fifo_len = 60;
 261                }
 262                qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo,
 263                                 s->tx_frame_len);
 264                s->tx_frame_len = -1;
 265                s->ris |= SE_INT_TXEMP;
 266                stellaris_enet_update(s);
 267                DPRINTF("Done TX\n");
 268            }
 269        }
 270        break;
 271    case 0x14: /* IA0 */
 272        s->conf.macaddr.a[0] = value;
 273        s->conf.macaddr.a[1] = value >> 8;
 274        s->conf.macaddr.a[2] = value >> 16;
 275        s->conf.macaddr.a[3] = value >> 24;
 276        break;
 277    case 0x18: /* IA1 */
 278        s->conf.macaddr.a[4] = value;
 279        s->conf.macaddr.a[5] = value >> 8;
 280        break;
 281    case 0x1c: /* THR */
 282        s->thr = value;
 283        break;
 284    case 0x20: /* MCTL */
 285        s->mctl = value;
 286        break;
 287    case 0x24: /* MDV */
 288        s->mdv = value;
 289        break;
 290    case 0x28: /* MADD */
 291        /* ignored.  */
 292        break;
 293    case 0x2c: /* MTXD */
 294        s->mtxd = value & 0xff;
 295        break;
 296    case 0x30: /* MRXD */
 297    case 0x34: /* NP */
 298    case 0x38: /* TR */
 299        /* Ignored.  */
 300    case 0x3c: /* Undocuented: Timestamp? */
 301        /* Ignored.  */
 302        break;
 303    default:
 304        hw_error("stellaris_enet_write: Bad offset %x\n", (int)offset);
 305    }
 306}
 307
 308static const MemoryRegionOps stellaris_enet_ops = {
 309    .read = stellaris_enet_read,
 310    .write = stellaris_enet_write,
 311    .endianness = DEVICE_NATIVE_ENDIAN,
 312};
 313
 314static void stellaris_enet_reset(stellaris_enet_state *s)
 315{
 316    s->mdv = 0x80;
 317    s->rctl = SE_RCTL_BADCRC;
 318    s->im = SE_INT_PHY | SE_INT_MD | SE_INT_RXER | SE_INT_FOV | SE_INT_TXEMP
 319            | SE_INT_TXER | SE_INT_RX;
 320    s->thr = 0x3f;
 321    s->tx_frame_len = -1;
 322}
 323
 324static void stellaris_enet_save(QEMUFile *f, void *opaque)
 325{
 326    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 327    int i;
 328
 329    qemu_put_be32(f, s->ris);
 330    qemu_put_be32(f, s->im);
 331    qemu_put_be32(f, s->rctl);
 332    qemu_put_be32(f, s->tctl);
 333    qemu_put_be32(f, s->thr);
 334    qemu_put_be32(f, s->mctl);
 335    qemu_put_be32(f, s->mdv);
 336    qemu_put_be32(f, s->mtxd);
 337    qemu_put_be32(f, s->mrxd);
 338    qemu_put_be32(f, s->np);
 339    qemu_put_be32(f, s->tx_frame_len);
 340    qemu_put_be32(f, s->tx_fifo_len);
 341    qemu_put_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
 342    for (i = 0; i < 31; i++) {
 343        qemu_put_be32(f, s->rx[i].len);
 344        qemu_put_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
 345
 346    }
 347    qemu_put_be32(f, s->next_packet);
 348    qemu_put_be32(f, s->rx_fifo - s->rx[s->next_packet].data);
 349    qemu_put_be32(f, s->rx_fifo_len);
 350}
 351
 352static int stellaris_enet_load(QEMUFile *f, void *opaque, int version_id)
 353{
 354    stellaris_enet_state *s = (stellaris_enet_state *)opaque;
 355    int i;
 356
 357    if (version_id != 1)
 358        return -EINVAL;
 359
 360    s->ris = qemu_get_be32(f);
 361    s->im = qemu_get_be32(f);
 362    s->rctl = qemu_get_be32(f);
 363    s->tctl = qemu_get_be32(f);
 364    s->thr = qemu_get_be32(f);
 365    s->mctl = qemu_get_be32(f);
 366    s->mdv = qemu_get_be32(f);
 367    s->mtxd = qemu_get_be32(f);
 368    s->mrxd = qemu_get_be32(f);
 369    s->np = qemu_get_be32(f);
 370    s->tx_frame_len = qemu_get_be32(f);
 371    s->tx_fifo_len = qemu_get_be32(f);
 372    qemu_get_buffer(f, s->tx_fifo, sizeof(s->tx_fifo));
 373    for (i = 0; i < 31; i++) {
 374        s->rx[i].len = qemu_get_be32(f);
 375        qemu_get_buffer(f, s->rx[i].data, sizeof(s->rx[i].data));
 376
 377    }
 378    s->next_packet = qemu_get_be32(f);
 379    s->rx_fifo = s->rx[s->next_packet].data + qemu_get_be32(f);
 380    s->rx_fifo_len = qemu_get_be32(f);
 381
 382    return 0;
 383}
 384
 385static void stellaris_enet_cleanup(NetClientState *nc)
 386{
 387    stellaris_enet_state *s = qemu_get_nic_opaque(nc);
 388
 389    unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
 390
 391    memory_region_destroy(&s->mmio);
 392
 393    g_free(s);
 394}
 395
 396static NetClientInfo net_stellaris_enet_info = {
 397    .type = NET_CLIENT_OPTIONS_KIND_NIC,
 398    .size = sizeof(NICState),
 399    .can_receive = stellaris_enet_can_receive,
 400    .receive = stellaris_enet_receive,
 401    .cleanup = stellaris_enet_cleanup,
 402};
 403
 404static int stellaris_enet_init(SysBusDevice *dev)
 405{
 406    stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
 407
 408    memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
 409                          0x1000);
 410    sysbus_init_mmio(dev, &s->mmio);
 411    sysbus_init_irq(dev, &s->irq);
 412    qemu_macaddr_default_if_unset(&s->conf.macaddr);
 413
 414    s->nic = qemu_new_nic(&net_stellaris_enet_info, &s->conf,
 415                          object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 416    qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 417
 418    stellaris_enet_reset(s);
 419    register_savevm(&s->busdev.qdev, "stellaris_enet", -1, 1,
 420                    stellaris_enet_save, stellaris_enet_load, s);
 421    return 0;
 422}
 423
 424static Property stellaris_enet_properties[] = {
 425    DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf),
 426    DEFINE_PROP_END_OF_LIST(),
 427};
 428
 429static void stellaris_enet_class_init(ObjectClass *klass, void *data)
 430{
 431    DeviceClass *dc = DEVICE_CLASS(klass);
 432    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 433
 434    k->init = stellaris_enet_init;
 435    dc->props = stellaris_enet_properties;
 436}
 437
 438static const TypeInfo stellaris_enet_info = {
 439    .name          = "stellaris_enet",
 440    .parent        = TYPE_SYS_BUS_DEVICE,
 441    .instance_size = sizeof(stellaris_enet_state),
 442    .class_init    = stellaris_enet_class_init,
 443};
 444
 445static void stellaris_enet_register_types(void)
 446{
 447    type_register_static(&stellaris_enet_info);
 448}
 449
 450type_init(stellaris_enet_register_types)
 451