LXR qemu/target-sparc/machine.c

   1#include "hw/hw.h"
   2#include "hw/boards.h"
   3#include "qemu/timer.h"
   4
   5#include "cpu.h"
   6
   7void cpu_save(QEMUFile *f, void *opaque)
   8{
   9    CPUSPARCState *env = opaque;
  10    int i;
  11    uint32_t tmp;
  12
  13    // if env->cwp == env->nwindows - 1, this will set the ins of the last
  14    // window as the outs of the first window
  15    cpu_set_cwp(env, env->cwp);
  16
  17    for(i = 0; i < 8; i++)
  18        qemu_put_betls(f, &env->gregs[i]);
  19    qemu_put_be32s(f, &env->nwindows);
  20    for(i = 0; i < env->nwindows * 16; i++)
  21        qemu_put_betls(f, &env->regbase[i]);
  22
  23    /* FPU */
  24    for (i = 0; i < TARGET_DPREGS; i++) {
  25        qemu_put_be32(f, env->fpr[i].l.upper);
  26        qemu_put_be32(f, env->fpr[i].l.lower);
  27    }
  28
  29    qemu_put_betls(f, &env->pc);
  30    qemu_put_betls(f, &env->npc);
  31    qemu_put_betls(f, &env->y);
  32    tmp = cpu_get_psr(env);
  33    qemu_put_be32(f, tmp);
  34    qemu_put_betls(f, &env->fsr);
  35    qemu_put_betls(f, &env->tbr);
  36    tmp = env->interrupt_index;
  37    qemu_put_be32(f, tmp);
  38    qemu_put_be32s(f, &env->pil_in);
  39#ifndef TARGET_SPARC64
  40    qemu_put_be32s(f, &env->wim);
  41    /* MMU */
  42    for (i = 0; i < 32; i++)
  43        qemu_put_be32s(f, &env->mmuregs[i]);
  44    for (i = 0; i < 4; i++) {
  45        qemu_put_be64s(f, &env->mxccdata[i]);
  46    }
  47    for (i = 0; i < 8; i++) {
  48        qemu_put_be64s(f, &env->mxccregs[i]);
  49    }
  50    qemu_put_be32s(f, &env->mmubpctrv);
  51    qemu_put_be32s(f, &env->mmubpctrc);
  52    qemu_put_be32s(f, &env->mmubpctrs);
  53    qemu_put_be64s(f, &env->mmubpaction);
  54    for (i = 0; i < 4; i++) {
  55        qemu_put_be64s(f, &env->mmubpregs[i]);
  56    }
  57#else
  58    qemu_put_be64s(f, &env->lsu);
  59    for (i = 0; i < 16; i++) {
  60        qemu_put_be64s(f, &env->immuregs[i]);
  61        qemu_put_be64s(f, &env->dmmuregs[i]);
  62    }
  63    for (i = 0; i < 64; i++) {
  64        qemu_put_be64s(f, &env->itlb[i].tag);
  65        qemu_put_be64s(f, &env->itlb[i].tte);
  66        qemu_put_be64s(f, &env->dtlb[i].tag);
  67        qemu_put_be64s(f, &env->dtlb[i].tte);
  68    }
  69    qemu_put_be32s(f, &env->mmu_version);
  70    for (i = 0; i < MAXTL_MAX; i++) {
  71        qemu_put_be64s(f, &env->ts[i].tpc);
  72        qemu_put_be64s(f, &env->ts[i].tnpc);
  73        qemu_put_be64s(f, &env->ts[i].tstate);
  74        qemu_put_be32s(f, &env->ts[i].tt);
  75    }
  76    qemu_put_be32s(f, &env->xcc);
  77    qemu_put_be32s(f, &env->asi);
  78    qemu_put_be32s(f, &env->pstate);
  79    qemu_put_be32s(f, &env->tl);
  80    qemu_put_be32s(f, &env->cansave);
  81    qemu_put_be32s(f, &env->canrestore);
  82    qemu_put_be32s(f, &env->otherwin);
  83    qemu_put_be32s(f, &env->wstate);
  84    qemu_put_be32s(f, &env->cleanwin);
  85    for (i = 0; i < 8; i++)
  86        qemu_put_be64s(f, &env->agregs[i]);
  87    for (i = 0; i < 8; i++)
  88        qemu_put_be64s(f, &env->bgregs[i]);
  89    for (i = 0; i < 8; i++)
  90        qemu_put_be64s(f, &env->igregs[i]);
  91    for (i = 0; i < 8; i++)
  92        qemu_put_be64s(f, &env->mgregs[i]);
  93    qemu_put_be64s(f, &env->fprs);
  94    qemu_put_be64s(f, &env->tick_cmpr);
  95    qemu_put_be64s(f, &env->stick_cmpr);
  96    cpu_put_timer(f, env->tick);
  97    cpu_put_timer(f, env->stick);
  98    qemu_put_be64s(f, &env->gsr);
  99    qemu_put_be32s(f, &env->gl);
 100    qemu_put_be64s(f, &env->hpstate);
 101    for (i = 0; i < MAXTL_MAX; i++)
 102        qemu_put_be64s(f, &env->htstate[i]);
 103    qemu_put_be64s(f, &env->hintp);
 104    qemu_put_be64s(f, &env->htba);
 105    qemu_put_be64s(f, &env->hver);
 106    qemu_put_be64s(f, &env->hstick_cmpr);
 107    qemu_put_be64s(f, &env->ssr);
 108    cpu_put_timer(f, env->hstick);
 109#endif
 110}
 111
 112int cpu_load(QEMUFile *f, void *opaque, int version_id)
 113{
 114    CPUSPARCState *env = opaque;
 115    int i;
 116    uint32_t tmp;
 117
 118    if (version_id < 6)
 119        return -EINVAL;
 120    for(i = 0; i < 8; i++)
 121        qemu_get_betls(f, &env->gregs[i]);
 122    qemu_get_be32s(f, &env->nwindows);
 123    for(i = 0; i < env->nwindows * 16; i++)
 124        qemu_get_betls(f, &env->regbase[i]);
 125
 126    /* FPU */
 127    for (i = 0; i < TARGET_DPREGS; i++) {
 128        env->fpr[i].l.upper = qemu_get_be32(f);
 129        env->fpr[i].l.lower = qemu_get_be32(f);
 130    }
 131
 132    qemu_get_betls(f, &env->pc);
 133    qemu_get_betls(f, &env->npc);
 134    qemu_get_betls(f, &env->y);
 135    tmp = qemu_get_be32(f);
 136    env->cwp = 0; /* needed to ensure that the wrapping registers are
 137                     correctly updated */
 138    cpu_put_psr(env, tmp);
 139    qemu_get_betls(f, &env->fsr);
 140    qemu_get_betls(f, &env->tbr);
 141    tmp = qemu_get_be32(f);
 142    env->interrupt_index = tmp;
 143    qemu_get_be32s(f, &env->pil_in);
 144#ifndef TARGET_SPARC64
 145    qemu_get_be32s(f, &env->wim);
 146    /* MMU */
 147    for (i = 0; i < 32; i++)
 148        qemu_get_be32s(f, &env->mmuregs[i]);
 149    for (i = 0; i < 4; i++) {
 150        qemu_get_be64s(f, &env->mxccdata[i]);
 151    }
 152    for (i = 0; i < 8; i++) {
 153        qemu_get_be64s(f, &env->mxccregs[i]);
 154    }
 155    qemu_get_be32s(f, &env->mmubpctrv);
 156    qemu_get_be32s(f, &env->mmubpctrc);
 157    qemu_get_be32s(f, &env->mmubpctrs);
 158    qemu_get_be64s(f, &env->mmubpaction);
 159    for (i = 0; i < 4; i++) {
 160        qemu_get_be64s(f, &env->mmubpregs[i]);
 161    }
 162#else
 163    qemu_get_be64s(f, &env->lsu);
 164    for (i = 0; i < 16; i++) {
 165        qemu_get_be64s(f, &env->immuregs[i]);
 166        qemu_get_be64s(f, &env->dmmuregs[i]);
 167    }
 168    for (i = 0; i < 64; i++) {
 169        qemu_get_be64s(f, &env->itlb[i].tag);
 170        qemu_get_be64s(f, &env->itlb[i].tte);
 171        qemu_get_be64s(f, &env->dtlb[i].tag);
 172        qemu_get_be64s(f, &env->dtlb[i].tte);
 173    }
 174    qemu_get_be32s(f, &env->mmu_version);
 175    for (i = 0; i < MAXTL_MAX; i++) {
 176        qemu_get_be64s(f, &env->ts[i].tpc);
 177        qemu_get_be64s(f, &env->ts[i].tnpc);
 178        qemu_get_be64s(f, &env->ts[i].tstate);
 179        qemu_get_be32s(f, &env->ts[i].tt);
 180    }
 181    qemu_get_be32s(f, &env->xcc);
 182    qemu_get_be32s(f, &env->asi);
 183    qemu_get_be32s(f, &env->pstate);
 184    qemu_get_be32s(f, &env->tl);
 185    qemu_get_be32s(f, &env->cansave);
 186    qemu_get_be32s(f, &env->canrestore);
 187    qemu_get_be32s(f, &env->otherwin);
 188    qemu_get_be32s(f, &env->wstate);
 189    qemu_get_be32s(f, &env->cleanwin);
 190    for (i = 0; i < 8; i++)
 191        qemu_get_be64s(f, &env->agregs[i]);
 192    for (i = 0; i < 8; i++)
 193        qemu_get_be64s(f, &env->bgregs[i]);
 194    for (i = 0; i < 8; i++)
 195        qemu_get_be64s(f, &env->igregs[i]);
 196    for (i = 0; i < 8; i++)
 197        qemu_get_be64s(f, &env->mgregs[i]);
 198    qemu_get_be64s(f, &env->fprs);
 199    qemu_get_be64s(f, &env->tick_cmpr);
 200    qemu_get_be64s(f, &env->stick_cmpr);
 201    cpu_get_timer(f, env->tick);
 202    cpu_get_timer(f, env->stick);
 203    qemu_get_be64s(f, &env->gsr);
 204    qemu_get_be32s(f, &env->gl);
 205    qemu_get_be64s(f, &env->hpstate);
 206    for (i = 0; i < MAXTL_MAX; i++)
 207        qemu_get_be64s(f, &env->htstate[i]);
 208    qemu_get_be64s(f, &env->hintp);
 209    qemu_get_be64s(f, &env->htba);
 210    qemu_get_be64s(f, &env->hver);
 211    qemu_get_be64s(f, &env->hstick_cmpr);
 212    qemu_get_be64s(f, &env->ssr);
 213    cpu_get_timer(f, env->hstick);
 214#endif
 215    tlb_flush(env, 1);
 216    return 0;
 217}
 218