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25#include "hw.h"
26#include "pc.h"
27#include "pci/pci.h"
28#include "pci/pci_host.h"
29#include "isa.h"
30#include "sysbus.h"
31#include "qemu/range.h"
32#include "xen.h"
33#include "pam.h"
34#include "sysemu/sysemu.h"
35
36
37
38
39
40
41typedef struct I440FXState {
42 PCIHostState parent_obj;
43} I440FXState;
44
45#define PIIX_NUM_PIC_IRQS 16
46#define PIIX_NUM_PIRQS 4ULL
47#define XEN_PIIX_NUM_PIRQS 128ULL
48#define PIIX_PIRQC 0x60
49
50
51
52
53
54#define RCR_IOPORT 0xcf9
55
56typedef struct PIIX3State {
57 PCIDevice dev;
58
59
60
61
62
63
64
65
66
67
68#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
69#error "unable to encode pic state in 64bit in pic_levels."
70#endif
71 uint64_t pic_levels;
72
73 qemu_irq *pic;
74
75
76 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
77
78
79 uint8_t rcr;
80
81
82 MemoryRegion rcr_mem;
83} PIIX3State;
84
85struct PCII440FXState {
86 PCIDevice dev;
87 MemoryRegion *system_memory;
88 MemoryRegion *pci_address_space;
89 MemoryRegion *ram_memory;
90 MemoryRegion pci_hole;
91 MemoryRegion pci_hole_64bit;
92 PAMMemoryRegion pam_regions[13];
93 MemoryRegion smram_region;
94 uint8_t smm_enabled;
95};
96
97
98#define I440FX_PAM 0x59
99#define I440FX_PAM_SIZE 7
100#define I440FX_SMRAM 0x72
101
102static void piix3_set_irq(void *opaque, int pirq, int level);
103static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
104static void piix3_write_config_xen(PCIDevice *dev,
105 uint32_t address, uint32_t val, int len);
106
107
108
109
110static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
111{
112 int slot_addend;
113 slot_addend = (pci_dev->devfn >> 3) - 1;
114 return (pci_intx + slot_addend) & 3;
115}
116
117static void i440fx_update_memory_mappings(PCII440FXState *d)
118{
119 int i;
120
121 memory_region_transaction_begin();
122 for (i = 0; i < 13; i++) {
123 pam_update(&d->pam_regions[i], i,
124 d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
125 }
126 smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
127 memory_region_transaction_commit();
128}
129
130static void i440fx_set_smm(int val, void *arg)
131{
132 PCII440FXState *d = arg;
133
134 memory_region_transaction_begin();
135 smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
136 &d->smram_region);
137 memory_region_transaction_commit();
138}
139
140
141static void i440fx_write_config(PCIDevice *dev,
142 uint32_t address, uint32_t val, int len)
143{
144 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
145
146
147 pci_default_write_config(dev, address, val, len);
148 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
149 range_covers_byte(address, len, I440FX_SMRAM)) {
150 i440fx_update_memory_mappings(d);
151 }
152}
153
154static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
155{
156 PCII440FXState *d = opaque;
157 int ret, i;
158
159 ret = pci_device_load(&d->dev, f);
160 if (ret < 0)
161 return ret;
162 i440fx_update_memory_mappings(d);
163 qemu_get_8s(f, &d->smm_enabled);
164
165 if (version_id == 2) {
166 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
167 qemu_get_be32(f);
168 }
169 }
170
171 return 0;
172}
173
174static int i440fx_post_load(void *opaque, int version_id)
175{
176 PCII440FXState *d = opaque;
177
178 i440fx_update_memory_mappings(d);
179 return 0;
180}
181
182static const VMStateDescription vmstate_i440fx = {
183 .name = "I440FX",
184 .version_id = 3,
185 .minimum_version_id = 3,
186 .minimum_version_id_old = 1,
187 .load_state_old = i440fx_load_old,
188 .post_load = i440fx_post_load,
189 .fields = (VMStateField []) {
190 VMSTATE_PCI_DEVICE(dev, PCII440FXState),
191 VMSTATE_UINT8(smm_enabled, PCII440FXState),
192 VMSTATE_END_OF_LIST()
193 }
194};
195
196static int i440fx_pcihost_initfn(SysBusDevice *dev)
197{
198 PCIHostState *s = PCI_HOST_BRIDGE(dev);
199
200 memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
201 "pci-conf-idx", 4);
202 sysbus_add_io(dev, 0xcf8, &s->conf_mem);
203 sysbus_init_ioports(&s->busdev, 0xcf8, 4);
204
205 memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
206 "pci-conf-data", 4);
207 sysbus_add_io(dev, 0xcfc, &s->data_mem);
208 sysbus_init_ioports(&s->busdev, 0xcfc, 4);
209
210 return 0;
211}
212
213static int i440fx_initfn(PCIDevice *dev)
214{
215 PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
216
217 d->dev.config[I440FX_SMRAM] = 0x02;
218
219 cpu_smm_register(&i440fx_set_smm, d);
220 return 0;
221}
222
223static PCIBus *i440fx_common_init(const char *device_name,
224 PCII440FXState **pi440fx_state,
225 int *piix3_devfn,
226 ISABus **isa_bus, qemu_irq *pic,
227 MemoryRegion *address_space_mem,
228 MemoryRegion *address_space_io,
229 ram_addr_t ram_size,
230 hwaddr pci_hole_start,
231 hwaddr pci_hole_size,
232 hwaddr pci_hole64_start,
233 hwaddr pci_hole64_size,
234 MemoryRegion *pci_address_space,
235 MemoryRegion *ram_memory)
236{
237 DeviceState *dev;
238 PCIBus *b;
239 PCIDevice *d;
240 PCIHostState *s;
241 PIIX3State *piix3;
242 PCII440FXState *f;
243 unsigned i;
244
245 dev = qdev_create(NULL, "i440FX-pcihost");
246 s = PCI_HOST_BRIDGE(dev);
247 s->address_space = address_space_mem;
248 b = pci_bus_new(dev, NULL, pci_address_space,
249 address_space_io, 0);
250 s->bus = b;
251 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
252 qdev_init_nofail(dev);
253
254 d = pci_create_simple(b, 0, device_name);
255 *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
256 f = *pi440fx_state;
257 f->system_memory = address_space_mem;
258 f->pci_address_space = pci_address_space;
259 f->ram_memory = ram_memory;
260 memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
261 pci_hole_start, pci_hole_size);
262 memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
263 memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
264 f->pci_address_space,
265 pci_hole64_start, pci_hole64_size);
266 if (pci_hole64_size) {
267 memory_region_add_subregion(f->system_memory, pci_hole64_start,
268 &f->pci_hole_64bit);
269 }
270 memory_region_init_alias(&f->smram_region, "smram-region",
271 f->pci_address_space, 0xa0000, 0x20000);
272 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
273 &f->smram_region, 1);
274 memory_region_set_enabled(&f->smram_region, false);
275 init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
276 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
277 for (i = 0; i < 12; ++i) {
278 init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
279 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
280 PAM_EXPAN_SIZE);
281 }
282
283
284
285
286
287 if (xen_enabled()) {
288 piix3 = DO_UPCAST(PIIX3State, dev,
289 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
290 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
291 piix3, XEN_PIIX_NUM_PIRQS);
292 } else {
293 piix3 = DO_UPCAST(PIIX3State, dev,
294 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
295 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
296 PIIX_NUM_PIRQS);
297 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
298 }
299 piix3->pic = pic;
300 *isa_bus = DO_UPCAST(ISABus, qbus,
301 qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
302
303 *piix3_devfn = piix3->dev.devfn;
304
305 ram_size = ram_size / 8 / 1024 / 1024;
306 if (ram_size > 255)
307 ram_size = 255;
308 (*pi440fx_state)->dev.config[0x57]=ram_size;
309
310 i440fx_update_memory_mappings(f);
311
312 return b;
313}
314
315PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
316 ISABus **isa_bus, qemu_irq *pic,
317 MemoryRegion *address_space_mem,
318 MemoryRegion *address_space_io,
319 ram_addr_t ram_size,
320 hwaddr pci_hole_start,
321 hwaddr pci_hole_size,
322 hwaddr pci_hole64_start,
323 hwaddr pci_hole64_size,
324 MemoryRegion *pci_memory, MemoryRegion *ram_memory)
325
326{
327 PCIBus *b;
328
329 b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
330 address_space_mem, address_space_io, ram_size,
331 pci_hole_start, pci_hole_size,
332 pci_hole64_start, pci_hole64_size,
333 pci_memory, ram_memory);
334 return b;
335}
336
337
338static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
339{
340 qemu_set_irq(piix3->pic[pic_irq],
341 !!(piix3->pic_levels &
342 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
343 (pic_irq * PIIX_NUM_PIRQS))));
344}
345
346static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
347{
348 int pic_irq;
349 uint64_t mask;
350
351 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
352 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
353 return;
354 }
355
356 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
357 piix3->pic_levels &= ~mask;
358 piix3->pic_levels |= mask * !!level;
359
360 piix3_set_irq_pic(piix3, pic_irq);
361}
362
363static void piix3_set_irq(void *opaque, int pirq, int level)
364{
365 PIIX3State *piix3 = opaque;
366 piix3_set_irq_level(piix3, pirq, level);
367}
368
369static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
370{
371 PIIX3State *piix3 = opaque;
372 int irq = piix3->dev.config[PIIX_PIRQC + pin];
373 PCIINTxRoute route;
374
375 if (irq < PIIX_NUM_PIC_IRQS) {
376 route.mode = PCI_INTX_ENABLED;
377 route.irq = irq;
378 } else {
379 route.mode = PCI_INTX_DISABLED;
380 route.irq = -1;
381 }
382 return route;
383}
384
385
386static void piix3_update_irq_levels(PIIX3State *piix3)
387{
388 int pirq;
389
390 piix3->pic_levels = 0;
391 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
392 piix3_set_irq_level(piix3, pirq,
393 pci_bus_get_irq_level(piix3->dev.bus, pirq));
394 }
395}
396
397static void piix3_write_config(PCIDevice *dev,
398 uint32_t address, uint32_t val, int len)
399{
400 pci_default_write_config(dev, address, val, len);
401 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
402 PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
403 int pic_irq;
404
405 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
406 piix3_update_irq_levels(piix3);
407 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
408 piix3_set_irq_pic(piix3, pic_irq);
409 }
410 }
411}
412
413static void piix3_write_config_xen(PCIDevice *dev,
414 uint32_t address, uint32_t val, int len)
415{
416 xen_piix_pci_write_config_client(address, val, len);
417 piix3_write_config(dev, address, val, len);
418}
419
420static void piix3_reset(void *opaque)
421{
422 PIIX3State *d = opaque;
423 uint8_t *pci_conf = d->dev.config;
424
425 pci_conf[0x04] = 0x07;
426 pci_conf[0x05] = 0x00;
427 pci_conf[0x06] = 0x00;
428 pci_conf[0x07] = 0x02;
429 pci_conf[0x4c] = 0x4d;
430 pci_conf[0x4e] = 0x03;
431 pci_conf[0x4f] = 0x00;
432 pci_conf[0x60] = 0x80;
433 pci_conf[0x61] = 0x80;
434 pci_conf[0x62] = 0x80;
435 pci_conf[0x63] = 0x80;
436 pci_conf[0x69] = 0x02;
437 pci_conf[0x70] = 0x80;
438 pci_conf[0x76] = 0x0c;
439 pci_conf[0x77] = 0x0c;
440 pci_conf[0x78] = 0x02;
441 pci_conf[0x79] = 0x00;
442 pci_conf[0x80] = 0x00;
443 pci_conf[0x82] = 0x00;
444 pci_conf[0xa0] = 0x08;
445 pci_conf[0xa2] = 0x00;
446 pci_conf[0xa3] = 0x00;
447 pci_conf[0xa4] = 0x00;
448 pci_conf[0xa5] = 0x00;
449 pci_conf[0xa6] = 0x00;
450 pci_conf[0xa7] = 0x00;
451 pci_conf[0xa8] = 0x0f;
452 pci_conf[0xaa] = 0x00;
453 pci_conf[0xab] = 0x00;
454 pci_conf[0xac] = 0x00;
455 pci_conf[0xae] = 0x00;
456
457 d->pic_levels = 0;
458 d->rcr = 0;
459}
460
461static int piix3_post_load(void *opaque, int version_id)
462{
463 PIIX3State *piix3 = opaque;
464 piix3_update_irq_levels(piix3);
465 return 0;
466}
467
468static void piix3_pre_save(void *opaque)
469{
470 int i;
471 PIIX3State *piix3 = opaque;
472
473 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
474 piix3->pci_irq_levels_vmstate[i] =
475 pci_bus_get_irq_level(piix3->dev.bus, i);
476 }
477}
478
479static bool piix3_rcr_needed(void *opaque)
480{
481 PIIX3State *piix3 = opaque;
482
483 return (piix3->rcr != 0);
484}
485
486static const VMStateDescription vmstate_piix3_rcr = {
487 .name = "PIIX3/rcr",
488 .version_id = 1,
489 .minimum_version_id = 1,
490 .fields = (VMStateField []) {
491 VMSTATE_UINT8(rcr, PIIX3State),
492 VMSTATE_END_OF_LIST()
493 }
494};
495
496static const VMStateDescription vmstate_piix3 = {
497 .name = "PIIX3",
498 .version_id = 3,
499 .minimum_version_id = 2,
500 .minimum_version_id_old = 2,
501 .post_load = piix3_post_load,
502 .pre_save = piix3_pre_save,
503 .fields = (VMStateField[]) {
504 VMSTATE_PCI_DEVICE(dev, PIIX3State),
505 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
506 PIIX_NUM_PIRQS, 3),
507 VMSTATE_END_OF_LIST()
508 },
509 .subsections = (VMStateSubsection[]) {
510 {
511 .vmsd = &vmstate_piix3_rcr,
512 .needed = piix3_rcr_needed,
513 },
514 { 0 }
515 }
516};
517
518
519static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
520{
521 PIIX3State *d = opaque;
522
523 if (val & 4) {
524 qemu_system_reset_request();
525 return;
526 }
527 d->rcr = val & 2;
528}
529
530static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
531{
532 PIIX3State *d = opaque;
533
534 return d->rcr;
535}
536
537static const MemoryRegionOps rcr_ops = {
538 .read = rcr_read,
539 .write = rcr_write,
540 .endianness = DEVICE_LITTLE_ENDIAN
541};
542
543static int piix3_initfn(PCIDevice *dev)
544{
545 PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
546
547 isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
548
549 memory_region_init_io(&d->rcr_mem, &rcr_ops, d, "piix3-reset-control", 1);
550 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
551 &d->rcr_mem, 1);
552
553 qemu_register_reset(piix3_reset, d);
554 return 0;
555}
556
557static void piix3_class_init(ObjectClass *klass, void *data)
558{
559 DeviceClass *dc = DEVICE_CLASS(klass);
560 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
561
562 dc->desc = "ISA bridge";
563 dc->vmsd = &vmstate_piix3;
564 dc->no_user = 1,
565 k->no_hotplug = 1;
566 k->init = piix3_initfn;
567 k->config_write = piix3_write_config;
568 k->vendor_id = PCI_VENDOR_ID_INTEL;
569 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
570 k->class_id = PCI_CLASS_BRIDGE_ISA;
571}
572
573static const TypeInfo piix3_info = {
574 .name = "PIIX3",
575 .parent = TYPE_PCI_DEVICE,
576 .instance_size = sizeof(PIIX3State),
577 .class_init = piix3_class_init,
578};
579
580static void piix3_xen_class_init(ObjectClass *klass, void *data)
581{
582 DeviceClass *dc = DEVICE_CLASS(klass);
583 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
584
585 dc->desc = "ISA bridge";
586 dc->vmsd = &vmstate_piix3;
587 dc->no_user = 1;
588 k->no_hotplug = 1;
589 k->init = piix3_initfn;
590 k->config_write = piix3_write_config_xen;
591 k->vendor_id = PCI_VENDOR_ID_INTEL;
592 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
593 k->class_id = PCI_CLASS_BRIDGE_ISA;
594};
595
596static const TypeInfo piix3_xen_info = {
597 .name = "PIIX3-xen",
598 .parent = TYPE_PCI_DEVICE,
599 .instance_size = sizeof(PIIX3State),
600 .class_init = piix3_xen_class_init,
601};
602
603static void i440fx_class_init(ObjectClass *klass, void *data)
604{
605 DeviceClass *dc = DEVICE_CLASS(klass);
606 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
607
608 k->no_hotplug = 1;
609 k->init = i440fx_initfn;
610 k->config_write = i440fx_write_config;
611 k->vendor_id = PCI_VENDOR_ID_INTEL;
612 k->device_id = PCI_DEVICE_ID_INTEL_82441;
613 k->revision = 0x02;
614 k->class_id = PCI_CLASS_BRIDGE_HOST;
615 dc->desc = "Host bridge";
616 dc->no_user = 1;
617 dc->vmsd = &vmstate_i440fx;
618}
619
620static const TypeInfo i440fx_info = {
621 .name = "i440FX",
622 .parent = TYPE_PCI_DEVICE,
623 .instance_size = sizeof(PCII440FXState),
624 .class_init = i440fx_class_init,
625};
626
627static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
628{
629 DeviceClass *dc = DEVICE_CLASS(klass);
630 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
631
632 k->init = i440fx_pcihost_initfn;
633 dc->fw_name = "pci";
634 dc->no_user = 1;
635}
636
637static const TypeInfo i440fx_pcihost_info = {
638 .name = "i440FX-pcihost",
639 .parent = TYPE_PCI_HOST_BRIDGE,
640 .instance_size = sizeof(I440FXState),
641 .class_init = i440fx_pcihost_class_init,
642};
643
644static void i440fx_register_types(void)
645{
646 type_register_static(&i440fx_info);
647 type_register_static(&piix3_info);
648 type_register_static(&piix3_xen_info);
649 type_register_static(&i440fx_pcihost_info);
650}
651
652type_init(i440fx_register_types)
653
