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10#include "hw.h"
11#include "sysbus.h"
12#include "pxa.h"
13
14#define PXA2XX_GPIO_BANKS 4
15
16typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
17struct PXA2xxGPIOInfo {
18 SysBusDevice busdev;
19 MemoryRegion iomem;
20 qemu_irq irq0, irq1, irqX;
21 int lines;
22 int ncpu;
23 ARMCPU *cpu;
24
25
26 uint32_t ilevel[PXA2XX_GPIO_BANKS];
27 uint32_t olevel[PXA2XX_GPIO_BANKS];
28 uint32_t dir[PXA2XX_GPIO_BANKS];
29 uint32_t rising[PXA2XX_GPIO_BANKS];
30 uint32_t falling[PXA2XX_GPIO_BANKS];
31 uint32_t status[PXA2XX_GPIO_BANKS];
32 uint32_t gpsr[PXA2XX_GPIO_BANKS];
33 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
34
35 uint32_t prev_level[PXA2XX_GPIO_BANKS];
36 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
37 qemu_irq read_notify;
38};
39
40static struct {
41 enum {
42 GPIO_NONE,
43 GPLR,
44 GPSR,
45 GPCR,
46 GPDR,
47 GRER,
48 GFER,
49 GEDR,
50 GAFR_L,
51 GAFR_U,
52 } reg;
53 int bank;
54} pxa2xx_gpio_regs[0x200] = {
55 [0 ... 0x1ff] = { GPIO_NONE, 0 },
56#define PXA2XX_REG(reg, a0, a1, a2, a3) \
57 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
58
59 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
60 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
61 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
62 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
63 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
64 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
65 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
66 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
67 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
68};
69
70static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
71{
72 if (s->status[0] & (1 << 0))
73 qemu_irq_raise(s->irq0);
74 else
75 qemu_irq_lower(s->irq0);
76
77 if (s->status[0] & (1 << 1))
78 qemu_irq_raise(s->irq1);
79 else
80 qemu_irq_lower(s->irq1);
81
82 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
83 qemu_irq_raise(s->irqX);
84 else
85 qemu_irq_lower(s->irqX);
86}
87
88
89static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
90 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
91};
92
93static void pxa2xx_gpio_set(void *opaque, int line, int level)
94{
95 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
96 int bank;
97 uint32_t mask;
98
99 if (line >= s->lines) {
100 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
101 return;
102 }
103
104 bank = line >> 5;
105 mask = 1 << (line & 31);
106
107 if (level) {
108 s->status[bank] |= s->rising[bank] & mask &
109 ~s->ilevel[bank] & ~s->dir[bank];
110 s->ilevel[bank] |= mask;
111 } else {
112 s->status[bank] |= s->falling[bank] & mask &
113 s->ilevel[bank] & ~s->dir[bank];
114 s->ilevel[bank] &= ~mask;
115 }
116
117 if (s->status[bank] & mask)
118 pxa2xx_gpio_irq_update(s);
119
120
121 if (s->cpu->env.halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
122 cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_EXITTB);
123 }
124}
125
126static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
127 uint32_t level, diff;
128 int i, bit, line;
129 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
130 level = s->olevel[i] & s->dir[i];
131
132 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
133 bit = ffs(diff) - 1;
134 line = bit + 32 * i;
135 qemu_set_irq(s->handler[line], (level >> bit) & 1);
136 }
137
138 s->prev_level[i] = level;
139 }
140}
141
142static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
143 unsigned size)
144{
145 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
146 uint32_t ret;
147 int bank;
148 if (offset >= 0x200)
149 return 0;
150
151 bank = pxa2xx_gpio_regs[offset].bank;
152 switch (pxa2xx_gpio_regs[offset].reg) {
153 case GPDR:
154 return s->dir[bank];
155
156 case GPSR:
157 printf("%s: Read from a write-only register " REG_FMT "\n",
158 __FUNCTION__, offset);
159 return s->gpsr[bank];
160
161 case GPCR:
162 printf("%s: Read from a write-only register " REG_FMT "\n",
163 __FUNCTION__, offset);
164 return 31337;
165
166 case GRER:
167 return s->rising[bank];
168
169 case GFER:
170 return s->falling[bank];
171
172 case GAFR_L:
173 return s->gafr[bank * 2];
174
175 case GAFR_U:
176 return s->gafr[bank * 2 + 1];
177
178 case GPLR:
179 ret = (s->olevel[bank] & s->dir[bank]) |
180 (s->ilevel[bank] & ~s->dir[bank]);
181 qemu_irq_raise(s->read_notify);
182 return ret;
183
184 case GEDR:
185 return s->status[bank];
186
187 default:
188 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
189 }
190
191 return 0;
192}
193
194static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
195 uint64_t value, unsigned size)
196{
197 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
198 int bank;
199 if (offset >= 0x200)
200 return;
201
202 bank = pxa2xx_gpio_regs[offset].bank;
203 switch (pxa2xx_gpio_regs[offset].reg) {
204 case GPDR:
205 s->dir[bank] = value;
206 pxa2xx_gpio_handler_update(s);
207 break;
208
209 case GPSR:
210 s->olevel[bank] |= value;
211 pxa2xx_gpio_handler_update(s);
212 s->gpsr[bank] = value;
213 break;
214
215 case GPCR:
216 s->olevel[bank] &= ~value;
217 pxa2xx_gpio_handler_update(s);
218 break;
219
220 case GRER:
221 s->rising[bank] = value;
222 break;
223
224 case GFER:
225 s->falling[bank] = value;
226 break;
227
228 case GAFR_L:
229 s->gafr[bank * 2] = value;
230 break;
231
232 case GAFR_U:
233 s->gafr[bank * 2 + 1] = value;
234 break;
235
236 case GEDR:
237 s->status[bank] &= ~value;
238 pxa2xx_gpio_irq_update(s);
239 break;
240
241 default:
242 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
243 }
244}
245
246static const MemoryRegionOps pxa_gpio_ops = {
247 .read = pxa2xx_gpio_read,
248 .write = pxa2xx_gpio_write,
249 .endianness = DEVICE_NATIVE_ENDIAN,
250};
251
252DeviceState *pxa2xx_gpio_init(hwaddr base,
253 ARMCPU *cpu, DeviceState *pic, int lines)
254{
255 CPUState *cs = CPU(cpu);
256 DeviceState *dev;
257
258 dev = qdev_create(NULL, "pxa2xx-gpio");
259 qdev_prop_set_int32(dev, "lines", lines);
260 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
261 qdev_init_nofail(dev);
262
263 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
264 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
265 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
266 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
267 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
268 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
269 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
270
271 return dev;
272}
273
274static int pxa2xx_gpio_initfn(SysBusDevice *dev)
275{
276 PXA2xxGPIOInfo *s;
277
278 s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
279
280 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
281
282 qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
283 qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
284
285 memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
286 sysbus_init_mmio(dev, &s->iomem);
287 sysbus_init_irq(dev, &s->irq0);
288 sysbus_init_irq(dev, &s->irq1);
289 sysbus_init_irq(dev, &s->irqX);
290
291 return 0;
292}
293
294
295
296
297
298void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
299{
300 PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
301 s->read_notify = handler;
302}
303
304static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
305 .name = "pxa2xx-gpio",
306 .version_id = 1,
307 .minimum_version_id = 1,
308 .minimum_version_id_old = 1,
309 .fields = (VMStateField []) {
310 VMSTATE_INT32(lines, PXA2xxGPIOInfo),
311 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
312 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
313 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
314 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
315 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
316 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
317 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
318 VMSTATE_END_OF_LIST(),
319 },
320};
321
322static Property pxa2xx_gpio_properties[] = {
323 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
324 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
325 DEFINE_PROP_END_OF_LIST(),
326};
327
328static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
329{
330 DeviceClass *dc = DEVICE_CLASS(klass);
331 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
332
333 k->init = pxa2xx_gpio_initfn;
334 dc->desc = "PXA2xx GPIO controller";
335 dc->props = pxa2xx_gpio_properties;
336}
337
338static const TypeInfo pxa2xx_gpio_info = {
339 .name = "pxa2xx-gpio",
340 .parent = TYPE_SYS_BUS_DEVICE,
341 .instance_size = sizeof(PXA2xxGPIOInfo),
342 .class_init = pxa2xx_gpio_class_init,
343};
344
345static void pxa2xx_gpio_register_types(void)
346{
347 type_register_static(&pxa2xx_gpio_info);
348}
349
350type_init(pxa2xx_gpio_register_types)
351
