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26#include <hw/hw.h>
27#include <hw/pc.h>
28#include <hw/pci/pci.h>
29#include <hw/isa.h>
30#include "block/block.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/dma.h"
33
34#include <hw/ide/pci.h>
35
36static uint64_t bmdma_read(void *opaque, hwaddr addr,
37 unsigned size)
38{
39 BMDMAState *bm = opaque;
40 uint32_t val;
41
42 if (size != 1) {
43 return ((uint64_t)1 << (size * 8)) - 1;
44 }
45
46 switch (addr & 3) {
47 case 0:
48 val = bm->cmd;
49 break;
50 case 2:
51 val = bm->status;
52 break;
53 default:
54 val = 0xff;
55 break;
56 }
57#ifdef DEBUG_IDE
58 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
59#endif
60 return val;
61}
62
63static void bmdma_write(void *opaque, hwaddr addr,
64 uint64_t val, unsigned size)
65{
66 BMDMAState *bm = opaque;
67
68 if (size != 1) {
69 return;
70 }
71
72#ifdef DEBUG_IDE
73 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
74#endif
75 switch (addr & 3) {
76 case 0:
77 bmdma_cmd_writeb(bm, val);
78 break;
79 case 2:
80 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
81 break;
82 default:;
83 }
84}
85
86static const MemoryRegionOps via_bmdma_ops = {
87 .read = bmdma_read,
88 .write = bmdma_write,
89};
90
91static void bmdma_setup_bar(PCIIDEState *d)
92{
93 int i;
94
95 memory_region_init(&d->bmdma_bar, "via-bmdma-container", 16);
96 for(i = 0;i < 2; i++) {
97 BMDMAState *bm = &d->bmdma[i];
98
99 memory_region_init_io(&bm->extra_io, &via_bmdma_ops, bm,
100 "via-bmdma", 4);
101 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
102 memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
103 "bmdma", 4);
104 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
105 }
106}
107
108static void via_reset(void *opaque)
109{
110 PCIIDEState *d = opaque;
111 uint8_t *pci_conf = d->dev.config;
112 int i;
113
114 for (i = 0; i < 2; i++) {
115 ide_bus_reset(&d->bus[i]);
116 }
117
118 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
119 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
120 PCI_STATUS_DEVSEL_MEDIUM);
121
122 pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
123 pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
124 pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
125 pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
126 pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01);
127 pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
128
129
130 pci_set_long(pci_conf + 0x40, 0x0a090600);
131
132 pci_set_long(pci_conf + 0x44, 0x00c00068);
133
134 pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
135
136 pci_set_long(pci_conf + 0x4c, 0x000000ff);
137
138 pci_set_long(pci_conf + 0x50, 0x07070707);
139
140 pci_set_long(pci_conf + 0x54, 0x00000004);
141
142 pci_set_long(pci_conf + 0x60, 0x00000200);
143
144 pci_set_long(pci_conf + 0x68, 0x00000200);
145
146 pci_set_long(pci_conf + 0xc0, 0x00020001);
147}
148
149static void vt82c686b_init_ports(PCIIDEState *d) {
150 static const struct {
151 int iobase;
152 int iobase2;
153 int isairq;
154 } port_info[] = {
155 {0x1f0, 0x3f6, 14},
156 {0x170, 0x376, 15},
157 };
158 int i;
159
160 for (i = 0; i < 2; i++) {
161 ide_bus_new(&d->bus[i], &d->dev.qdev, i);
162 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
163 port_info[i].iobase2);
164 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
165
166 bmdma_init(&d->bus[i], &d->bmdma[i], d);
167 d->bmdma[i].bus = &d->bus[i];
168 qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
169 &d->bmdma[i].dma);
170 }
171}
172
173
174static int vt82c686b_ide_initfn(PCIDevice *dev)
175{
176 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
177 uint8_t *pci_conf = d->dev.config;
178
179 pci_config_set_prog_interface(pci_conf, 0x8a);
180 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
181
182 qemu_register_reset(via_reset, d);
183 bmdma_setup_bar(d);
184 pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
185
186 vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
187
188 vt82c686b_init_ports(d);
189
190 return 0;
191}
192
193static void vt82c686b_ide_exitfn(PCIDevice *dev)
194{
195 PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
196 unsigned i;
197
198 for (i = 0; i < 2; ++i) {
199 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
200 memory_region_destroy(&d->bmdma[i].extra_io);
201 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
202 memory_region_destroy(&d->bmdma[i].addr_ioport);
203 }
204 memory_region_destroy(&d->bmdma_bar);
205}
206
207void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
208{
209 PCIDevice *dev;
210
211 dev = pci_create_simple(bus, devfn, "via-ide");
212 pci_ide_create_devs(dev, hd_table);
213}
214
215static void via_ide_class_init(ObjectClass *klass, void *data)
216{
217 DeviceClass *dc = DEVICE_CLASS(klass);
218 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
219
220 k->init = vt82c686b_ide_initfn;
221 k->exit = vt82c686b_ide_exitfn;
222 k->vendor_id = PCI_VENDOR_ID_VIA;
223 k->device_id = PCI_DEVICE_ID_VIA_IDE;
224 k->revision = 0x06;
225 k->class_id = PCI_CLASS_STORAGE_IDE;
226 dc->no_user = 1;
227}
228
229static const TypeInfo via_ide_info = {
230 .name = "via-ide",
231 .parent = TYPE_PCI_DEVICE,
232 .instance_size = sizeof(PCIIDEState),
233 .class_init = via_ide_class_init,
234};
235
236static void via_ide_register_types(void)
237{
238 type_register_static(&via_ide_info);
239}
240
241type_init(via_ide_register_types)
242
